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clk: renesas: r9a07g043: Add USB clocks/resets

Add clock/reset entries for USB PHY control, USB2.0 host and device.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Biju Das and committed by
Geert Uytterhoeven
666b5a01 be5b5fcb

+12
+12
drivers/clk/renesas/r9a07g043-cpg.c
··· 160 160 0x570, 6), 161 161 DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 162 162 0x570, 7), 163 + DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 164 + 0x578, 0), 165 + DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 166 + 0x578, 1), 167 + DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 168 + 0x578, 2), 169 + DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 170 + 0x578, 3), 163 171 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 164 172 0x57c, 0), 165 173 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, ··· 214 206 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), 215 207 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), 216 208 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), 209 + DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), 210 + DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), 211 + DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), 212 + DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), 217 213 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), 218 214 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), 219 215 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),