Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Program the VDR PLL registers for LT PHY
Fetch the tables which need to be used and program it in
the specified VDR register space. Everything is done over
the respective lanes.
Bspec: 68862, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
+45
-5
+2
-5
drivers/gpu/drm/i915/display/intel_cx0_phy.c
+2
-5
drivers/gpu/drm/i915/display/intel_cx0_phy.c
···
23
23
#include "intel_snps_hdmi_pll.h"
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24
#include "intel_tc.h"
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-
#define MB_WRITE_COMMITTED true
27
-
#define MB_WRITE_UNCOMMITTED false
28
-
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#define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
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27
for ((__lane) = 0; (__lane) < 2; (__lane)++) \
31
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for_each_if((__lane_mask) & BIT(__lane))
···
355
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"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
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}
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-
static void intel_cx0_write(struct intel_encoder *encoder,
359
-
u8 lane_mask, u16 addr, u8 data, bool committed)
361
+
void intel_cx0_write(struct intel_encoder *encoder,
362
+
u8 lane_mask, u16 addr, u8 data, bool committed)
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{
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int lane;
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+5
drivers/gpu/drm/i915/display/intel_cx0_phy.h
+5
drivers/gpu/drm/i915/display/intel_cx0_phy.h
···
8
8
9
9
#include <linux/types.h>
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10
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+
#define MB_WRITE_COMMITTED true
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+
#define MB_WRITE_UNCOMMITTED false
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+
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enum icl_port_dpll_id;
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struct intel_atomic_state;
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16
struct intel_c10pll_state;
···
50
47
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
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bool intel_cx0_is_hdmi_frl(u32 clock);
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u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr);
50
+
void intel_cx0_write(struct intel_encoder *encoder,
51
+
u8 lane_mask, u16 addr, u8 data, bool committed);
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int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
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void intel_cx0_pll_power_save_wa(struct intel_display *display);
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void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
+38
drivers/gpu/drm/i915/display/intel_lt_phy.c
+38
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
992
992
return intel_cx0_read(encoder, lane_mask, addr);
993
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}
994
994
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+
static void intel_lt_phy_write(struct intel_encoder *encoder,
996
+
u8 lane_mask, u16 addr, u8 data, bool committed)
997
+
{
998
+
intel_cx0_write(encoder, lane_mask, addr, data, committed);
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+
}
1000
+
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static void
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intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count)
997
1003
{
···
1234
1228
return -EINVAL;
1235
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}
1236
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+
static void
1232
+
intel_lt_phy_program_pll(struct intel_encoder *encoder,
1233
+
const struct intel_crtc_state *crtc_state)
1234
+
{
1235
+
u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
1236
+
int i, j, k;
1237
+
1238
+
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG,
1239
+
crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED);
1240
+
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG,
1241
+
crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED);
1242
+
intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG,
1243
+
crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED);
1244
+
1245
+
for (i = 0; i <= 12; i++) {
1246
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intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i),
1247
+
crtc_state->dpll_hw_state.ltpll.addr_msb[i],
1248
+
MB_WRITE_COMMITTED);
1249
+
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i),
1250
+
crtc_state->dpll_hw_state.ltpll.addr_lsb[i],
1251
+
MB_WRITE_COMMITTED);
1252
+
1253
+
for (j = 3, k = 0; j >= 0; j--, k++)
1254
+
intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0,
1255
+
LT_PHY_VDR_X_DATAY(i, j),
1256
+
crtc_state->dpll_hw_state.ltpll.data[i][k],
1257
+
MB_WRITE_COMMITTED);
1258
+
}
1259
+
}
1260
+
1237
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void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
1238
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const struct intel_crtc_state *crtc_state)
1239
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{
···
1294
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* 5. Program the PHY internal PLL registers over PHY message bus for the desired
1295
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* frequency and protocol type
1296
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*/
1261
+
intel_lt_phy_program_pll(encoder, crtc_state);
1262
+
1297
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/* 6. Use the P2P transaction flow */
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/*
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* 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message