Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Add LT Phy Programming recipe tables
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.
Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
+1036
-1
+28
-1
drivers/gpu/drm/i915/display/intel_dpll.c
+28
-1
drivers/gpu/drm/i915/display/intel_dpll.c
···
17
17
#include "intel_display_types.h"
18
18
#include "intel_dpio_phy.h"
19
19
#include "intel_dpll.h"
20
+
#include "intel_lt_phy.h"
20
21
#include "intel_lvds.h"
21
22
#include "intel_lvds_regs.h"
22
23
#include "intel_panel.h"
···
1233
1232
return 0;
1234
1233
}
1235
1234
1235
+
static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
1236
+
struct intel_crtc *crtc)
1237
+
{
1238
+
struct intel_crtc_state *crtc_state =
1239
+
intel_atomic_get_new_crtc_state(state, crtc);
1240
+
struct intel_encoder *encoder =
1241
+
intel_get_crtc_new_encoder(state, crtc_state);
1242
+
int ret;
1243
+
1244
+
ret = intel_lt_phy_pll_calc_state(crtc_state, encoder);
1245
+
if (ret)
1246
+
return ret;
1247
+
1248
+
/* TODO: Do the readback via intel_compute_shared_dplls() */
1249
+
1250
+
crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1251
+
1252
+
return 0;
1253
+
}
1254
+
1236
1255
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
1237
1256
{
1238
1257
struct intel_display *display = to_intel_display(crtc_state);
···
1712
1691
return 0;
1713
1692
}
1714
1693
1694
+
static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
1695
+
.crtc_compute_clock = xe3plpd_crtc_compute_clock,
1696
+
};
1697
+
1715
1698
static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
1716
1699
.crtc_compute_clock = mtl_crtc_compute_clock,
1717
1700
};
···
1814
1789
void
1815
1790
intel_dpll_init_clock_hook(struct intel_display *display)
1816
1791
{
1817
-
if (DISPLAY_VER(display) >= 14)
1792
+
if (HAS_LT_PHY(display))
1793
+
display->funcs.dpll = &xe3plpd_dpll_funcs;
1794
+
else if (DISPLAY_VER(display) >= 14)
1818
1795
display->funcs.dpll = &mtl_dpll_funcs;
1819
1796
else if (display->platform.dg2)
1820
1797
display->funcs.dpll = &dg2_dpll_funcs;
+11
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+11
drivers/gpu/drm/i915/display/intel_dpll_mgr.h
···
267
267
bool tbt_mode;
268
268
};
269
269
270
+
struct intel_lt_phy_pll_state {
271
+
u32 clock; /* in kHz */
272
+
u8 addr_msb[13];
273
+
u8 addr_lsb[13];
274
+
u8 data[13][4];
275
+
u8 config[3];
276
+
bool ssc_enabled;
277
+
bool tbt_mode;
278
+
};
279
+
270
280
struct intel_dpll_hw_state {
271
281
union {
272
282
struct i9xx_dpll_hw_state i9xx;
···
286
276
struct icl_dpll_hw_state icl;
287
277
struct intel_mpllb_state mpllb;
288
278
struct intel_cx0pll_state cx0pll;
279
+
struct intel_lt_phy_pll_state ltpll;
289
280
};
290
281
};
291
282
+992
drivers/gpu/drm/i915/display/intel_lt_phy.c
+992
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
12
12
#include "intel_de.h"
13
13
#include "intel_display.h"
14
14
#include "intel_display_types.h"
15
+
#include "intel_dpll_mgr.h"
15
16
#include "intel_hdmi.h"
16
17
#include "intel_lt_phy.h"
17
18
#include "intel_lt_phy_regs.h"
···
24
23
#define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\
25
24
INTEL_LT_PHY_LANE0)
26
25
#define MODE_DP 3
26
+
27
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = {
28
+
.clock = 162000,
29
+
.config = {
30
+
0x83,
31
+
0x2d,
32
+
0x0,
33
+
},
34
+
.addr_msb = {
35
+
0x87,
36
+
0x87,
37
+
0x87,
38
+
0x87,
39
+
0x88,
40
+
0x88,
41
+
0x88,
42
+
0x88,
43
+
0x88,
44
+
0x88,
45
+
0x88,
46
+
0x88,
47
+
0x88,
48
+
},
49
+
.addr_lsb = {
50
+
0x10,
51
+
0x0c,
52
+
0x14,
53
+
0xe4,
54
+
0x0c,
55
+
0x10,
56
+
0x14,
57
+
0x18,
58
+
0x48,
59
+
0x40,
60
+
0x4c,
61
+
0x24,
62
+
0x44,
63
+
},
64
+
.data = {
65
+
{ 0x0, 0x4c, 0x2, 0x0 },
66
+
{ 0x5, 0xa, 0x2a, 0x20 },
67
+
{ 0x80, 0x0, 0x0, 0x0 },
68
+
{ 0x4, 0x4, 0x82, 0x28 },
69
+
{ 0xfa, 0x16, 0x83, 0x11 },
70
+
{ 0x80, 0x0f, 0xf9, 0x53 },
71
+
{ 0x84, 0x26, 0x5, 0x4 },
72
+
{ 0x0, 0xe0, 0x1, 0x0 },
73
+
{ 0x4b, 0x48, 0x0, 0x0 },
74
+
{ 0x27, 0x8, 0x0, 0x0 },
75
+
{ 0x5a, 0x13, 0x29, 0x13 },
76
+
{ 0x0, 0x5b, 0xe0, 0x0a },
77
+
{ 0x0, 0x0, 0x0, 0x0 },
78
+
},
79
+
};
80
+
81
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = {
82
+
.clock = 270000,
83
+
.config = {
84
+
0x8b,
85
+
0x2d,
86
+
0x0,
87
+
},
88
+
.addr_msb = {
89
+
0x87,
90
+
0x87,
91
+
0x87,
92
+
0x87,
93
+
0x88,
94
+
0x88,
95
+
0x88,
96
+
0x88,
97
+
0x88,
98
+
0x88,
99
+
0x88,
100
+
0x88,
101
+
0x88,
102
+
},
103
+
.addr_lsb = {
104
+
0x10,
105
+
0x0c,
106
+
0x14,
107
+
0xe4,
108
+
0x0c,
109
+
0x10,
110
+
0x14,
111
+
0x18,
112
+
0x48,
113
+
0x40,
114
+
0x4c,
115
+
0x24,
116
+
0x44,
117
+
},
118
+
.data = {
119
+
{ 0x0, 0x4c, 0x2, 0x0 },
120
+
{ 0x3, 0xca, 0x34, 0xa0 },
121
+
{ 0xe0, 0x0, 0x0, 0x0 },
122
+
{ 0x5, 0x4, 0x81, 0xad },
123
+
{ 0xfa, 0x11, 0x83, 0x11 },
124
+
{ 0x80, 0x0f, 0xf9, 0x53 },
125
+
{ 0x84, 0x26, 0x7, 0x4 },
126
+
{ 0x0, 0xe0, 0x1, 0x0 },
127
+
{ 0x43, 0x48, 0x0, 0x0 },
128
+
{ 0x27, 0x8, 0x0, 0x0 },
129
+
{ 0x5a, 0x13, 0x29, 0x13 },
130
+
{ 0x0, 0x5b, 0xe0, 0x0d },
131
+
{ 0x0, 0x0, 0x0, 0x0 },
132
+
},
133
+
};
134
+
135
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = {
136
+
.clock = 540000,
137
+
.config = {
138
+
0x93,
139
+
0x2d,
140
+
0x0,
141
+
},
142
+
.addr_msb = {
143
+
0x87,
144
+
0x87,
145
+
0x87,
146
+
0x87,
147
+
0x88,
148
+
0x88,
149
+
0x88,
150
+
0x88,
151
+
0x88,
152
+
0x88,
153
+
0x88,
154
+
0x88,
155
+
0x88,
156
+
},
157
+
.addr_lsb = {
158
+
0x10,
159
+
0x0c,
160
+
0x14,
161
+
0xe4,
162
+
0x0c,
163
+
0x10,
164
+
0x14,
165
+
0x18,
166
+
0x48,
167
+
0x40,
168
+
0x4c,
169
+
0x24,
170
+
0x44,
171
+
},
172
+
.data = {
173
+
{ 0x0, 0x4c, 0x2, 0x0 },
174
+
{ 0x1, 0x4d, 0x34, 0xa0 },
175
+
{ 0xe0, 0x0, 0x0, 0x0 },
176
+
{ 0xa, 0x4, 0x81, 0xda },
177
+
{ 0xfa, 0x11, 0x83, 0x11 },
178
+
{ 0x80, 0x0f, 0xf9, 0x53 },
179
+
{ 0x84, 0x26, 0x7, 0x4 },
180
+
{ 0x0, 0xe0, 0x1, 0x0 },
181
+
{ 0x43, 0x48, 0x0, 0x0 },
182
+
{ 0x27, 0x8, 0x0, 0x0 },
183
+
{ 0x5a, 0x13, 0x29, 0x13 },
184
+
{ 0x0, 0x5b, 0xe0, 0x0d },
185
+
{ 0x0, 0x0, 0x0, 0x0 },
186
+
},
187
+
};
188
+
189
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = {
190
+
.clock = 810000,
191
+
.config = {
192
+
0x9b,
193
+
0x2d,
194
+
0x0,
195
+
},
196
+
.addr_msb = {
197
+
0x87,
198
+
0x87,
199
+
0x87,
200
+
0x87,
201
+
0x88,
202
+
0x88,
203
+
0x88,
204
+
0x88,
205
+
0x88,
206
+
0x88,
207
+
0x88,
208
+
0x88,
209
+
0x88,
210
+
},
211
+
.addr_lsb = {
212
+
0x10,
213
+
0x0c,
214
+
0x14,
215
+
0xe4,
216
+
0x0c,
217
+
0x10,
218
+
0x14,
219
+
0x18,
220
+
0x48,
221
+
0x40,
222
+
0x4c,
223
+
0x24,
224
+
0x44,
225
+
},
226
+
.data = {
227
+
{ 0x0, 0x4c, 0x2, 0x0 },
228
+
{ 0x1, 0x4a, 0x34, 0xa0 },
229
+
{ 0xe0, 0x0, 0x0, 0x0 },
230
+
{ 0x5, 0x4, 0x80, 0xa8 },
231
+
{ 0xfa, 0x11, 0x83, 0x11 },
232
+
{ 0x80, 0x0f, 0xf9, 0x53 },
233
+
{ 0x84, 0x26, 0x7, 0x4 },
234
+
{ 0x0, 0xe0, 0x1, 0x0 },
235
+
{ 0x43, 0x48, 0x0, 0x0 },
236
+
{ 0x27, 0x8, 0x0, 0x0 },
237
+
{ 0x5a, 0x13, 0x29, 0x13 },
238
+
{ 0x0, 0x5b, 0xe0, 0x0d },
239
+
{ 0x0, 0x0, 0x0, 0x0 },
240
+
},
241
+
};
242
+
243
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = {
244
+
.clock = 1000000,
245
+
.config = {
246
+
0x43,
247
+
0x2d,
248
+
0x0,
249
+
},
250
+
.addr_msb = {
251
+
0x85,
252
+
0x85,
253
+
0x85,
254
+
0x85,
255
+
0x86,
256
+
0x86,
257
+
0x86,
258
+
0x86,
259
+
0x86,
260
+
0x86,
261
+
0x86,
262
+
0x86,
263
+
0x86,
264
+
},
265
+
.addr_lsb = {
266
+
0x10,
267
+
0x0c,
268
+
0x14,
269
+
0xe4,
270
+
0x0c,
271
+
0x10,
272
+
0x14,
273
+
0x18,
274
+
0x48,
275
+
0x40,
276
+
0x4c,
277
+
0x24,
278
+
0x44,
279
+
},
280
+
.data = {
281
+
{ 0x0, 0x4c, 0x2, 0x0 },
282
+
{ 0x1, 0xa, 0x20, 0x80 },
283
+
{ 0x6a, 0xaa, 0xaa, 0xab },
284
+
{ 0x0, 0x3, 0x4, 0x94 },
285
+
{ 0xfa, 0x1c, 0x83, 0x11 },
286
+
{ 0x80, 0x0f, 0xf9, 0x53 },
287
+
{ 0x84, 0x26, 0x4, 0x4 },
288
+
{ 0x0, 0xe0, 0x1, 0x0 },
289
+
{ 0x45, 0x48, 0x0, 0x0 },
290
+
{ 0x27, 0x8, 0x0, 0x0 },
291
+
{ 0x5a, 0x14, 0x2a, 0x14 },
292
+
{ 0x0, 0x5b, 0xe0, 0x8 },
293
+
{ 0x0, 0x0, 0x0, 0x0 },
294
+
},
295
+
};
296
+
297
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = {
298
+
.clock = 1350000,
299
+
.config = {
300
+
0xcb,
301
+
0x2d,
302
+
0x0,
303
+
},
304
+
.addr_msb = {
305
+
0x87,
306
+
0x87,
307
+
0x87,
308
+
0x87,
309
+
0x88,
310
+
0x88,
311
+
0x88,
312
+
0x88,
313
+
0x88,
314
+
0x88,
315
+
0x88,
316
+
0x88,
317
+
0x88,
318
+
},
319
+
.addr_lsb = {
320
+
0x10,
321
+
0x0c,
322
+
0x14,
323
+
0xe4,
324
+
0x0c,
325
+
0x10,
326
+
0x14,
327
+
0x18,
328
+
0x48,
329
+
0x40,
330
+
0x4c,
331
+
0x24,
332
+
0x44,
333
+
},
334
+
.data = {
335
+
{ 0x0, 0x4c, 0x2, 0x0 },
336
+
{ 0x2, 0x9, 0x2b, 0xe0 },
337
+
{ 0x90, 0x0, 0x0, 0x0 },
338
+
{ 0x8, 0x4, 0x80, 0xe0 },
339
+
{ 0xfa, 0x15, 0x83, 0x11 },
340
+
{ 0x80, 0x0f, 0xf9, 0x53 },
341
+
{ 0x84, 0x26, 0x6, 0x4 },
342
+
{ 0x0, 0xe0, 0x1, 0x0 },
343
+
{ 0x49, 0x48, 0x0, 0x0 },
344
+
{ 0x27, 0x8, 0x0, 0x0 },
345
+
{ 0x5a, 0x13, 0x29, 0x13 },
346
+
{ 0x0, 0x57, 0xe0, 0x0c },
347
+
{ 0x0, 0x0, 0x0, 0x0 },
348
+
},
349
+
};
350
+
351
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
352
+
.clock = 2000000,
353
+
.config = {
354
+
0x53,
355
+
0x2d,
356
+
0x0,
357
+
},
358
+
.addr_msb = {
359
+
0x85,
360
+
0x85,
361
+
0x85,
362
+
0x85,
363
+
0x86,
364
+
0x86,
365
+
0x86,
366
+
0x86,
367
+
0x86,
368
+
0x86,
369
+
0x86,
370
+
0x86,
371
+
0x86,
372
+
},
373
+
.addr_lsb = {
374
+
0x10,
375
+
0x0c,
376
+
0x14,
377
+
0xe4,
378
+
0x0c,
379
+
0x10,
380
+
0x14,
381
+
0x18,
382
+
0x48,
383
+
0x40,
384
+
0x4c,
385
+
0x24,
386
+
0x44,
387
+
},
388
+
.data = {
389
+
{ 0x0, 0x4c, 0x2, 0x0 },
390
+
{ 0x1, 0xa, 0x20, 0x80 },
391
+
{ 0x6a, 0xaa, 0xaa, 0xab },
392
+
{ 0x0, 0x3, 0x4, 0x94 },
393
+
{ 0xfa, 0x1c, 0x83, 0x11 },
394
+
{ 0x80, 0x0f, 0xf9, 0x53 },
395
+
{ 0x84, 0x26, 0x4, 0x4 },
396
+
{ 0x0, 0xe0, 0x1, 0x0 },
397
+
{ 0x45, 0x48, 0x0, 0x0 },
398
+
{ 0x27, 0x8, 0x0, 0x0 },
399
+
{ 0x5a, 0x14, 0x2a, 0x14 },
400
+
{ 0x0, 0x5b, 0xe0, 0x8 },
401
+
{ 0x0, 0x0, 0x0, 0x0 },
402
+
},
403
+
};
404
+
405
+
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
406
+
&xe3plpd_lt_dp_rbr,
407
+
&xe3plpd_lt_dp_hbr1,
408
+
&xe3plpd_lt_dp_hbr2,
409
+
&xe3plpd_lt_dp_hbr3,
410
+
&xe3plpd_lt_dp_uhbr10,
411
+
&xe3plpd_lt_dp_uhbr13_5,
412
+
&xe3plpd_lt_dp_uhbr20,
413
+
NULL,
414
+
};
415
+
416
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
417
+
.clock = 216000,
418
+
.config = {
419
+
0xa3,
420
+
0x2d,
421
+
0x1,
422
+
},
423
+
.addr_msb = {
424
+
0x87,
425
+
0x87,
426
+
0x87,
427
+
0x87,
428
+
0x88,
429
+
0x88,
430
+
0x88,
431
+
0x88,
432
+
0x88,
433
+
0x88,
434
+
0x88,
435
+
0x88,
436
+
0x88,
437
+
},
438
+
.addr_lsb = {
439
+
0x10,
440
+
0x0c,
441
+
0x14,
442
+
0xe4,
443
+
0x0c,
444
+
0x10,
445
+
0x14,
446
+
0x18,
447
+
0x48,
448
+
0x40,
449
+
0x4c,
450
+
0x24,
451
+
0x44,
452
+
},
453
+
.data = {
454
+
{ 0x0, 0x4c, 0x2, 0x0 },
455
+
{ 0x3, 0xca, 0x2a, 0x20 },
456
+
{ 0x80, 0x0, 0x0, 0x0 },
457
+
{ 0x6, 0x4, 0x81, 0xbc },
458
+
{ 0xfa, 0x16, 0x83, 0x11 },
459
+
{ 0x80, 0x0f, 0xf9, 0x53 },
460
+
{ 0x84, 0x26, 0x5, 0x4 },
461
+
{ 0x0, 0xe0, 0x1, 0x0 },
462
+
{ 0x4b, 0x48, 0x0, 0x0 },
463
+
{ 0x27, 0x8, 0x0, 0x0 },
464
+
{ 0x5a, 0x13, 0x29, 0x13 },
465
+
{ 0x0, 0x5b, 0xe0, 0x0a },
466
+
{ 0x0, 0x0, 0x0, 0x0 },
467
+
},
468
+
};
469
+
470
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = {
471
+
.clock = 243000,
472
+
.config = {
473
+
0xab,
474
+
0x2d,
475
+
0x1,
476
+
},
477
+
.addr_msb = {
478
+
0x87,
479
+
0x87,
480
+
0x87,
481
+
0x87,
482
+
0x88,
483
+
0x88,
484
+
0x88,
485
+
0x88,
486
+
0x88,
487
+
0x88,
488
+
0x88,
489
+
0x88,
490
+
0x88,
491
+
},
492
+
.addr_lsb = {
493
+
0x10,
494
+
0x0c,
495
+
0x14,
496
+
0xe4,
497
+
0x0c,
498
+
0x10,
499
+
0x14,
500
+
0x18,
501
+
0x48,
502
+
0x40,
503
+
0x4c,
504
+
0x24,
505
+
0x44,
506
+
},
507
+
.data = {
508
+
{ 0x0, 0x4c, 0x2, 0x0 },
509
+
{ 0x3, 0xca, 0x2f, 0x60 },
510
+
{ 0xb0, 0x0, 0x0, 0x0 },
511
+
{ 0x6, 0x4, 0x81, 0xbc },
512
+
{ 0xfa, 0x13, 0x83, 0x11 },
513
+
{ 0x80, 0x0f, 0xf9, 0x53 },
514
+
{ 0x84, 0x26, 0x6, 0x4 },
515
+
{ 0x0, 0xe0, 0x1, 0x0 },
516
+
{ 0x47, 0x48, 0x0, 0x0 },
517
+
{ 0x0, 0x0, 0x0, 0x0 },
518
+
{ 0x5a, 0x13, 0x29, 0x13 },
519
+
{ 0x0, 0x5b, 0xe0, 0x0c },
520
+
{ 0x0, 0x0, 0x0, 0x0 },
521
+
},
522
+
};
523
+
524
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = {
525
+
.clock = 324000,
526
+
.config = {
527
+
0xb3,
528
+
0x2d,
529
+
0x1,
530
+
},
531
+
.addr_msb = {
532
+
0x87,
533
+
0x87,
534
+
0x87,
535
+
0x87,
536
+
0x88,
537
+
0x88,
538
+
0x88,
539
+
0x88,
540
+
0x88,
541
+
0x88,
542
+
0x88,
543
+
0x88,
544
+
0x88,
545
+
},
546
+
.addr_lsb = {
547
+
0x10,
548
+
0x0c,
549
+
0x14,
550
+
0xe4,
551
+
0x0c,
552
+
0x10,
553
+
0x14,
554
+
0x18,
555
+
0x48,
556
+
0x40,
557
+
0x4c,
558
+
0x24,
559
+
0x44,
560
+
},
561
+
.data = {
562
+
{ 0x0, 0x4c, 0x2, 0x0 },
563
+
{ 0x2, 0x8a, 0x2a, 0x20 },
564
+
{ 0x80, 0x0, 0x0, 0x0 },
565
+
{ 0x6, 0x4, 0x81, 0x28 },
566
+
{ 0xfa, 0x16, 0x83, 0x11 },
567
+
{ 0x80, 0x0f, 0xf9, 0x53 },
568
+
{ 0x84, 0x26, 0x5, 0x4 },
569
+
{ 0x0, 0xe0, 0x1, 0x0 },
570
+
{ 0x4b, 0x48, 0x0, 0x0 },
571
+
{ 0x27, 0x8, 0x0, 0x0 },
572
+
{ 0x5a, 0x13, 0x29, 0x13 },
573
+
{ 0x0, 0x5b, 0xe0, 0x0a },
574
+
{ 0x0, 0x0, 0x0, 0x0 },
575
+
},
576
+
};
577
+
578
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = {
579
+
.clock = 432000,
580
+
.config = {
581
+
0xbb,
582
+
0x2d,
583
+
0x1,
584
+
},
585
+
.addr_msb = {
586
+
0x87,
587
+
0x87,
588
+
0x87,
589
+
0x87,
590
+
0x88,
591
+
0x88,
592
+
0x88,
593
+
0x88,
594
+
0x88,
595
+
0x88,
596
+
0x88,
597
+
0x88,
598
+
0x88,
599
+
},
600
+
.addr_lsb = {
601
+
0x10,
602
+
0x0c,
603
+
0x14,
604
+
0xe4,
605
+
0x0c,
606
+
0x10,
607
+
0x14,
608
+
0x18,
609
+
0x48,
610
+
0x40,
611
+
0x4c,
612
+
0x24,
613
+
0x44,
614
+
},
615
+
.data = {
616
+
{ 0x0, 0x4c, 0x2, 0x0 },
617
+
{ 0x1, 0x4d, 0x2a, 0x20 },
618
+
{ 0x80, 0x0, 0x0, 0x0 },
619
+
{ 0xc, 0x4, 0x81, 0xbc },
620
+
{ 0xfa, 0x16, 0x83, 0x11 },
621
+
{ 0x80, 0x0f, 0xf9, 0x53 },
622
+
{ 0x84, 0x26, 0x5, 0x4 },
623
+
{ 0x0, 0xe0, 0x1, 0x0 },
624
+
{ 0x4b, 0x48, 0x0, 0x0 },
625
+
{ 0x27, 0x8, 0x0, 0x0 },
626
+
{ 0x5a, 0x13, 0x29, 0x13 },
627
+
{ 0x0, 0x5b, 0xe0, 0x0a },
628
+
{ 0x0, 0x0, 0x0, 0x0 },
629
+
},
630
+
};
631
+
632
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
633
+
.clock = 675000,
634
+
.config = {
635
+
0xdb,
636
+
0x2d,
637
+
0x1,
638
+
},
639
+
.addr_msb = {
640
+
0x87,
641
+
0x87,
642
+
0x87,
643
+
0x87,
644
+
0x88,
645
+
0x88,
646
+
0x88,
647
+
0x88,
648
+
0x88,
649
+
0x88,
650
+
0x88,
651
+
0x88,
652
+
0x88,
653
+
},
654
+
.addr_lsb = {
655
+
0x10,
656
+
0x0c,
657
+
0x14,
658
+
0xe4,
659
+
0x0c,
660
+
0x10,
661
+
0x14,
662
+
0x18,
663
+
0x48,
664
+
0x40,
665
+
0x4c,
666
+
0x24,
667
+
0x44,
668
+
},
669
+
.data = {
670
+
{ 0x0, 0x4c, 0x2, 0x0 },
671
+
{ 0x1, 0x4a, 0x2b, 0xe0 },
672
+
{ 0x90, 0x0, 0x0, 0x0 },
673
+
{ 0x6, 0x4, 0x80, 0xa8 },
674
+
{ 0xfa, 0x15, 0x83, 0x11 },
675
+
{ 0x80, 0x0f, 0xf9, 0x53 },
676
+
{ 0x84, 0x26, 0x6, 0x4 },
677
+
{ 0x0, 0xe0, 0x1, 0x0 },
678
+
{ 0x49, 0x48, 0x0, 0x0 },
679
+
{ 0x27, 0x8, 0x0, 0x0 },
680
+
{ 0x5a, 0x13, 0x29, 0x13 },
681
+
{ 0x0, 0x57, 0xe0, 0x0c },
682
+
{ 0x0, 0x0, 0x0, 0x0 },
683
+
},
684
+
};
685
+
686
+
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
687
+
&xe3plpd_lt_dp_rbr,
688
+
&xe3plpd_lt_edp_2_16,
689
+
&xe3plpd_lt_edp_2_43,
690
+
&xe3plpd_lt_dp_hbr1,
691
+
&xe3plpd_lt_edp_3_24,
692
+
&xe3plpd_lt_edp_4_32,
693
+
&xe3plpd_lt_dp_hbr2,
694
+
&xe3plpd_lt_edp_6_75,
695
+
&xe3plpd_lt_dp_hbr3,
696
+
NULL,
697
+
};
698
+
699
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
700
+
.clock = 25200,
701
+
.config = {
702
+
0x84,
703
+
0x2d,
704
+
0x0,
705
+
},
706
+
.addr_msb = {
707
+
0x87,
708
+
0x87,
709
+
0x87,
710
+
0x87,
711
+
0x88,
712
+
0x88,
713
+
0x88,
714
+
0x88,
715
+
0x88,
716
+
0x88,
717
+
0x88,
718
+
0x88,
719
+
0x88,
720
+
},
721
+
.addr_lsb = {
722
+
0x10,
723
+
0x0c,
724
+
0x14,
725
+
0xe4,
726
+
0x0c,
727
+
0x10,
728
+
0x14,
729
+
0x18,
730
+
0x48,
731
+
0x40,
732
+
0x4c,
733
+
0x24,
734
+
0x44,
735
+
},
736
+
.data = {
737
+
{ 0x0, 0x4c, 0x2, 0x0 },
738
+
{ 0x0c, 0x15, 0x27, 0x60 },
739
+
{ 0x0, 0x0, 0x0, 0x0 },
740
+
{ 0x8, 0x4, 0x98, 0x28 },
741
+
{ 0x42, 0x0, 0x84, 0x10 },
742
+
{ 0x80, 0x0f, 0xd9, 0xb5 },
743
+
{ 0x86, 0x0, 0x0, 0x0 },
744
+
{ 0x1, 0xa0, 0x1, 0x0 },
745
+
{ 0x4b, 0x0, 0x0, 0x0 },
746
+
{ 0x28, 0x0, 0x0, 0x0 },
747
+
{ 0x0, 0x14, 0x2a, 0x14 },
748
+
{ 0x0, 0x0, 0x0, 0x0 },
749
+
{ 0x0, 0x0, 0x0, 0x0 },
750
+
},
751
+
};
752
+
753
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {
754
+
.clock = 27200,
755
+
.config = {
756
+
0x84,
757
+
0x2d,
758
+
0x0,
759
+
},
760
+
.addr_msb = {
761
+
0x87,
762
+
0x87,
763
+
0x87,
764
+
0x87,
765
+
0x88,
766
+
0x88,
767
+
0x88,
768
+
0x88,
769
+
0x88,
770
+
0x88,
771
+
0x88,
772
+
0x88,
773
+
0x88,
774
+
},
775
+
.addr_lsb = {
776
+
0x10,
777
+
0x0c,
778
+
0x14,
779
+
0xe4,
780
+
0x0c,
781
+
0x10,
782
+
0x14,
783
+
0x18,
784
+
0x48,
785
+
0x40,
786
+
0x4c,
787
+
0x24,
788
+
0x44,
789
+
},
790
+
.data = {
791
+
{ 0x0, 0x4c, 0x2, 0x0 },
792
+
{ 0x0b, 0x15, 0x26, 0xa0 },
793
+
{ 0x60, 0x0, 0x0, 0x0 },
794
+
{ 0x8, 0x4, 0x96, 0x28 },
795
+
{ 0xfa, 0x0c, 0x84, 0x11 },
796
+
{ 0x80, 0x0f, 0xd9, 0x53 },
797
+
{ 0x86, 0x0, 0x0, 0x0 },
798
+
{ 0x1, 0xa0, 0x1, 0x0 },
799
+
{ 0x4b, 0x0, 0x0, 0x0 },
800
+
{ 0x28, 0x0, 0x0, 0x0 },
801
+
{ 0x0, 0x14, 0x2a, 0x14 },
802
+
{ 0x0, 0x0, 0x0, 0x0 },
803
+
{ 0x0, 0x0, 0x0, 0x0 },
804
+
},
805
+
};
806
+
807
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {
808
+
.clock = 74250,
809
+
.config = {
810
+
0x84,
811
+
0x2d,
812
+
0x0,
813
+
},
814
+
.addr_msb = {
815
+
0x87,
816
+
0x87,
817
+
0x87,
818
+
0x87,
819
+
0x88,
820
+
0x88,
821
+
0x88,
822
+
0x88,
823
+
0x88,
824
+
0x88,
825
+
0x88,
826
+
0x88,
827
+
0x88,
828
+
},
829
+
.addr_lsb = {
830
+
0x10,
831
+
0x0c,
832
+
0x14,
833
+
0xe4,
834
+
0x0c,
835
+
0x10,
836
+
0x14,
837
+
0x18,
838
+
0x48,
839
+
0x40,
840
+
0x4c,
841
+
0x24,
842
+
0x44,
843
+
},
844
+
.data = {
845
+
{ 0x0, 0x4c, 0x2, 0x0 },
846
+
{ 0x4, 0x15, 0x26, 0xa0 },
847
+
{ 0x60, 0x0, 0x0, 0x0 },
848
+
{ 0x8, 0x4, 0x88, 0x28 },
849
+
{ 0xfa, 0x0c, 0x84, 0x11 },
850
+
{ 0x80, 0x0f, 0xd9, 0x53 },
851
+
{ 0x86, 0x0, 0x0, 0x0 },
852
+
{ 0x1, 0xa0, 0x1, 0x0 },
853
+
{ 0x4b, 0x0, 0x0, 0x0 },
854
+
{ 0x28, 0x0, 0x0, 0x0 },
855
+
{ 0x0, 0x14, 0x2a, 0x14 },
856
+
{ 0x0, 0x0, 0x0, 0x0 },
857
+
{ 0x0, 0x0, 0x0, 0x0 },
858
+
},
859
+
};
860
+
861
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = {
862
+
.clock = 148500,
863
+
.config = {
864
+
0x84,
865
+
0x2d,
866
+
0x0,
867
+
},
868
+
.addr_msb = {
869
+
0x87,
870
+
0x87,
871
+
0x87,
872
+
0x87,
873
+
0x88,
874
+
0x88,
875
+
0x88,
876
+
0x88,
877
+
0x88,
878
+
0x88,
879
+
0x88,
880
+
0x88,
881
+
0x88,
882
+
},
883
+
.addr_lsb = {
884
+
0x10,
885
+
0x0c,
886
+
0x14,
887
+
0xe4,
888
+
0x0c,
889
+
0x10,
890
+
0x14,
891
+
0x18,
892
+
0x48,
893
+
0x40,
894
+
0x4c,
895
+
0x24,
896
+
0x44,
897
+
},
898
+
.data = {
899
+
{ 0x0, 0x4c, 0x2, 0x0 },
900
+
{ 0x2, 0x15, 0x26, 0xa0 },
901
+
{ 0x60, 0x0, 0x0, 0x0 },
902
+
{ 0x8, 0x4, 0x84, 0x28 },
903
+
{ 0xfa, 0x0c, 0x84, 0x11 },
904
+
{ 0x80, 0x0f, 0xd9, 0x53 },
905
+
{ 0x86, 0x0, 0x0, 0x0 },
906
+
{ 0x1, 0xa0, 0x1, 0x0 },
907
+
{ 0x4b, 0x0, 0x0, 0x0 },
908
+
{ 0x28, 0x0, 0x0, 0x0 },
909
+
{ 0x0, 0x14, 0x2a, 0x14 },
910
+
{ 0x0, 0x0, 0x0, 0x0 },
911
+
{ 0x0, 0x0, 0x0, 0x0 },
912
+
},
913
+
};
914
+
915
+
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
916
+
.clock = 594000,
917
+
.config = {
918
+
0x84,
919
+
0x2d,
920
+
0x0,
921
+
},
922
+
.addr_msb = {
923
+
0x87,
924
+
0x87,
925
+
0x87,
926
+
0x87,
927
+
0x88,
928
+
0x88,
929
+
0x88,
930
+
0x88,
931
+
0x88,
932
+
0x88,
933
+
0x88,
934
+
0x88,
935
+
0x88,
936
+
},
937
+
.addr_lsb = {
938
+
0x10,
939
+
0x0c,
940
+
0x14,
941
+
0xe4,
942
+
0x0c,
943
+
0x10,
944
+
0x14,
945
+
0x18,
946
+
0x48,
947
+
0x40,
948
+
0x4c,
949
+
0x24,
950
+
0x44,
951
+
},
952
+
.data = {
953
+
{ 0x0, 0x4c, 0x2, 0x0 },
954
+
{ 0x0, 0x95, 0x26, 0xa0 },
955
+
{ 0x60, 0x0, 0x0, 0x0 },
956
+
{ 0x8, 0x4, 0x81, 0x28 },
957
+
{ 0xfa, 0x0c, 0x84, 0x11 },
958
+
{ 0x80, 0x0f, 0xd9, 0x53 },
959
+
{ 0x86, 0x0, 0x0, 0x0 },
960
+
{ 0x1, 0xa0, 0x1, 0x0 },
961
+
{ 0x4b, 0x0, 0x0, 0x0 },
962
+
{ 0x28, 0x0, 0x0, 0x0 },
963
+
{ 0x0, 0x14, 0x2a, 0x14 },
964
+
{ 0x0, 0x0, 0x0, 0x0 },
965
+
{ 0x0, 0x0, 0x0, 0x0 },
966
+
},
967
+
};
968
+
969
+
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
970
+
&xe3plpd_lt_hdmi_252,
971
+
&xe3plpd_lt_hdmi_272,
972
+
&xe3plpd_lt_hdmi_742p5,
973
+
&xe3plpd_lt_hdmi_1p485,
974
+
&xe3plpd_lt_hdmi_5p94,
975
+
NULL,
976
+
};
27
977
28
978
static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
29
979
{
···
1186
234
1187
235
intel_psr_resume(intel_dp);
1188
236
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
237
+
}
238
+
239
+
static const struct intel_lt_phy_pll_state * const *
240
+
intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
241
+
struct intel_encoder *encoder)
242
+
{
243
+
if (intel_crtc_has_dp_encoder(crtc_state)) {
244
+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
245
+
return xe3plpd_lt_edp_tables;
246
+
247
+
return xe3plpd_lt_dp_tables;
248
+
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
249
+
return xe3plpd_lt_hdmi_tables;
250
+
}
251
+
252
+
MISSING_CASE(encoder->type);
253
+
return NULL;
254
+
}
255
+
256
+
int
257
+
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
258
+
struct intel_encoder *encoder)
259
+
{
260
+
const struct intel_lt_phy_pll_state * const *tables;
261
+
int i;
262
+
263
+
tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
264
+
if (!tables)
265
+
return -EINVAL;
266
+
267
+
for (i = 0; tables[i]; i++) {
268
+
if (crtc_state->port_clock == tables[i]->clock) {
269
+
crtc_state->dpll_hw_state.ltpll = *tables[i];
270
+
return 0;
271
+
}
272
+
}
273
+
274
+
/* TODO: Add a function to compute the data for HDMI TMDS*/
275
+
276
+
return -EINVAL;
1189
277
}
1190
278
1191
279
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
+5
drivers/gpu/drm/i915/display/intel_lt_phy.h
+5
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
13
13
14
14
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
15
15
const struct intel_crtc_state *crtc_state);
16
+
int
17
+
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
18
+
struct intel_encoder *encoder);
19
+
20
+
#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
16
21
17
22
#endif /* __INTEL_LT_PHY_H__ */