Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas ARM DT updates for v6.2 (take two)
- Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for
the R-Car V4H SoC,
- Watchdog, L2 cache, and system controller support for the RZ/V2M
SoC on the RZ/V2M Evaluation Kit 2.0,
- Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the
Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
arm64: dts: renesas: r9a09g011: Add system controller node
arm64: dts: renesas: r8a779g0: Add CA76 operating points
arm64: dts: renesas: r8a779g0: Add CPU core clocks
arm64: dts: renesas: r8a779g0: Add CPUIdle support
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
arm64: dts: renesas: r8a779g0: Add L3 cache controller
arm64: dts: renesas: r9a09g011: Add L2 Cache node
arm64: dts: renesas: rzv2mevk2: Enable watchdog
arm64: dts: renesas: r9a09g011: Add watchdog node
arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0
arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes
arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings
arm64: dts: renesas: rzg2l: Add missing cache-level properties
arm64: dts: renesas: r8a779g0: Add CMT node
arm64: dts: renesas: r9a09g011: Fix unit address format error
arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly
arm64: dts: renesas: r8a779g0: Add TMU nodes
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
...
Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+522
-37
+15
-15
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+15
-15
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
···
12
12
compatible = "renesas,spider-cpu", "renesas,r8a779f0";
13
13
14
14
aliases {
15
-
serial0 = &scif3;
15
+
serial0 = &hscif0;
16
16
serial1 = &scif0;
17
17
};
18
18
19
19
chosen {
20
20
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
21
-
stdout-path = "serial0:115200n8";
21
+
stdout-path = "serial0:1843200n8";
22
22
};
23
23
24
24
memory@48000000 {
···
57
57
58
58
&extalr_clk {
59
59
clock-frequency = <32768>;
60
+
};
61
+
62
+
&hscif0 {
63
+
pinctrl-0 = <&hscif0_pins>;
64
+
pinctrl-names = "default";
65
+
66
+
uart-has-rtscts;
67
+
status = "okay";
60
68
};
61
69
62
70
&i2c4 {
···
107
99
pinctrl-0 = <&scif_clk_pins>;
108
100
pinctrl-names = "default";
109
101
102
+
hscif0_pins: hscif0 {
103
+
groups = "hscif0_data", "hscif0_ctrl";
104
+
function = "hscif0";
105
+
};
106
+
110
107
i2c4_pins: i2c4 {
111
108
groups = "i2c4";
112
109
function = "i2c4";
···
128
115
function = "scif0";
129
116
};
130
117
131
-
scif3_pins: scif3 {
132
-
groups = "scif3_data", "scif3_ctrl";
133
-
function = "scif3";
134
-
};
135
-
136
118
scif_clk_pins: scif_clk {
137
119
groups = "scif_clk";
138
120
function = "scif_clk";
···
141
133
142
134
&scif0 {
143
135
pinctrl-0 = <&scif0_pins>;
144
-
pinctrl-names = "default";
145
-
146
-
uart-has-rtscts;
147
-
status = "okay";
148
-
};
149
-
150
-
&scif3 {
151
-
pinctrl-0 = <&scif3_pins>;
152
136
pinctrl-names = "default";
153
137
154
138
uart-has-rtscts;
+90
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
+90
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
···
5
5
* Copyright (C) 2021 Renesas Electronics Corp.
6
6
*/
7
7
8
+
ð_serdes {
9
+
status = "okay";
10
+
};
11
+
8
12
&i2c4 {
9
13
eeprom@52 {
10
14
compatible = "rohm,br24g01", "atmel,24c01";
11
15
label = "ethernet-sub-board";
12
16
reg = <0x52>;
13
17
pagesize = <8>;
18
+
};
19
+
};
20
+
21
+
&pfc {
22
+
tsn0_pins: tsn0 {
23
+
groups = "tsn0_mdio_b", "tsn0_link_b";
24
+
function = "tsn0";
25
+
power-source = <1800>;
26
+
};
27
+
28
+
tsn1_pins: tsn1 {
29
+
groups = "tsn1_mdio_b", "tsn1_link_b";
30
+
function = "tsn1";
31
+
power-source = <1800>;
32
+
};
33
+
34
+
tsn2_pins: tsn2 {
35
+
groups = "tsn2_mdio_b", "tsn2_link_b";
36
+
function = "tsn2";
37
+
power-source = <1800>;
38
+
};
39
+
};
40
+
41
+
&rswitch {
42
+
pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
43
+
pinctrl-names = "default";
44
+
status = "okay";
45
+
46
+
ethernet-ports {
47
+
#address-cells = <1>;
48
+
#size-cells = <0>;
49
+
50
+
port@0 {
51
+
reg = <0>;
52
+
phy-handle = <&u101>;
53
+
phy-mode = "sgmii";
54
+
phys = <ð_serdes 0>;
55
+
56
+
mdio {
57
+
#address-cells = <1>;
58
+
#size-cells = <0>;
59
+
60
+
u101: ethernet-phy@1 {
61
+
reg = <1>;
62
+
compatible = "ethernet-phy-ieee802.3-c45";
63
+
interrupt-parent = <&gpio3>;
64
+
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
65
+
};
66
+
};
67
+
};
68
+
port@1 {
69
+
reg = <1>;
70
+
phy-handle = <&u201>;
71
+
phy-mode = "sgmii";
72
+
phys = <ð_serdes 1>;
73
+
74
+
mdio {
75
+
#address-cells = <1>;
76
+
#size-cells = <0>;
77
+
78
+
u201: ethernet-phy@2 {
79
+
reg = <2>;
80
+
compatible = "ethernet-phy-ieee802.3-c45";
81
+
interrupt-parent = <&gpio3>;
82
+
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
83
+
};
84
+
};
85
+
};
86
+
port@2 {
87
+
reg = <2>;
88
+
phy-handle = <&u301>;
89
+
phy-mode = "sgmii";
90
+
phys = <ð_serdes 2>;
91
+
92
+
mdio {
93
+
#address-cells = <1>;
94
+
#size-cells = <0>;
95
+
96
+
u301: ethernet-phy@3 {
97
+
reg = <3>;
98
+
compatible = "ethernet-phy-ieee802.3-c45";
99
+
interrupt-parent = <&gpio3>;
100
+
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
101
+
};
102
+
};
103
+
};
14
104
};
15
105
};
+118
-8
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+118
-8
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
···
469
469
status = "disabled";
470
470
};
471
471
472
+
eth_serdes: phy@e6444000 {
473
+
compatible = "renesas,r8a779f0-ether-serdes";
474
+
reg = <0 0xe6444000 0 0x2800>;
475
+
clocks = <&cpg CPG_MOD 1506>;
476
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
477
+
resets = <&cpg 1506>;
478
+
#phy-cells = <1>;
479
+
status = "disabled";
480
+
};
481
+
472
482
i2c0: i2c@e6500000 {
473
483
compatible = "renesas,i2c-r8a779f0",
474
484
"renesas,rcar-gen4-i2c";
···
587
577
reg = <0 0xe6540000 0 0x60>;
588
578
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
589
579
clocks = <&cpg CPG_MOD 514>,
590
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3>,
580
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
591
581
<&scif_clk>;
592
582
clock-names = "fck", "brg_int", "scif_clk";
593
583
dmas = <&dmac0 0x31>, <&dmac0 0x30>,
···
604
594
reg = <0 0xe6550000 0 0x60>;
605
595
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
606
596
clocks = <&cpg CPG_MOD 515>,
607
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3>,
597
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
608
598
<&scif_clk>;
609
599
clock-names = "fck", "brg_int", "scif_clk";
610
600
dmas = <&dmac0 0x33>, <&dmac0 0x32>,
···
621
611
reg = <0 0xe6560000 0 0x60>;
622
612
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
623
613
clocks = <&cpg CPG_MOD 516>,
624
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3>,
614
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
625
615
<&scif_clk>;
626
616
clock-names = "fck", "brg_int", "scif_clk";
627
617
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
···
638
628
reg = <0 0xe66a0000 0 0x60>;
639
629
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
640
630
clocks = <&cpg CPG_MOD 517>,
641
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3>,
631
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
642
632
<&scif_clk>;
643
633
clock-names = "fck", "brg_int", "scif_clk";
644
634
dmas = <&dmac0 0x37>, <&dmac0 0x36>,
···
661
651
status = "disabled";
662
652
};
663
653
654
+
rswitch: ethernet@e6880000 {
655
+
compatible = "renesas,r8a779f0-ether-switch";
656
+
reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
657
+
reg-names = "base", "secure_base";
658
+
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
659
+
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
660
+
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
661
+
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
662
+
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
663
+
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
664
+
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
665
+
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
666
+
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
667
+
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
668
+
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
669
+
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
670
+
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
671
+
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
672
+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
673
+
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
674
+
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
675
+
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
676
+
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
677
+
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
678
+
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
679
+
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
680
+
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
681
+
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
682
+
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
683
+
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
684
+
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
685
+
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
686
+
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
687
+
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
688
+
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
689
+
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
690
+
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
691
+
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
692
+
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
693
+
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
694
+
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
695
+
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
696
+
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
697
+
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
698
+
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
699
+
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
700
+
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
701
+
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
702
+
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
703
+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
704
+
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
705
+
interrupt-names = "mfwd_error", "race_error",
706
+
"coma_error", "gwca0_error",
707
+
"gwca1_error", "etha0_error",
708
+
"etha1_error", "etha2_error",
709
+
"gptp0_status", "gptp1_status",
710
+
"mfwd_status", "race_status",
711
+
"coma_status", "gwca0_status",
712
+
"gwca1_status", "etha0_status",
713
+
"etha1_status", "etha2_status",
714
+
"rmac0_status", "rmac1_status",
715
+
"rmac2_status",
716
+
"gwca0_rxtx0", "gwca0_rxtx1",
717
+
"gwca0_rxtx2", "gwca0_rxtx3",
718
+
"gwca0_rxtx4", "gwca0_rxtx5",
719
+
"gwca0_rxtx6", "gwca0_rxtx7",
720
+
"gwca1_rxtx0", "gwca1_rxtx1",
721
+
"gwca1_rxtx2", "gwca1_rxtx3",
722
+
"gwca1_rxtx4", "gwca1_rxtx5",
723
+
"gwca1_rxtx6", "gwca1_rxtx7",
724
+
"gwca0_rxts0", "gwca0_rxts1",
725
+
"gwca1_rxts0", "gwca1_rxts1",
726
+
"rmac0_mdio", "rmac1_mdio",
727
+
"rmac2_mdio",
728
+
"rmac0_phy", "rmac1_phy",
729
+
"rmac2_phy";
730
+
clocks = <&cpg CPG_MOD 1505>;
731
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
732
+
resets = <&cpg 1505>;
733
+
status = "disabled";
734
+
735
+
ethernet-ports {
736
+
#address-cells = <1>;
737
+
#size-cells = <0>;
738
+
739
+
port@0 {
740
+
reg = <0>;
741
+
phys = <ð_serdes 0>;
742
+
};
743
+
port@1 {
744
+
reg = <1>;
745
+
phys = <ð_serdes 1>;
746
+
};
747
+
port@2 {
748
+
reg = <2>;
749
+
phys = <ð_serdes 2>;
750
+
};
751
+
};
752
+
};
753
+
664
754
scif0: serial@e6e60000 {
665
755
compatible = "renesas,scif-r8a779f0",
666
756
"renesas,rcar-gen4-scif", "renesas,scif";
667
757
reg = <0 0xe6e60000 0 64>;
668
758
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
669
759
clocks = <&cpg CPG_MOD 702>,
670
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
760
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
671
761
<&scif_clk>;
672
762
clock-names = "fck", "brg_int", "scif_clk";
673
763
dmas = <&dmac0 0x51>, <&dmac0 0x50>,
···
784
674
reg = <0 0xe6e68000 0 64>;
785
675
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
786
676
clocks = <&cpg CPG_MOD 703>,
787
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
677
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
788
678
<&scif_clk>;
789
679
clock-names = "fck", "brg_int", "scif_clk";
790
680
dmas = <&dmac0 0x53>, <&dmac0 0x52>,
···
801
691
reg = <0 0xe6c50000 0 64>;
802
692
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
803
693
clocks = <&cpg CPG_MOD 704>,
804
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
694
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
805
695
<&scif_clk>;
806
696
clock-names = "fck", "brg_int", "scif_clk";
807
697
dmas = <&dmac0 0x57>, <&dmac0 0x56>,
···
818
708
reg = <0 0xe6c40000 0 64>;
819
709
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
820
710
clocks = <&cpg CPG_MOD 705>,
821
-
<&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
711
+
<&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
822
712
<&scif_clk>;
823
713
clock-names = "fck", "brg_int", "scif_clk";
824
714
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
+4
-4
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
+4
-4
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
+260
-5
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+260
-5
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
···
14
14
#address-cells = <2>;
15
15
#size-cells = <2>;
16
16
17
+
cluster0_opp: opp-table-0 {
18
+
compatible = "operating-points-v2";
19
+
opp-shared;
20
+
21
+
opp-500000000 {
22
+
opp-hz = /bits/ 64 <500000000>;
23
+
opp-microvolt = <825000>;
24
+
clock-latency-ns = <500000>;
25
+
};
26
+
opp-1000000000 {
27
+
opp-hz = /bits/ 64 <1000000000>;
28
+
opp-microvolt = <825000>;
29
+
clock-latency-ns = <500000>;
30
+
};
31
+
opp-1500000000 {
32
+
opp-hz = /bits/ 64 <1500000000>;
33
+
opp-microvolt = <825000>;
34
+
clock-latency-ns = <500000>;
35
+
};
36
+
opp-1700000000 {
37
+
opp-hz = /bits/ 64 <1700000000>;
38
+
opp-microvolt = <825000>;
39
+
clock-latency-ns = <500000>;
40
+
opp-suspend;
41
+
};
42
+
};
43
+
17
44
cpus {
18
45
#address-cells = <1>;
19
46
#size-cells = <0>;
47
+
48
+
cpu-map {
49
+
cluster0 {
50
+
core0 {
51
+
cpu = <&a76_0>;
52
+
};
53
+
core1 {
54
+
cpu = <&a76_1>;
55
+
};
56
+
};
57
+
58
+
cluster1 {
59
+
core0 {
60
+
cpu = <&a76_2>;
61
+
};
62
+
core1 {
63
+
cpu = <&a76_3>;
64
+
};
65
+
};
66
+
};
20
67
21
68
a76_0: cpu@0 {
22
69
compatible = "arm,cortex-a76";
23
70
reg = <0>;
24
71
device_type = "cpu";
25
72
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
73
+
next-level-cache = <&L3_CA76_0>;
74
+
enable-method = "psci";
75
+
cpu-idle-states = <&CPU_SLEEP_0>;
76
+
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
77
+
operating-points-v2 = <&cluster0_opp>;
26
78
};
79
+
80
+
a76_1: cpu@100 {
81
+
compatible = "arm,cortex-a76";
82
+
reg = <0x100>;
83
+
device_type = "cpu";
84
+
power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
85
+
next-level-cache = <&L3_CA76_0>;
86
+
enable-method = "psci";
87
+
cpu-idle-states = <&CPU_SLEEP_0>;
88
+
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
89
+
operating-points-v2 = <&cluster0_opp>;
90
+
};
91
+
92
+
a76_2: cpu@10000 {
93
+
compatible = "arm,cortex-a76";
94
+
reg = <0x10000>;
95
+
device_type = "cpu";
96
+
power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
97
+
next-level-cache = <&L3_CA76_1>;
98
+
enable-method = "psci";
99
+
cpu-idle-states = <&CPU_SLEEP_0>;
100
+
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
101
+
operating-points-v2 = <&cluster0_opp>;
102
+
};
103
+
104
+
a76_3: cpu@10100 {
105
+
compatible = "arm,cortex-a76";
106
+
reg = <0x10100>;
107
+
device_type = "cpu";
108
+
power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
109
+
next-level-cache = <&L3_CA76_1>;
110
+
enable-method = "psci";
111
+
cpu-idle-states = <&CPU_SLEEP_0>;
112
+
clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
113
+
operating-points-v2 = <&cluster0_opp>;
114
+
};
115
+
116
+
idle-states {
117
+
entry-method = "psci";
118
+
119
+
CPU_SLEEP_0: cpu-sleep-0 {
120
+
compatible = "arm,idle-state";
121
+
arm,psci-suspend-param = <0x0010000>;
122
+
local-timer-stop;
123
+
entry-latency-us = <400>;
124
+
exit-latency-us = <500>;
125
+
min-residency-us = <4000>;
126
+
};
127
+
};
128
+
129
+
L3_CA76_0: cache-controller-0 {
130
+
compatible = "cache";
131
+
power-domains = <&sysc R8A779G0_PD_A2E0D0>;
132
+
cache-unified;
133
+
cache-level = <3>;
134
+
};
135
+
136
+
L3_CA76_1: cache-controller-1 {
137
+
compatible = "cache";
138
+
power-domains = <&sysc R8A779G0_PD_A2E0D1>;
139
+
cache-unified;
140
+
cache-level = <3>;
141
+
};
142
+
};
143
+
144
+
psci {
145
+
compatible = "arm,psci-1.0", "arm,psci-0.2";
146
+
method = "smc";
27
147
};
28
148
29
149
extal_clk: extal {
···
334
214
#interrupt-cells = <2>;
335
215
};
336
216
217
+
cmt0: timer@e60f0000 {
218
+
compatible = "renesas,r8a779g0-cmt0",
219
+
"renesas,rcar-gen4-cmt0";
220
+
reg = <0 0xe60f0000 0 0x1004>;
221
+
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
222
+
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
223
+
clocks = <&cpg CPG_MOD 910>;
224
+
clock-names = "fck";
225
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
226
+
resets = <&cpg 910>;
227
+
status = "disabled";
228
+
};
229
+
230
+
cmt1: timer@e6130000 {
231
+
compatible = "renesas,r8a779g0-cmt1",
232
+
"renesas,rcar-gen4-cmt1";
233
+
reg = <0 0xe6130000 0 0x1004>;
234
+
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
235
+
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
236
+
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
237
+
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
238
+
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
239
+
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
240
+
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
241
+
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
242
+
clocks = <&cpg CPG_MOD 911>;
243
+
clock-names = "fck";
244
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
245
+
resets = <&cpg 911>;
246
+
status = "disabled";
247
+
};
248
+
249
+
cmt2: timer@e6140000 {
250
+
compatible = "renesas,r8a779g0-cmt1",
251
+
"renesas,rcar-gen4-cmt1";
252
+
reg = <0 0xe6140000 0 0x1004>;
253
+
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
254
+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
255
+
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
256
+
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
257
+
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
258
+
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
259
+
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
260
+
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
261
+
clocks = <&cpg CPG_MOD 912>;
262
+
clock-names = "fck";
263
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
264
+
resets = <&cpg 912>;
265
+
status = "disabled";
266
+
};
267
+
268
+
cmt3: timer@e6148000 {
269
+
compatible = "renesas,r8a779g0-cmt1",
270
+
"renesas,rcar-gen4-cmt1";
271
+
reg = <0 0xe6148000 0 0x1004>;
272
+
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
273
+
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
274
+
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
275
+
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
276
+
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
277
+
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
278
+
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
279
+
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
280
+
clocks = <&cpg CPG_MOD 913>;
281
+
clock-names = "fck";
282
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
283
+
resets = <&cpg 913>;
284
+
status = "disabled";
285
+
};
286
+
337
287
cpg: clock-controller@e6150000 {
338
288
compatible = "renesas,r8a779g0-cpg-mssr";
339
289
reg = <0 0xe6150000 0 0x4000>;
···
439
249
clocks = <&cpg CPG_MOD 611>;
440
250
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
441
251
resets = <&cpg 611>;
252
+
};
253
+
254
+
tmu0: timer@e61e0000 {
255
+
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
256
+
reg = <0 0xe61e0000 0 0x30>;
257
+
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
258
+
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
259
+
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
260
+
clocks = <&cpg CPG_MOD 713>;
261
+
clock-names = "fck";
262
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
263
+
resets = <&cpg 713>;
264
+
status = "disabled";
265
+
};
266
+
267
+
tmu1: timer@e6fc0000 {
268
+
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
269
+
reg = <0 0xe6fc0000 0 0x30>;
270
+
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
271
+
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
272
+
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
273
+
clocks = <&cpg CPG_MOD 714>;
274
+
clock-names = "fck";
275
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
276
+
resets = <&cpg 714>;
277
+
status = "disabled";
278
+
};
279
+
280
+
tmu2: timer@e6fd0000 {
281
+
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
282
+
reg = <0 0xe6fd0000 0 0x30>;
283
+
interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
284
+
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
285
+
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
286
+
clocks = <&cpg CPG_MOD 715>;
287
+
clock-names = "fck";
288
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
289
+
resets = <&cpg 715>;
290
+
status = "disabled";
291
+
};
292
+
293
+
tmu3: timer@e6fe0000 {
294
+
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
295
+
reg = <0 0xe6fe0000 0 0x30>;
296
+
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
297
+
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
298
+
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
299
+
clocks = <&cpg CPG_MOD 716>;
300
+
clock-names = "fck";
301
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
302
+
resets = <&cpg 716>;
303
+
status = "disabled";
304
+
};
305
+
306
+
tmu4: timer@ffc00000 {
307
+
compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
308
+
reg = <0 0xffc00000 0 0x30>;
309
+
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
310
+
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
311
+
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
312
+
clocks = <&cpg CPG_MOD 717>;
313
+
clock-names = "fck";
314
+
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
315
+
resets = <&cpg 717>;
316
+
status = "disabled";
442
317
};
443
318
444
319
i2c0: i2c@e6500000 {
···
1200
945
reg = <0x0 0xf1000000 0 0x20000>,
1201
946
<0x0 0xf1060000 0 0x110000>;
1202
947
interrupts = <GIC_PPI 9
1203
-
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
948
+
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1204
949
};
1205
950
1206
951
prr: chipid@fff00044 {
···
1211
956
1212
957
timer {
1213
958
compatible = "arm,armv8-timer";
1214
-
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1215
-
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1216
-
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1217
-
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
959
+
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
960
+
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
961
+
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
962
+
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1218
963
};
1219
964
};
+1
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+1
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+1
-1
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+1
-1
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
···
109
109
compatible = "cache";
110
110
cache-unified;
111
111
cache-size = <0x40000>;
112
+
cache-level = <3>;
112
113
};
113
114
};
114
115
···
645
644
reg = <0 0x11030000 0 0x10000>;
646
645
gpio-controller;
647
646
#gpio-cells = <2>;
648
-
#address-cells = <2>;
649
647
#interrupt-cells = <2>;
650
648
interrupt-parent = <&irqc>;
651
649
interrupt-controller;
+1
-1
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+1
-1
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
···
109
109
compatible = "cache";
110
110
cache-unified;
111
111
cache-size = <0x40000>;
112
+
cache-level = <3>;
112
113
};
113
114
};
114
115
···
651
650
reg = <0 0x11030000 0 0x10000>;
652
651
gpio-controller;
653
652
#gpio-cells = <2>;
654
-
#address-cells = <2>;
655
653
#interrupt-cells = <2>;
656
654
interrupt-parent = <&irqc>;
657
655
interrupt-controller;
+4
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+4
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
+28
-3
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
+28
-3
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
···
37
37
compatible = "arm,cortex-a53";
38
38
reg = <0>;
39
39
device_type = "cpu";
40
+
next-level-cache = <&L2_CA53>;
40
41
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
42
+
};
43
+
44
+
L2_CA53: cache-controller-0 {
45
+
compatible = "cache";
46
+
cache-unified;
47
+
cache-level = <2>;
41
48
};
42
49
};
43
50
···
55
48
#size-cells = <2>;
56
49
ranges;
57
50
58
-
gic: interrupt-controller@82000000 {
51
+
gic: interrupt-controller@82010000 {
59
52
compatible = "arm,gic-400";
60
53
#interrupt-cells = <3>;
61
54
#address-cells = <0>;
···
130
123
#power-domain-cells = <0>;
131
124
};
132
125
126
+
sys: system-controller@a3f03000 {
127
+
compatible = "renesas,r9a09g011-sys";
128
+
reg = <0 0xa3f03000 0 0x400>;
129
+
};
130
+
133
131
i2c0: i2c@a4030000 {
134
132
#address-cells = <1>;
135
133
#size-cells = <0>;
136
-
compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
134
+
compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
137
135
reg = <0 0xa4030000 0 0x80>;
138
136
interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
139
137
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
···
152
140
i2c2: i2c@a4030100 {
153
141
#address-cells = <1>;
154
142
#size-cells = <0>;
155
-
compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
143
+
compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
156
144
reg = <0 0xa4030100 0 0x80>;
157
145
interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
158
146
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
···
170
158
clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
171
159
<&cpg CPG_MOD R9A09G011_URT_PCLK>;
172
160
clock-names = "sclk", "pclk";
161
+
status = "disabled";
162
+
};
163
+
164
+
wdt0: watchdog@a4050000 {
165
+
compatible = "renesas,r9a09g011-wdt",
166
+
"renesas,rzv2m-wdt";
167
+
reg = <0 0xa4050000 0 0x80>;
168
+
clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
169
+
<&cpg CPG_MOD R9A09G011_WDT0_CLK>;
170
+
clock-names = "pclk", "oscclk";
171
+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
172
+
resets = <&cpg R9A09G011_WDT0_PRESETN>;
173
+
power-domains = <&cpg>;
173
174
status = "disabled";
174
175
};
175
176