Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+202
-1
+2
-1
MAINTAINERS
+2
-1
MAINTAINERS
···
2694
2694
F: arch/arm/mach-realtek/
2695
2695
F: arch/arm64/boot/dts/realtek/
2696
2696
2697
-
ARM/RENESAS ARCHITECTURE
2697
+
ARM/RISC-V/RENESAS ARCHITECTURE
2698
2698
M: Geert Uytterhoeven <geert+renesas@glider.be>
2699
2699
M: Magnus Damm <magnus.damm@gmail.com>
2700
2700
L: linux-renesas-soc@vger.kernel.org
···
2715
2715
F: arch/arm/include/debug/renesas-scif.S
2716
2716
F: arch/arm/mach-shmobile/
2717
2717
F: arch/arm64/boot/dts/renesas/
2718
+
F: arch/riscv/boot/dts/renesas/
2718
2719
F: drivers/soc/renesas/
2719
2720
F: include/linux/soc/renesas/
2720
2721
+1
arch/riscv/boot/dts/Makefile
+1
arch/riscv/boot/dts/Makefile
+2
arch/riscv/boot/dts/renesas/Makefile
+2
arch/riscv/boot/dts/renesas/Makefile
+59
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+59
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/Five SoC
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/irq.h>
9
+
10
+
#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
11
+
12
+
#include <arm64/renesas/r9a07g043.dtsi>
13
+
14
+
/ {
15
+
cpus {
16
+
#address-cells = <1>;
17
+
#size-cells = <0>;
18
+
timebase-frequency = <12000000>;
19
+
20
+
cpu0: cpu@0 {
21
+
compatible = "andestech,ax45mp", "riscv";
22
+
device_type = "cpu";
23
+
#cooling-cells = <2>;
24
+
reg = <0x0>;
25
+
status = "okay";
26
+
riscv,isa = "rv64imafdc";
27
+
mmu-type = "riscv,sv39";
28
+
i-cache-size = <0x8000>;
29
+
i-cache-line-size = <0x40>;
30
+
d-cache-size = <0x8000>;
31
+
d-cache-line-size = <0x40>;
32
+
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
33
+
operating-points-v2 = <&cluster0_opp>;
34
+
35
+
cpu0_intc: interrupt-controller {
36
+
#interrupt-cells = <1>;
37
+
compatible = "riscv,cpu-intc";
38
+
interrupt-controller;
39
+
};
40
+
};
41
+
};
42
+
};
43
+
44
+
&soc {
45
+
interrupt-parent = <&plic>;
46
+
47
+
plic: interrupt-controller@12c00000 {
48
+
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
49
+
#interrupt-cells = <2>;
50
+
#address-cells = <0>;
51
+
riscv,ndev = <511>;
52
+
interrupt-controller;
53
+
reg = <0x0 0x12c00000 0 0x400000>;
54
+
clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
55
+
power-domains = <&cpg>;
56
+
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
57
+
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
58
+
};
59
+
};
+27
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
+27
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/Five SMARC EVK
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
10
+
/*
11
+
* DIP-Switch SW1 setting
12
+
* 1 : High; 0: Low
13
+
* SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14
+
* SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15
+
* Please change below macros according to SW1 setting on the SoM
16
+
*/
17
+
#define SW_SW0_DEV_SEL 1
18
+
#define SW_ET0_EN_N 1
19
+
20
+
#include "r9a07g043f.dtsi"
21
+
#include "rzfive-smarc-som.dtsi"
22
+
#include "rzfive-smarc.dtsi"
23
+
24
+
/ {
25
+
model = "Renesas SMARC EVK based on r9a07g043f01";
26
+
compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
27
+
};
+47
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+47
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/Five SMARC EVK SOM
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
9
+
10
+
/ {
11
+
aliases {
12
+
/delete-property/ ethernet0;
13
+
/delete-property/ ethernet1;
14
+
};
15
+
16
+
chosen {
17
+
bootargs = "ignore_loglevel";
18
+
};
19
+
};
20
+
21
+
&dmac {
22
+
status = "disabled";
23
+
};
24
+
25
+
ð0 {
26
+
status = "disabled";
27
+
};
28
+
29
+
ð1 {
30
+
status = "disabled";
31
+
};
32
+
33
+
&ostm1 {
34
+
status = "disabled";
35
+
};
36
+
37
+
&ostm2 {
38
+
status = "disabled";
39
+
};
40
+
41
+
&sdhi0 {
42
+
status = "disabled";
43
+
};
44
+
45
+
&wdt0 {
46
+
status = "disabled";
47
+
};
+64
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
+64
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/Five SMARC EVK carrier board
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <arm64/renesas/rzg2ul-smarc.dtsi>
9
+
10
+
&ehci0 {
11
+
status = "disabled";
12
+
};
13
+
14
+
&ehci1 {
15
+
status = "disabled";
16
+
};
17
+
18
+
&hsusb {
19
+
status = "disabled";
20
+
};
21
+
22
+
&ohci0 {
23
+
status = "disabled";
24
+
};
25
+
26
+
&ohci1 {
27
+
status = "disabled";
28
+
};
29
+
30
+
&phyrst {
31
+
status = "disabled";
32
+
};
33
+
34
+
&sdhi1 {
35
+
status = "disabled";
36
+
};
37
+
38
+
&snd_rzg2l {
39
+
status = "disabled";
40
+
};
41
+
42
+
&spi1 {
43
+
status = "disabled";
44
+
};
45
+
46
+
&ssi1 {
47
+
status = "disabled";
48
+
};
49
+
50
+
&usb0_vbus_otg {
51
+
status = "disabled";
52
+
};
53
+
54
+
&usb2_phy0 {
55
+
status = "disabled";
56
+
};
57
+
58
+
&usb2_phy1 {
59
+
status = "disabled";
60
+
};
61
+
62
+
&vccq_sdhi1 {
63
+
status = "disabled";
64
+
};