Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: dac: ad3552r-hs: update function name (non functional)
Update ad3552r_qspi_update_reg_bits function name to a more
generic name, since used mode can be SIMPLE/DUAL/QUAD SPI.
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250114-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v4-9-979402e33545@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Angelo Dureghello
and committed by
Jonathan Cameron
1ec0d78d
350d1ebf
+29
-31
+29
-31
drivers/iio/dac/ad3552r-hs.c
+29
-31
drivers/iio/dac/ad3552r-hs.c
···
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return st->data->bus_reg_read(st->back, reg, val, xfer_size);
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}
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-
static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st,
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-
u32 reg, u32 mask, u32 val,
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-
size_t xfer_size)
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+
static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg,
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+
u32 mask, u32 val, size_t xfer_size)
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{
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u32 rval;
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int ret;
···
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*/
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/* Primary region access, set streaming mode (now in SPI + SDR). */
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ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
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AD3552R_MASK_SINGLE_INST, 0, 1);
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+
ret = ad3552r_hs_update_reg_bits(st,
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AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
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AD3552R_MASK_SINGLE_INST, 0, 1);
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if (ret)
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return ret;
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···
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* 0x2c or 0x2a, in descending loop (2 or 4 bytes), keeping loop len
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* value so that it's not cleared hereafter when _CS is deasserted.
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*/
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ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_TRANSFER_REGISTER,
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AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
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AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
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+
ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
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AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
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AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
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+
1);
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if (ret)
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goto exit_err_streaming;
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···
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/*
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* From here onward mode is DDR, so reading any register is not possible
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* anymore, including calling "ad3552r_qspi_update_reg_bits" function.
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+
* anymore, including calling "ad3552r_hs_update_reg_bits" function.
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*/
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/* Set target to best high speed mode (D or QSPI). */
···
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* Back to simple SPI for secondary region too now, so to be able to
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* dump/read registers there too if needed.
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*/
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ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_TRANSFER_REGISTER,
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AD3552R_MASK_MULTI_IO_MODE,
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AD3552R_SPI, 1);
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+
ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
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AD3552R_MASK_MULTI_IO_MODE,
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AD3552R_SPI, 1);
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if (ret)
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return ret;
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/* Back to single instruction mode, disabling loop. */
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ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
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AD3552R_MASK_SINGLE_INST,
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AD3552R_MASK_SINGLE_INST, 1);
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+
ret = ad3552r_hs_update_reg_bits(st,
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AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
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AD3552R_MASK_SINGLE_INST,
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+
AD3552R_MASK_SINGLE_INST, 1);
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if (ret)
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return ret;
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···
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else
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val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode);
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-
return ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
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AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
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val, 1);
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+
return ad3552r_hs_update_reg_bits(st,
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AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
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AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
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val, 1);
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}
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static int ad3552r_hs_reset(struct ad3552r_hs_state *st)
···
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fsleep(10);
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gpiod_set_value_cansleep(st->reset_gpio, 0);
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} else {
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-
ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
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AD3552R_MASK_SOFTWARE_RESET,
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AD3552R_MASK_SOFTWARE_RESET, 1);
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+
ret = ad3552r_hs_update_reg_bits(st,
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+
AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
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AD3552R_MASK_SOFTWARE_RESET,
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+
AD3552R_MASK_SOFTWARE_RESET, 1);
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if (ret)
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return ret;
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}
···
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val = ret;
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-
ret = ad3552r_qspi_update_reg_bits(st,
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AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
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AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
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val, 1);
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+
ret = ad3552r_hs_update_reg_bits(st,
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AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
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AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
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+
val, 1);
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if (ret)
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return ret;
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