Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: dac: ad3552r-hs: add ad3541/2r support
A new FPGA HDL has been developed from ADI to support ad354xr
devices.
Add support for ad3541r and ad3542r with following additions:
- use common device_info structures for hs and non hs drivers,
- DMA buffering, use DSPI mode for ad354xr and QSPI for ad355xr,
- change sample rate to respect number of lanes.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Link: https://patch.msgid.link/20250114-wip-bl-ad3552r-axi-v0-iio-testing-carlos-v4-8-979402e33545@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Angelo Dureghello
and committed by
Jonathan Cameron
350d1ebf
67a0f040
+216
-51
+4
drivers/iio/dac/ad3552r-common.c
+4
drivers/iio/dac/ad3552r-common.c
···
42
42
.ranges_table = ad3542r_ch_ranges,
43
43
.num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
44
44
.requires_output_range = true,
45
+
.num_spi_data_lanes = 2,
45
46
};
46
47
EXPORT_SYMBOL_NS_GPL(ad3541r_model_data, "IIO_AD3552R");
47
48
···
53
52
.ranges_table = ad3542r_ch_ranges,
54
53
.num_ranges = ARRAY_SIZE(ad3542r_ch_ranges),
55
54
.requires_output_range = true,
55
+
.num_spi_data_lanes = 2,
56
56
};
57
57
EXPORT_SYMBOL_NS_GPL(ad3542r_model_data, "IIO_AD3552R");
58
58
···
64
62
.ranges_table = ad3552r_ch_ranges,
65
63
.num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
66
64
.requires_output_range = false,
65
+
.num_spi_data_lanes = 4,
67
66
};
68
67
EXPORT_SYMBOL_NS_GPL(ad3551r_model_data, "IIO_AD3552R");
69
68
···
75
72
.ranges_table = ad3552r_ch_ranges,
76
73
.num_ranges = ARRAY_SIZE(ad3552r_ch_ranges),
77
74
.requires_output_range = false,
75
+
.num_spi_data_lanes = 4,
78
76
};
79
77
EXPORT_SYMBOL_NS_GPL(ad3552r_model_data, "IIO_AD3552R");
80
78
+209
-51
drivers/iio/dac/ad3552r-hs.c
+209
-51
drivers/iio/dac/ad3552r-hs.c
···
19
19
#include "ad3552r.h"
20
20
#include "ad3552r-hs.h"
21
21
22
+
/*
23
+
* Important notes for register map access:
24
+
* ========================================
25
+
*
26
+
* Register address space is divided in 2 regions, primary (config) and
27
+
* secondary (DAC). Primary region can only be accessed in simple SPI mode,
28
+
* with exception for ad355x models where setting QSPI pin high allows QSPI
29
+
* access to both the regions.
30
+
*
31
+
* Due to the fact that ad3541/2r do not implement QSPI, for proper device
32
+
* detection, HDL keeps "QSPI" pin level low at boot (see ad3552r manual, rev B
33
+
* table 7, pin 31, digital input). For this reason, actually the working mode
34
+
* between SPI, DSPI and QSPI must be set via software, configuring the target
35
+
* DAC appropriately, together with the backend API to configure the bus mode
36
+
* accordingly.
37
+
*
38
+
* Also, important to note that none of the three modes allow to read in DDR.
39
+
*
40
+
* In non-buffering operations, mode is set to simple SPI SDR for all primary
41
+
* and secondary region r/w accesses, to avoid to switch the mode each time DAC
42
+
* register is accessed (raw accesses, r/w), and to be able to dump registers
43
+
* content (possible as non DDR only).
44
+
* In buffering mode, driver sets best possible mode, D/QSPI and DDR.
45
+
*/
46
+
22
47
struct ad3552r_hs_state {
23
48
const struct ad3552r_model_data *model_data;
24
49
struct gpio_desc *reset_gpio;
···
52
27
bool single_channel;
53
28
struct ad3552r_ch_data ch_data[AD3552R_MAX_CH];
54
29
struct ad3552r_hs_platform_data *data;
30
+
/* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */
31
+
u32 config_d;
55
32
};
33
+
34
+
static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val,
35
+
size_t xfer_size)
36
+
{
37
+
/* No chip in the family supports DDR read. Informing of this. */
38
+
WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR);
39
+
40
+
return st->data->bus_reg_read(st->back, reg, val, xfer_size);
41
+
}
56
42
57
43
static int ad3552r_qspi_update_reg_bits(struct ad3552r_hs_state *st,
58
44
u32 reg, u32 mask, u32 val,
···
72
36
u32 rval;
73
37
int ret;
74
38
75
-
ret = st->data->bus_reg_read(st->back, reg, &rval, xfer_size);
39
+
ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size);
76
40
if (ret)
77
41
return ret;
78
42
···
92
56
switch (mask) {
93
57
case IIO_CHAN_INFO_SAMP_FREQ:
94
58
/*
95
-
* Using 4 lanes (QSPI), then using 2 as DDR mode is
96
-
* considered always on (considering buffering mode always).
59
+
* Using a "num_spi_data_lanes" variable since ad3541/2 have
60
+
* only DSPI interface, while ad355x is QSPI. Then using 2 as
61
+
* DDR mode is considered always on (considering buffering
62
+
* mode always).
97
63
*/
98
64
*val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz *
99
-
4 * 2, chan->scan_type.realbits);
65
+
st->model_data->num_spi_data_lanes * 2,
66
+
chan->scan_type.realbits);
100
67
101
68
return IIO_VAL_INT;
102
69
103
70
case IIO_CHAN_INFO_RAW:
104
-
ret = st->data->bus_reg_read(st->back,
71
+
/* For RAW accesses, stay always in simple-spi. */
72
+
ret = ad3552r_hs_reg_read(st,
105
73
AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
106
74
val, 2);
107
75
if (ret)
···
133
93
134
94
switch (mask) {
135
95
case IIO_CHAN_INFO_RAW:
96
+
/* For RAW accesses, stay always in simple-spi. */
136
97
iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
137
98
return st->data->bus_reg_write(st->back,
138
99
AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
···
143
102
default:
144
103
return -EINVAL;
145
104
}
105
+
}
106
+
107
+
static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st)
108
+
{
109
+
int bus_mode;
110
+
111
+
if (st->model_data->num_spi_data_lanes == 4)
112
+
bus_mode = AD3552R_IO_MODE_QSPI;
113
+
else
114
+
bus_mode = AD3552R_IO_MODE_DSPI;
115
+
116
+
return st->data->bus_set_io_mode(st->back, bus_mode);
117
+
}
118
+
119
+
static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st)
120
+
{
121
+
u32 mode_target;
122
+
123
+
/*
124
+
* Best access for secondary reg area, QSPI where possible,
125
+
* else as DSPI.
126
+
*/
127
+
if (st->model_data->num_spi_data_lanes == 4)
128
+
mode_target = AD3552R_QUAD_SPI;
129
+
else
130
+
mode_target = AD3552R_DUAL_SPI;
131
+
132
+
/*
133
+
* Better to not use update here, since generally it is already
134
+
* set as DDR mode, and it's not possible to read in DDR mode.
135
+
*/
136
+
return st->data->bus_reg_write(st->back,
137
+
AD3552R_REG_ADDR_TRANSFER_REGISTER,
138
+
FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
139
+
mode_target) |
140
+
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
146
141
}
147
142
148
143
static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
···
209
132
return -EINVAL;
210
133
}
211
134
212
-
ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_STREAM_MODE,
213
-
loop_len, 1);
214
-
if (ret)
215
-
return ret;
135
+
/*
136
+
* With ad3541/2r support, QSPI pin is held low at reset from HDL,
137
+
* streaming start sequence must respect strictly the order below.
138
+
*/
216
139
217
140
/* Primary region access, set streaming mode (now in SPI + SDR). */
218
141
ret = ad3552r_qspi_update_reg_bits(st,
···
221
144
if (ret)
222
145
return ret;
223
146
224
-
/* Inform DAC chip to switch into DDR mode */
147
+
/*
148
+
* Set target loop len, keeping the value: streaming writes at address
149
+
* 0x2c or 0x2a, in descending loop (2 or 4 bytes), keeping loop len
150
+
* value so that it's not cleared hereafter when _CS is deasserted.
151
+
*/
225
152
ret = ad3552r_qspi_update_reg_bits(st,
226
-
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
227
-
AD3552R_MASK_SPI_CONFIG_DDR,
228
-
AD3552R_MASK_SPI_CONFIG_DDR, 1);
153
+
AD3552R_REG_ADDR_TRANSFER_REGISTER,
154
+
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
155
+
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
229
156
if (ret)
230
-
goto exit_err_ddr;
157
+
goto exit_err_streaming;
231
158
232
-
/* Inform DAC IP to go for DDR mode from now on */
159
+
ret = st->data->bus_reg_write(st->back,
160
+
AD3552R_REG_ADDR_STREAM_MODE,
161
+
loop_len, 1);
162
+
if (ret)
163
+
goto exit_err_streaming;
164
+
165
+
st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR;
166
+
ret = st->data->bus_reg_write(st->back,
167
+
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
168
+
st->config_d, 1);
169
+
if (ret)
170
+
goto exit_err_streaming;
171
+
233
172
ret = iio_backend_ddr_enable(st->back);
234
-
if (ret) {
235
-
dev_err(st->dev, "could not set DDR mode, not streaming");
236
-
goto exit_err;
237
-
}
173
+
if (ret)
174
+
goto exit_err_ddr_mode_target;
238
175
176
+
/*
177
+
* From here onward mode is DDR, so reading any register is not possible
178
+
* anymore, including calling "ad3552r_qspi_update_reg_bits" function.
179
+
*/
180
+
181
+
/* Set target to best high speed mode (D or QSPI). */
182
+
ret = ad3552r_hs_set_target_io_mode_hs(st);
183
+
if (ret)
184
+
goto exit_err_ddr_mode;
185
+
186
+
/* Set bus to best high speed mode (D or QSPI). */
187
+
ret = ad3552r_hs_set_bus_io_mode_hs(st);
188
+
if (ret)
189
+
goto exit_err_bus_mode_target;
190
+
191
+
/*
192
+
* Backend setup must be done now only, or related register values will
193
+
* be disrupted by previous bus accesses.
194
+
*/
239
195
ret = iio_backend_data_transfer_addr(st->back, val);
240
196
if (ret)
241
-
goto exit_err;
197
+
goto exit_err_bus_mode_target;
242
198
243
199
ret = iio_backend_data_format_set(st->back, 0, &fmt);
244
200
if (ret)
245
-
goto exit_err;
201
+
goto exit_err_bus_mode_target;
246
202
247
203
ret = iio_backend_data_stream_enable(st->back);
248
204
if (ret)
249
-
goto exit_err;
205
+
goto exit_err_bus_mode_target;
250
206
251
207
return 0;
252
208
253
-
exit_err:
254
-
ad3552r_qspi_update_reg_bits(st,
255
-
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
256
-
AD3552R_MASK_SPI_CONFIG_DDR,
257
-
0, 1);
209
+
exit_err_bus_mode_target:
210
+
/* Back to simple SPI, not using update to avoid read. */
211
+
st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER,
212
+
FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
213
+
AD3552R_SPI) |
214
+
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
258
215
216
+
/*
217
+
* Back bus to simple SPI, this must be executed together with above
218
+
* target mode unwind, and can be done only after it.
219
+
*/
220
+
st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
221
+
222
+
exit_err_ddr_mode:
259
223
iio_backend_ddr_disable(st->back);
260
224
261
-
exit_err_ddr:
262
-
ad3552r_qspi_update_reg_bits(st, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
263
-
AD3552R_MASK_SINGLE_INST,
264
-
AD3552R_MASK_SINGLE_INST, 1);
225
+
exit_err_ddr_mode_target:
226
+
/*
227
+
* Back to SDR. In DDR we cannot read, whatever the mode is, so not
228
+
* using update.
229
+
*/
230
+
st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
231
+
st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
232
+
st->config_d, 1);
233
+
234
+
exit_err_streaming:
235
+
/* Back to single instruction mode, disabling loop. */
236
+
st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
237
+
AD3552R_MASK_SINGLE_INST |
238
+
AD3552R_MASK_SHORT_INSTRUCTION, 1);
265
239
266
240
return ret;
267
241
}
···
326
198
if (ret)
327
199
return ret;
328
200
329
-
/* Inform DAC to set in SDR mode */
330
-
ret = ad3552r_qspi_update_reg_bits(st,
331
-
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
332
-
AD3552R_MASK_SPI_CONFIG_DDR,
333
-
0, 1);
201
+
/*
202
+
* Set us to simple SPI, even if still in ddr, so to be able to write
203
+
* in primary region.
204
+
*/
205
+
ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
206
+
if (ret)
207
+
return ret;
208
+
209
+
/*
210
+
* Back to SDR (in DDR we cannot read, whatever the mode is, so not
211
+
* using update).
212
+
*/
213
+
st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
214
+
ret = st->data->bus_reg_write(st->back,
215
+
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
216
+
st->config_d, 1);
334
217
if (ret)
335
218
return ret;
336
219
337
220
ret = iio_backend_ddr_disable(st->back);
221
+
if (ret)
222
+
return ret;
223
+
224
+
/*
225
+
* Back to simple SPI for secondary region too now, so to be able to
226
+
* dump/read registers there too if needed.
227
+
*/
228
+
ret = ad3552r_qspi_update_reg_bits(st,
229
+
AD3552R_REG_ADDR_TRANSFER_REGISTER,
230
+
AD3552R_MASK_MULTI_IO_MODE,
231
+
AD3552R_SPI, 1);
338
232
if (ret)
339
233
return ret;
340
234
···
474
324
if (ret)
475
325
return ret;
476
326
327
+
/* HDL starts with DDR enabled, disabling it. */
477
328
ret = iio_backend_ddr_disable(st->back);
478
329
if (ret)
479
330
return ret;
···
490
339
if (ret)
491
340
return ret;
492
341
493
-
ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_L,
494
-
&val, 1);
342
+
/*
343
+
* Caching config_d, needed to restore it after streaming,
344
+
* and also, to detect possible DDR read, that's not allowed.
345
+
*/
346
+
ret = st->data->bus_reg_read(st->back,
347
+
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
348
+
&st->config_d, 1);
349
+
if (ret)
350
+
return ret;
351
+
352
+
ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1);
495
353
if (ret)
496
354
return ret;
497
355
498
356
id = val;
499
357
500
-
ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_PRODUCT_ID_H,
501
-
&val, 1);
358
+
ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1);
502
359
if (ret)
503
360
return ret;
504
361
···
515
356
dev_warn(st->dev,
516
357
"chip ID mismatch, detected 0x%x but expected 0x%x\n",
517
358
id, st->model_data->chip_id);
359
+
360
+
dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name);
518
361
519
362
/* Clear reset error flag, see ad3552r manual, rev B table 38. */
520
363
ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS,
···
527
366
ret = st->data->bus_reg_write(st->back,
528
367
AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
529
368
0, 1);
530
-
if (ret)
531
-
return ret;
532
-
533
-
ret = st->data->bus_reg_write(st->back,
534
-
AD3552R_REG_ADDR_TRANSFER_REGISTER,
535
-
FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
536
-
AD3552R_QUAD_SPI) |
537
-
AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
538
369
if (ret)
539
370
return ret;
540
371
···
553
400
554
401
ret = ad3552r_get_drive_strength(st->dev, &val);
555
402
if (!ret) {
556
-
ret = ad3552r_qspi_update_reg_bits(st,
403
+
st->config_d |=
404
+
FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val);
405
+
406
+
ret = st->data->bus_reg_write(st->back,
557
407
AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
558
-
AD3552R_MASK_SDO_DRIVE_STRENGTH,
559
-
val, 1);
408
+
st->config_d, 1);
560
409
if (ret)
561
410
return ret;
562
411
}
···
688
533
}
689
534
690
535
static const struct of_device_id ad3552r_hs_of_id[] = {
536
+
{ .compatible = "adi,ad3541r", .data = &ad3541r_model_data },
537
+
{ .compatible = "adi,ad3542r", .data = &ad3542r_model_data },
538
+
{ .compatible = "adi,ad3551r", .data = &ad3551r_model_data },
691
539
{ .compatible = "adi,ad3552r", .data = &ad3552r_model_data },
692
540
{ }
693
541
};
+3
drivers/iio/dac/ad3552r.h
+3
drivers/iio/dac/ad3552r.h
···
132
132
133
133
#define AD3552R_MAX_RANGES 5
134
134
#define AD3542R_MAX_RANGES 5
135
+
#define AD3552R_SPI 0
136
+
#define AD3552R_DUAL_SPI 1
135
137
#define AD3552R_QUAD_SPI 2
136
138
137
139
extern const struct ad3552r_model_data ad3541r_model_data;
···
155
153
const s32 (*ranges_table)[2];
156
154
int num_ranges;
157
155
bool requires_output_range;
156
+
int num_spi_data_lanes;
158
157
};
159
158
160
159
struct ad3552r_ch_data {