Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-fixes-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC DT and driver fixes from Arnd Bergmann:
"Lots of dts fixes for Qualcomm Snapdragon and NXP i.MX platforms,
including:
- A regression fix for SDHCI controllers on Inforce 6540, and another
SDHCI fix on SM8350
- Reenable cluster idle on sm8250 after the the code fix is upstream
- multiple fixes for the QMP PHY binding, needing an incompatible dt
change
- The reserved memory map is updated on Xiaomi Mi 4C and Huawei Nexus
6P, to avoid instabilities caused by use of protected memory
regions
- Fix i.MX8MP DT for missing GPC Interrupt, power-domain typo and USB
clock error
- A couple of verdin-imx8mm DT fixes for audio playback support
- Fix pca9547 i2c-mux node name for i.MX and Vybrid device trees
- Fix an imx93-11x11-evk uSDHC pad setting problem that causes Micron
eMMC CMD8 CRC error in HS400ES/HS400 mode
The remaining ARM and RISC-V platforms only have very few smaller dts
bugfixes this time:
- A fix for the SiFive unmatched board's PCI memory space
- A revert to fix a regression with GPIO on Marvell Armada
- A fix for the UART address on Marvell AC5
- Missing chip-select phandles for stm32 boards
- Selecting the correct clock for the sam9x60 memory controller
- Amlogic based Odroid-HC4 needs a revert to restore USB
functionality.
And finally, there are some minor code fixes:
- Build fixes for OMAP1, pxa, riscpc, raspberry pi firmware, and zynq
firmware
- memory controller driver fixes for an OMAP regression and older
bugs on tegra, atmel and mvebu
- reset controller fixes for ti-sci and uniphier platforms
- ARM SCMI firmware fixes for a couple of rare corner cases
- Qualcomm platform driver fixes for incorrect error handling and a
backwards compatibility fix for the apr driver using older dtb
- NXP i.MX SoC driver fixes for HDMI output, error handling in the
imx8 soc-id and missing reference counting on older cpuid code"
* tag 'soc-fixes-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (60 commits)
firmware: zynqmp: fix declarations for gcc-13
ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1l
ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp157c-emstamp-argon
ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-som
ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-som
ARM: dts: at91: sam9x60: fix the ddr clock for sam9x60
ARM: omap1: fix building gpio15xx
ARM: omap1: fix !ARCH_OMAP1_ANY link failures
firmware: raspberrypi: Fix type assignment
arm64: dts: qcom: msm8992-libra: Fix the memory map
arm64: dts: qcom: msm8992: Don't use sfpb mutex
PM: AVS: qcom-cpr: Fix an error handling path in cpr_probe()
arm64: dts: msm8994-angler: fix the memory map
arm64: dts: marvell: AC5/AC5X: Fix address for UART1
ARM: footbridge: drop unnecessary inclusion
Revert "ARM: dts: armada-39x: Fix compatible string for gpios"
Revert "ARM: dts: armada-38x: Fix compatible string for gpios"
ARM: pxa: enable PXA310/PXA320 for DT-only build
riscv: dts: sifive: fu740: fix size of pcie 32bit memory
soc: qcom: apr: Make qcom,protection-domain optional again
...
+265
-289
+2
-3
Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml
+2
-3
Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml
···
39
39
qcom,protection-domain:
40
40
$ref: /schemas/types.yaml#/definitions/string-array
41
41
description: |
42
-
Protection domain service name and path for APR service
43
-
possible values are::
42
+
Protection domain service name and path for APR service (if supported).
43
+
Possible values are::
44
44
"avs/audio", "msm/adsp/audio_pd".
45
45
"kernel/elf_loader", "msm/modem/wlan_pd".
46
46
"tms/servreg", "msm/adsp/audio_pd".
···
49
49
50
50
required:
51
51
- reg
52
-
- qcom,protection-domain
53
52
54
53
additionalProperties: true
+2
-2
arch/arm/boot/dts/armada-38x.dtsi
+2
-2
arch/arm/boot/dts/armada-38x.dtsi
···
304
304
};
305
305
306
306
gpio0: gpio@18100 {
307
-
compatible = "marvell,armadaxp-gpio",
307
+
compatible = "marvell,armada-370-gpio",
308
308
"marvell,orion-gpio";
309
309
reg = <0x18100 0x40>, <0x181c0 0x08>;
310
310
reg-names = "gpio", "pwm";
···
323
323
};
324
324
325
325
gpio1: gpio@18140 {
326
-
compatible = "marvell,armadaxp-gpio",
326
+
compatible = "marvell,armada-370-gpio",
327
327
"marvell,orion-gpio";
328
328
reg = <0x18140 0x40>, <0x181c8 0x08>;
329
329
reg-names = "gpio", "pwm";
+2
-2
arch/arm/boot/dts/armada-39x.dtsi
+2
-2
arch/arm/boot/dts/armada-39x.dtsi
···
213
213
};
214
214
215
215
gpio0: gpio@18100 {
216
-
compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
216
+
compatible = "marvell,orion-gpio";
217
217
reg = <0x18100 0x40>;
218
218
ngpios = <32>;
219
219
gpio-controller;
···
227
227
};
228
228
229
229
gpio1: gpio@18140 {
230
-
compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
230
+
compatible = "marvell,orion-gpio";
231
231
reg = <0x18140 0x40>;
232
232
ngpios = <28>;
233
233
gpio-controller;
+1
-1
arch/arm/boot/dts/imx53-ppd.dts
+1
-1
arch/arm/boot/dts/imx53-ppd.dts
-1
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
-1
arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+1
-1
arch/arm/boot/dts/imx6ul-pico-dwarf.dts
+1
-1
arch/arm/boot/dts/imx6ul-pico-dwarf.dts
+2
-2
arch/arm/boot/dts/imx7d-pico-dwarf.dts
+2
-2
arch/arm/boot/dts/imx7d-pico-dwarf.dts
···
32
32
};
33
33
34
34
&i2c1 {
35
-
clock_frequency = <100000>;
35
+
clock-frequency = <100000>;
36
36
pinctrl-names = "default";
37
37
pinctrl-0 = <&pinctrl_i2c1>;
38
38
status = "okay";
···
52
52
};
53
53
54
54
&i2c4 {
55
-
clock_frequency = <100000>;
55
+
clock-frequency = <100000>;
56
56
pinctrl-names = "default";
57
57
pinctrl-0 = <&pinctrl_i2c1>;
58
58
status = "okay";
+2
-2
arch/arm/boot/dts/imx7d-pico-nymph.dts
+2
-2
arch/arm/boot/dts/imx7d-pico-nymph.dts
···
43
43
};
44
44
45
45
&i2c1 {
46
-
clock_frequency = <100000>;
46
+
clock-frequency = <100000>;
47
47
pinctrl-names = "default";
48
48
pinctrl-0 = <&pinctrl_i2c1>;
49
49
status = "okay";
···
64
64
};
65
65
66
66
&i2c2 {
67
-
clock_frequency = <100000>;
67
+
clock-frequency = <100000>;
68
68
pinctrl-names = "default";
69
69
pinctrl-0 = <&pinctrl_i2c2>;
70
70
status = "okay";
+11
-11
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
+11
-11
arch/arm/boot/dts/qcom-apq8084-ifc6540.dts
···
19
19
serial@f995e000 {
20
20
status = "okay";
21
21
};
22
-
23
-
sdhci@f9824900 {
24
-
bus-width = <8>;
25
-
non-removable;
26
-
status = "okay";
27
-
};
28
-
29
-
sdhci@f98a4900 {
30
-
cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
31
-
bus-width = <4>;
32
-
};
33
22
};
23
+
};
24
+
25
+
&sdhc_1 {
26
+
bus-width = <8>;
27
+
non-removable;
28
+
status = "okay";
29
+
};
30
+
31
+
&sdhc_2 {
32
+
cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
33
+
bus-width = <4>;
34
34
};
+2
-2
arch/arm/boot/dts/qcom-apq8084.dtsi
+2
-2
arch/arm/boot/dts/qcom-apq8084.dtsi
···
421
421
status = "disabled";
422
422
};
423
423
424
-
mmc@f9824900 {
424
+
sdhc_1: mmc@f9824900 {
425
425
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
426
426
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
427
427
reg-names = "hc", "core";
···
434
434
status = "disabled";
435
435
};
436
436
437
-
mmc@f98a4900 {
437
+
sdhc_2: mmc@f98a4900 {
438
438
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
439
439
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
440
440
reg-names = "hc", "core";
+1
-1
arch/arm/boot/dts/sam9x60.dtsi
+1
-1
arch/arm/boot/dts/sam9x60.dtsi
···
564
564
mpddrc: mpddrc@ffffe800 {
565
565
compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
566
566
reg = <0xffffe800 0x200>;
567
-
clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
567
+
clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
568
568
clock-names = "ddrck", "mpddr";
569
569
};
570
570
+6
-2
arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi
+6
-2
arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi
···
101
101
102
102
&qspi {
103
103
pinctrl-names = "default", "sleep";
104
-
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
105
-
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
104
+
pinctrl-0 = <&qspi_clk_pins_a
105
+
&qspi_bk1_pins_a
106
+
&qspi_cs1_pins_a>;
107
+
pinctrl-1 = <&qspi_clk_sleep_pins_a
108
+
&qspi_bk1_sleep_pins_a
109
+
&qspi_cs1_sleep_pins_a>;
106
110
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
107
111
#address-cells = <1>;
108
112
#size-cells = <0>;
+6
-2
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
+6
-2
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
···
391
391
392
392
&qspi {
393
393
pinctrl-names = "default", "sleep";
394
-
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
395
-
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
394
+
pinctrl-0 = <&qspi_clk_pins_a
395
+
&qspi_bk1_pins_a
396
+
&qspi_cs1_pins_a>;
397
+
pinctrl-1 = <&qspi_clk_sleep_pins_a
398
+
&qspi_bk1_sleep_pins_a
399
+
&qspi_cs1_sleep_pins_a>;
396
400
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
397
401
#address-cells = <1>;
398
402
#size-cells = <0>;
+6
-2
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
+6
-2
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
···
428
428
429
429
&qspi {
430
430
pinctrl-names = "default", "sleep";
431
-
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
432
-
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
431
+
pinctrl-0 = <&qspi_clk_pins_a
432
+
&qspi_bk1_pins_a
433
+
&qspi_cs1_pins_a>;
434
+
pinctrl-1 = <&qspi_clk_sleep_pins_a
435
+
&qspi_bk1_sleep_pins_a
436
+
&qspi_cs1_sleep_pins_a>;
433
437
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
434
438
#address-cells = <1>;
435
439
#size-cells = <0>;
+6
-2
arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
+6
-2
arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
···
247
247
248
248
&qspi {
249
249
pinctrl-names = "default", "sleep";
250
-
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
251
-
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
250
+
pinctrl-0 = <&qspi_clk_pins_a
251
+
&qspi_bk1_pins_a
252
+
&qspi_cs1_pins_a>;
253
+
pinctrl-1 = <&qspi_clk_sleep_pins_a
254
+
&qspi_bk1_sleep_pins_a
255
+
&qspi_cs1_sleep_pins_a>;
252
256
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
253
257
#address-cells = <1>;
254
258
#size-cells = <0>;
+1
-1
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+1
-1
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+1
-1
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+1
-1
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
-1
arch/arm/mach-footbridge/isa-rtc.c
-1
arch/arm/mach-footbridge/isa-rtc.c
+1
arch/arm/mach-imx/cpu-imx25.c
+1
arch/arm/mach-imx/cpu-imx25.c
+1
arch/arm/mach-imx/cpu-imx27.c
+1
arch/arm/mach-imx/cpu-imx27.c
+1
arch/arm/mach-imx/cpu-imx31.c
+1
arch/arm/mach-imx/cpu-imx31.c
+1
arch/arm/mach-imx/cpu-imx35.c
+1
arch/arm/mach-imx/cpu-imx35.c
+1
arch/arm/mach-imx/cpu-imx5.c
+1
arch/arm/mach-imx/cpu-imx5.c
+1
-4
arch/arm/mach-omap1/Kconfig
+1
-4
arch/arm/mach-omap1/Kconfig
···
4
4
depends on ARCH_MULTI_V4T || ARCH_MULTI_V5
5
5
depends on CPU_LITTLE_ENDIAN
6
6
depends on ATAGS
7
+
select ARCH_OMAP
7
8
select ARCH_HAS_HOLES_MEMORYMODEL
8
9
select ARCH_OMAP
9
10
select CLKSRC_MMIO
···
45
44
select ARCH_OMAP_OTG
46
45
select CPU_ARM926T
47
46
select OMAP_DM_TIMER
48
-
49
-
config ARCH_OMAP1_ANY
50
-
select ARCH_OMAP
51
-
def_bool ARCH_OMAP730 || ARCH_OMAP850 || ARCH_OMAP15XX || ARCH_OMAP16XX
52
47
53
48
config ARCH_OMAP
54
49
bool
-4
arch/arm/mach-omap1/Makefile
-4
arch/arm/mach-omap1/Makefile
···
3
3
# Makefile for the linux kernel.
4
4
#
5
5
6
-
ifdef CONFIG_ARCH_OMAP1_ANY
7
-
8
6
# Common support
9
7
obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
10
8
serial.o devices.o dma.o omap-dma.o fb.o
···
57
59
obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o
58
60
obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o
59
61
obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o
60
-
61
-
endif
+1
arch/arm/mach-omap1/gpio15xx.c
+1
arch/arm/mach-omap1/gpio15xx.c
+15
-17
arch/arm/mach-omap1/io.c
+15
-17
arch/arm/mach-omap1/io.c
···
22
22
* The machine specific code may provide the extra mapping besides the
23
23
* default mapping provided here.
24
24
*/
25
-
static struct map_desc omap_io_desc[] __initdata = {
25
+
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
26
+
static struct map_desc omap7xx_io_desc[] __initdata = {
26
27
{
27
28
.virtual = OMAP1_IO_VIRT,
28
29
.pfn = __phys_to_pfn(OMAP1_IO_PHYS),
29
30
.length = OMAP1_IO_SIZE,
30
31
.type = MT_DEVICE
31
-
}
32
-
};
33
-
34
-
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
35
-
static struct map_desc omap7xx_io_desc[] __initdata = {
32
+
},
36
33
{
37
34
.virtual = OMAP7XX_DSP_BASE,
38
35
.pfn = __phys_to_pfn(OMAP7XX_DSP_START),
···
47
50
#ifdef CONFIG_ARCH_OMAP15XX
48
51
static struct map_desc omap1510_io_desc[] __initdata = {
49
52
{
53
+
.virtual = OMAP1_IO_VIRT,
54
+
.pfn = __phys_to_pfn(OMAP1_IO_PHYS),
55
+
.length = OMAP1_IO_SIZE,
56
+
.type = MT_DEVICE
57
+
},
58
+
{
50
59
.virtual = OMAP1510_DSP_BASE,
51
60
.pfn = __phys_to_pfn(OMAP1510_DSP_START),
52
61
.length = OMAP1510_DSP_SIZE,
···
69
66
#if defined(CONFIG_ARCH_OMAP16XX)
70
67
static struct map_desc omap16xx_io_desc[] __initdata = {
71
68
{
69
+
.virtual = OMAP1_IO_VIRT,
70
+
.pfn = __phys_to_pfn(OMAP1_IO_PHYS),
71
+
.length = OMAP1_IO_SIZE,
72
+
.type = MT_DEVICE
73
+
},
74
+
{
72
75
.virtual = OMAP16XX_DSP_BASE,
73
76
.pfn = __phys_to_pfn(OMAP16XX_DSP_START),
74
77
.length = OMAP16XX_DSP_SIZE,
···
88
79
};
89
80
#endif
90
81
91
-
/*
92
-
* Maps common IO regions for omap1
93
-
*/
94
-
static void __init omap1_map_common_io(void)
95
-
{
96
-
iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
97
-
}
98
-
99
82
#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
100
83
void __init omap7xx_map_io(void)
101
84
{
102
-
omap1_map_common_io();
103
85
iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
104
86
}
105
87
#endif
···
98
98
#ifdef CONFIG_ARCH_OMAP15XX
99
99
void __init omap15xx_map_io(void)
100
100
{
101
-
omap1_map_common_io();
102
101
iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
103
102
}
104
103
#endif
···
105
106
#if defined(CONFIG_ARCH_OMAP16XX)
106
107
void __init omap16xx_map_io(void)
107
108
{
108
-
omap1_map_common_io();
109
109
iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
110
110
}
111
111
#endif
-21
arch/arm/mach-omap1/mcbsp.c
-21
arch/arm/mach-omap1/mcbsp.c
···
89
89
#define OMAP1610_MCBSP2_BASE 0xfffb1000
90
90
#define OMAP1610_MCBSP3_BASE 0xe1017000
91
91
92
-
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
93
92
struct resource omap7xx_mcbsp_res[][6] = {
94
93
{
95
94
{
···
158
159
};
159
160
#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
160
161
#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
161
-
#else
162
-
#define omap7xx_mcbsp_res_0 NULL
163
-
#define omap7xx_mcbsp_pdata NULL
164
-
#define OMAP7XX_MCBSP_RES_SZ 0
165
-
#define OMAP7XX_MCBSP_COUNT 0
166
-
#endif
167
162
168
-
#ifdef CONFIG_ARCH_OMAP15XX
169
163
struct resource omap15xx_mcbsp_res[][6] = {
170
164
{
171
165
{
···
258
266
};
259
267
#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
260
268
#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
261
-
#else
262
-
#define omap15xx_mcbsp_res_0 NULL
263
-
#define omap15xx_mcbsp_pdata NULL
264
-
#define OMAP15XX_MCBSP_RES_SZ 0
265
-
#define OMAP15XX_MCBSP_COUNT 0
266
-
#endif
267
269
268
-
#ifdef CONFIG_ARCH_OMAP16XX
269
270
struct resource omap16xx_mcbsp_res[][6] = {
270
271
{
271
272
{
···
358
373
};
359
374
#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
360
375
#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
361
-
#else
362
-
#define omap16xx_mcbsp_res_0 NULL
363
-
#define omap16xx_mcbsp_pdata NULL
364
-
#define OMAP16XX_MCBSP_RES_SZ 0
365
-
#define OMAP16XX_MCBSP_COUNT 0
366
-
#endif
367
376
368
377
static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
369
378
struct omap_mcbsp_platform_data *config, int size)
-7
arch/arm/mach-omap1/pm.h
-7
arch/arm/mach-omap1/pm.h
···
106
106
#define OMAP7XX_IDLECT3 0xfffece24
107
107
#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
108
108
109
-
#if !defined(CONFIG_ARCH_OMAP730) && \
110
-
!defined(CONFIG_ARCH_OMAP850) && \
111
-
!defined(CONFIG_ARCH_OMAP15XX) && \
112
-
!defined(CONFIG_ARCH_OMAP16XX)
113
-
#warning "Power management for this processor not implemented yet"
114
-
#endif
115
-
116
109
#ifndef __ASSEMBLER__
117
110
118
111
#include <linux/clk.h>
+2
arch/arm/mach-pxa/Kconfig
+2
arch/arm/mach-pxa/Kconfig
+2
-6
arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
+2
-6
arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+1
-1
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+2
-2
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
···
120
120
&ecspi2 {
121
121
pinctrl-names = "default";
122
122
pinctrl-0 = <&pinctrl_espi2>;
123
-
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
123
+
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
124
124
status = "okay";
125
125
126
126
eeprom@0 {
···
316
316
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
317
317
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
318
318
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
319
-
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
319
+
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x41
320
320
>;
321
321
};
322
322
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+1
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
+1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
···
9
9
simple-audio-card,bitclock-master = <&dailink_master>;
10
10
simple-audio-card,format = "i2s";
11
11
simple-audio-card,frame-master = <&dailink_master>;
12
+
simple-audio-card,mclk-fs = <256>;
12
13
simple-audio-card,name = "imx8mm-wm8904";
13
14
simple-audio-card,routing =
14
15
"Headphone Jack", "HPOUTL",
+1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
+1
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
···
11
11
simple-audio-card,bitclock-master = <&dailink_master>;
12
12
simple-audio-card,format = "i2s";
13
13
simple-audio-card,frame-master = <&dailink_master>;
14
+
simple-audio-card,mclk-fs = <256>;
14
15
simple-audio-card,name = "imx8mm-nau8822";
15
16
simple-audio-card,routing =
16
17
"Headphones", "LHP",
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
-10
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
-10
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
···
99
99
100
100
regulators {
101
101
buck1: BUCK1 {
102
-
regulator-compatible = "BUCK1";
103
102
regulator-min-microvolt = <600000>;
104
103
regulator-max-microvolt = <2187500>;
105
104
regulator-boot-on;
···
107
108
};
108
109
109
110
buck2: BUCK2 {
110
-
regulator-compatible = "BUCK2";
111
111
regulator-min-microvolt = <600000>;
112
112
regulator-max-microvolt = <2187500>;
113
113
regulator-boot-on;
···
117
119
};
118
120
119
121
buck4: BUCK4 {
120
-
regulator-compatible = "BUCK4";
121
122
regulator-min-microvolt = <600000>;
122
123
regulator-max-microvolt = <3400000>;
123
124
regulator-boot-on;
···
124
127
};
125
128
126
129
buck5: BUCK5 {
127
-
regulator-compatible = "BUCK5";
128
130
regulator-min-microvolt = <600000>;
129
131
regulator-max-microvolt = <3400000>;
130
132
regulator-boot-on;
···
131
135
};
132
136
133
137
buck6: BUCK6 {
134
-
regulator-compatible = "BUCK6";
135
138
regulator-min-microvolt = <600000>;
136
139
regulator-max-microvolt = <3400000>;
137
140
regulator-boot-on;
···
138
143
};
139
144
140
145
ldo1: LDO1 {
141
-
regulator-compatible = "LDO1";
142
146
regulator-min-microvolt = <1600000>;
143
147
regulator-max-microvolt = <3300000>;
144
148
regulator-boot-on;
···
145
151
};
146
152
147
153
ldo2: LDO2 {
148
-
regulator-compatible = "LDO2";
149
154
regulator-min-microvolt = <800000>;
150
155
regulator-max-microvolt = <1150000>;
151
156
regulator-boot-on;
···
152
159
};
153
160
154
161
ldo3: LDO3 {
155
-
regulator-compatible = "LDO3";
156
162
regulator-min-microvolt = <800000>;
157
163
regulator-max-microvolt = <3300000>;
158
164
regulator-boot-on;
···
159
167
};
160
168
161
169
ldo4: LDO4 {
162
-
regulator-compatible = "LDO4";
163
170
regulator-min-microvolt = <800000>;
164
171
regulator-max-microvolt = <3300000>;
165
172
};
166
173
167
174
ldo5: LDO5 {
168
-
regulator-compatible = "LDO5";
169
175
regulator-min-microvolt = <1800000>;
170
176
regulator-max-microvolt = <3300000>;
171
177
regulator-boot-on;
+8
-7
arch/arm64/boot/dts/freescale/imx8mp.dtsi
+8
-7
arch/arm64/boot/dts/freescale/imx8mp.dtsi
···
524
524
compatible = "fsl,imx8mp-gpc";
525
525
reg = <0x303a0000 0x1000>;
526
526
interrupt-parent = <&gic>;
527
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
527
528
interrupt-controller;
528
529
#interrupt-cells = <3>;
529
530
···
591
590
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
592
591
};
593
592
594
-
pgc_hsiomix: power-domains@17 {
593
+
pgc_hsiomix: power-domain@17 {
595
594
#power-domain-cells = <0>;
596
595
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
597
596
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
···
1298
1297
reg = <0x32f10100 0x8>,
1299
1298
<0x381f0000 0x20>;
1300
1299
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1301
-
<&clk IMX8MP_CLK_USB_ROOT>;
1300
+
<&clk IMX8MP_CLK_USB_SUSP>;
1302
1301
clock-names = "hsio", "suspend";
1303
1302
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1304
1303
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
···
1311
1310
usb_dwc3_0: usb@38100000 {
1312
1311
compatible = "snps,dwc3";
1313
1312
reg = <0x38100000 0x10000>;
1314
-
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1313
+
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1315
1314
<&clk IMX8MP_CLK_USB_CORE_REF>,
1316
-
<&clk IMX8MP_CLK_USB_ROOT>;
1315
+
<&clk IMX8MP_CLK_USB_SUSP>;
1317
1316
clock-names = "bus_early", "ref", "suspend";
1318
1317
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1319
1318
phys = <&usb3_phy0>, <&usb3_phy0>;
···
1340
1339
reg = <0x32f10108 0x8>,
1341
1340
<0x382f0000 0x20>;
1342
1341
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1343
-
<&clk IMX8MP_CLK_USB_ROOT>;
1342
+
<&clk IMX8MP_CLK_USB_SUSP>;
1344
1343
clock-names = "hsio", "suspend";
1345
1344
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1346
1345
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
···
1353
1352
usb_dwc3_1: usb@38200000 {
1354
1353
compatible = "snps,dwc3";
1355
1354
reg = <0x38200000 0x10000>;
1356
-
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1355
+
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1357
1356
<&clk IMX8MP_CLK_USB_CORE_REF>,
1358
-
<&clk IMX8MP_CLK_USB_ROOT>;
1357
+
<&clk IMX8MP_CLK_USB_SUSP>;
1359
1358
clock-names = "bus_early", "ref", "suspend";
1360
1359
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1361
1360
phys = <&usb3_phy1>, <&usb3_phy1>;
+2
-2
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
···
133
133
pinctrl-0 = <&pinctrl_i2c1>;
134
134
status = "okay";
135
135
136
-
i2cmux@70 {
136
+
i2c-mux@70 {
137
137
compatible = "nxp,pca9546";
138
138
pinctrl-names = "default";
139
139
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
···
216
216
pinctrl-0 = <&pinctrl_i2c4>;
217
217
status = "okay";
218
218
219
-
pca9546: i2cmux@70 {
219
+
pca9546: i2c-mux@70 {
220
220
compatible = "nxp,pca9546";
221
221
reg = <0x70>;
222
222
#address-cells = <1>;
+2
-2
arch/arm64/boot/dts/freescale/imx8mq-thor96.dts
+2
-2
arch/arm64/boot/dts/freescale/imx8mq-thor96.dts
···
339
339
bus-width = <4>;
340
340
non-removable;
341
341
no-sd;
342
-
no-emmc;
342
+
no-mmc;
343
343
status = "okay";
344
344
345
345
brcmf: wifi@1 {
···
359
359
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
360
360
bus-width = <4>;
361
361
no-sdio;
362
-
no-emmc;
362
+
no-mmc;
363
363
disable-wp;
364
364
status = "okay";
365
365
};
+1
-1
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+1
-1
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+3
-3
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+3
-3
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
···
74
74
75
75
pinctrl_usdhc1: usdhc1grp {
76
76
fsl,pins = <
77
-
MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
77
+
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
78
78
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
79
79
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
80
80
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
···
84
84
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
85
85
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
86
86
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
87
-
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
87
+
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
88
88
>;
89
89
};
90
90
···
102
102
103
103
pinctrl_usdhc2: usdhc2grp {
104
104
fsl,pins = <
105
-
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
105
+
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
106
106
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
107
107
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
108
108
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+1
-1
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+1
-1
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+6
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
+6
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
···
3
3
* Copyright (c) 2015, LGE Inc. All rights reserved.
4
4
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
5
5
* Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>
6
+
* Copyright (c) 2022, Dominik Kobinski <dominikkobinski314@gmail.com>
6
7
*/
7
8
8
9
/dts-v1/;
···
50
49
51
50
cont_splash_mem: memory@3400000 {
52
51
reg = <0 0x03400000 0 0x1200000>;
52
+
no-map;
53
+
};
54
+
55
+
removed_region: reserved@5000000 {
56
+
reg = <0 0x05000000 0 0x2200000>;
53
57
no-map;
54
58
};
55
59
};
+60
-17
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
+60
-17
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
···
11
11
#include <dt-bindings/gpio/gpio.h>
12
12
#include <dt-bindings/input/gpio-keys.h>
13
13
14
+
/delete-node/ &adsp_mem;
15
+
/delete-node/ &audio_mem;
16
+
/delete-node/ &mpss_mem;
17
+
/delete-node/ &peripheral_region;
18
+
/delete-node/ &rmtfs_mem;
19
+
14
20
/ {
15
21
model = "Xiaomi Mi 4C";
16
22
compatible = "xiaomi,libra", "qcom,msm8992";
···
76
70
#size-cells = <2>;
77
71
ranges;
78
72
79
-
/* This is for getting crash logs using Android downstream kernels */
73
+
memory_hole: hole@6400000 {
74
+
reg = <0 0x06400000 0 0x600000>;
75
+
no-map;
76
+
};
77
+
78
+
memory_hole2: hole2@6c00000 {
79
+
reg = <0 0x06c00000 0 0x2400000>;
80
+
no-map;
81
+
};
82
+
83
+
mpss_mem: mpss@9000000 {
84
+
reg = <0 0x09000000 0 0x5a00000>;
85
+
no-map;
86
+
};
87
+
88
+
tzapp: tzapp@ea00000 {
89
+
reg = <0 0x0ea00000 0 0x1900000>;
90
+
no-map;
91
+
};
92
+
93
+
mdm_rfsa_mem: mdm-rfsa@ca0b0000 {
94
+
reg = <0 0xca0b0000 0 0x10000>;
95
+
no-map;
96
+
};
97
+
98
+
rmtfs_mem: rmtfs@ca100000 {
99
+
compatible = "qcom,rmtfs-mem";
100
+
reg = <0 0xca100000 0 0x180000>;
101
+
no-map;
102
+
103
+
qcom,client-id = <1>;
104
+
};
105
+
106
+
audio_mem: audio@cb400000 {
107
+
reg = <0 0xcb000000 0 0x400000>;
108
+
no-mem;
109
+
};
110
+
111
+
qseecom_mem: qseecom@cb400000 {
112
+
reg = <0 0xcb400000 0 0x1c00000>;
113
+
no-mem;
114
+
};
115
+
116
+
adsp_rfsa_mem: adsp-rfsa@cd000000 {
117
+
reg = <0 0xcd000000 0 0x10000>;
118
+
no-map;
119
+
};
120
+
121
+
sensor_rfsa_mem: sensor-rfsa@cd010000 {
122
+
reg = <0 0xcd010000 0 0x10000>;
123
+
no-map;
124
+
};
125
+
80
126
ramoops@dfc00000 {
81
127
compatible = "ramoops";
82
-
reg = <0x0 0xdfc00000 0x0 0x40000>;
128
+
reg = <0 0xdfc00000 0 0x40000>;
83
129
console-size = <0x10000>;
84
130
record-size = <0x10000>;
85
131
ftrace-size = <0x10000>;
86
132
pmsg-size = <0x20000>;
87
-
};
88
-
89
-
modem_region: modem_region@9000000 {
90
-
reg = <0x0 0x9000000 0x0 0x5a00000>;
91
-
no-map;
92
-
};
93
-
94
-
tzapp: modem_region@ea00000 {
95
-
reg = <0x0 0xea00000 0x0 0x1900000>;
96
-
no-map;
97
133
};
98
134
};
99
135
};
···
176
128
177
129
&blsp2_uart2 {
178
130
status = "okay";
179
-
};
180
-
181
-
&peripheral_region {
182
-
reg = <0x0 0x7400000 0x0 0x1c00000>;
183
-
no-map;
184
131
};
185
132
186
133
&pm8994_spmi_regulators {
-4
arch/arm64/boot/dts/qcom/msm8992.dtsi
-4
arch/arm64/boot/dts/qcom/msm8992.dtsi
···
37
37
compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc";
38
38
};
39
39
40
-
&tcsr_mutex {
41
-
compatible = "qcom,sfpb-mutex";
42
-
};
43
-
44
40
&timer {
45
41
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46
42
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+16
-3
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
+16
-3
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
···
9
9
10
10
#include "msm8994.dtsi"
11
11
12
-
/* Angler's firmware does not report where the memory is allocated */
13
-
/delete-node/ &cont_splash_mem;
14
-
15
12
/ {
16
13
model = "Huawei Nexus 6P";
17
14
compatible = "huawei,angler", "qcom,msm8994";
···
24
27
25
28
chosen {
26
29
stdout-path = "serial0:115200n8";
30
+
};
31
+
32
+
reserved-memory {
33
+
#address-cells = <2>;
34
+
#size-cells = <2>;
35
+
ranges;
36
+
37
+
tzapp_mem: tzapp@4800000 {
38
+
reg = <0 0x04800000 0 0x1900000>;
39
+
no-map;
40
+
};
41
+
42
+
removed_region: reserved@6300000 {
43
+
reg = <0 0x06300000 0 0xD00000>;
44
+
no-map;
45
+
};
27
46
};
28
47
};
29
48
+26
-57
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+26
-57
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
···
10
10
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
11
11
#include <dt-bindings/interrupt-controller/arm-gic.h>
12
12
#include <dt-bindings/mailbox/qcom-ipcc.h>
13
+
#include <dt-bindings/phy/phy-qcom-qmp.h>
13
14
#include <dt-bindings/power/qcom-rpmpd.h>
14
15
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
15
16
#include <dt-bindings/thermal/thermal.h>
···
763
762
<0>,
764
763
<0>,
765
764
<0>,
766
-
<&usb_0_ssphy>,
765
+
<&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
767
766
<0>,
768
767
<0>,
769
768
<0>,
···
771
770
<0>,
772
771
<0>,
773
772
<0>,
774
-
<&usb_1_ssphy>,
773
+
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
775
774
<0>,
776
775
<0>,
777
776
<0>,
···
1674
1673
};
1675
1674
};
1676
1675
1677
-
usb_0_qmpphy: phy-wrapper@88ec000 {
1676
+
usb_0_qmpphy: phy@88eb000 {
1678
1677
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1679
-
reg = <0 0x088ec000 0 0x1e4>,
1680
-
<0 0x088eb000 0 0x40>,
1681
-
<0 0x088ed000 0 0x1c8>;
1682
-
#address-cells = <2>;
1683
-
#size-cells = <2>;
1684
-
ranges;
1678
+
reg = <0 0x088eb000 0 0x4000>;
1685
1679
1686
1680
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1687
-
<&rpmhcc RPMH_CXO_CLK>,
1688
1681
<&gcc GCC_USB4_EUD_CLKREF_CLK>,
1689
-
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1690
-
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1691
-
1692
-
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1693
-
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1694
-
reset-names = "phy", "common";
1682
+
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1683
+
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1684
+
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1695
1685
1696
1686
power-domains = <&gcc USB30_PRIM_GDSC>;
1697
1687
1698
-
status = "disabled";
1688
+
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1689
+
<&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
1690
+
reset-names = "phy", "common";
1699
1691
1700
-
usb_0_ssphy: usb3-phy@88eb400 {
1701
-
reg = <0 0x088eb400 0 0x100>,
1702
-
<0 0x088eb600 0 0x3ec>,
1703
-
<0 0x088ec400 0 0x364>,
1704
-
<0 0x088eba00 0 0x100>,
1705
-
<0 0x088ebc00 0 0x3ec>,
1706
-
<0 0x088ec200 0 0x18>;
1707
-
#phy-cells = <0>;
1708
-
#clock-cells = <0>;
1709
-
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1710
-
clock-names = "pipe0";
1711
-
clock-output-names = "usb0_phy_pipe_clk_src";
1712
-
};
1692
+
#clock-cells = <1>;
1693
+
#phy-cells = <1>;
1694
+
1695
+
status = "disabled";
1713
1696
};
1714
1697
1715
1698
usb_1_hsphy: phy@8902000 {
···
1710
1725
status = "disabled";
1711
1726
};
1712
1727
1713
-
usb_1_qmpphy: phy-wrapper@8904000 {
1728
+
usb_1_qmpphy: phy@8903000 {
1714
1729
compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1715
-
reg = <0 0x08904000 0 0x1e4>,
1716
-
<0 0x08903000 0 0x40>,
1717
-
<0 0x08905000 0 0x1c8>;
1718
-
#address-cells = <2>;
1719
-
#size-cells = <2>;
1720
-
ranges;
1730
+
reg = <0 0x08903000 0 0x4000>;
1721
1731
1722
1732
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1723
-
<&rpmhcc RPMH_CXO_CLK>,
1724
1733
<&gcc GCC_USB4_CLKREF_CLK>,
1725
-
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1726
-
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1734
+
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1735
+
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1736
+
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1737
+
1738
+
power-domains = <&gcc USB30_SEC_GDSC>;
1727
1739
1728
1740
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1729
1741
<&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1730
1742
reset-names = "phy", "common";
1731
1743
1732
-
power-domains = <&gcc USB30_SEC_GDSC>;
1744
+
#clock-cells = <1>;
1745
+
#phy-cells = <1>;
1733
1746
1734
1747
status = "disabled";
1735
-
1736
-
usb_1_ssphy: usb3-phy@8903400 {
1737
-
reg = <0 0x08903400 0 0x100>,
1738
-
<0 0x08903600 0 0x3ec>,
1739
-
<0 0x08904400 0 0x364>,
1740
-
<0 0x08903a00 0 0x100>,
1741
-
<0 0x08903c00 0 0x3ec>,
1742
-
<0 0x08904200 0 0x18>;
1743
-
#phy-cells = <0>;
1744
-
#clock-cells = <0>;
1745
-
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1746
-
clock-names = "pipe0";
1747
-
clock-output-names = "usb1_phy_pipe_clk_src";
1748
-
};
1749
1748
};
1750
1749
1751
1750
pmu@9091000 {
···
1879
1910
reg = <0 0x0a600000 0 0xcd00>;
1880
1911
interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1881
1912
iommus = <&apps_smmu 0x820 0x0>;
1882
-
phys = <&usb_0_hsphy>, <&usb_0_ssphy>;
1913
+
phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
1883
1914
phy-names = "usb2-phy", "usb3-phy";
1884
1915
};
1885
1916
};
···
1933
1964
reg = <0 0x0a800000 0 0xcd00>;
1934
1965
interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1935
1966
iommus = <&apps_smmu 0x860 0x0>;
1936
-
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1967
+
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
1937
1968
phy-names = "usb2-phy", "usb3-phy";
1938
1969
};
1939
1970
};
-1
arch/arm64/boot/dts/qcom/sm8250.dtsi
-1
arch/arm64/boot/dts/qcom/sm8250.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8350.dtsi
+2
-2
arch/arm64/boot/dts/qcom/sm8350.dtsi
···
2382
2382
<&rpmhcc RPMH_CXO_CLK>;
2383
2383
clock-names = "iface", "core", "xo";
2384
2384
resets = <&gcc GCC_SDCC2_BCR>;
2385
-
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2386
-
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2385
+
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
2386
+
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
2387
2387
interconnect-names = "sdhc-ddr","cpu-sdhc";
2388
2388
iommus = <&apps_smmu 0x4a0 0x0>;
2389
2389
power-domains = <&rpmhpd SM8350_CX>;
+1
-1
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+1
-1
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
···
328
328
bus-range = <0x0 0xff>;
329
329
ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
330
330
<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
331
-
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
331
+
<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000>, /* mem */
332
332
<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
333
333
num-lanes = <0x8>;
334
334
interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
+2
drivers/firmware/arm_scmi/driver.c
+2
drivers/firmware/arm_scmi/driver.c
+6
-3
drivers/firmware/arm_scmi/shmem.c
+6
-3
drivers/firmware/arm_scmi/shmem.c
···
81
81
void shmem_fetch_response(struct scmi_shared_mem __iomem *shmem,
82
82
struct scmi_xfer *xfer)
83
83
{
84
+
size_t len = ioread32(&shmem->length);
85
+
84
86
xfer->hdr.status = ioread32(shmem->msg_payload);
85
87
/* Skip the length of header and status in shmem area i.e 8 bytes */
86
-
xfer->rx.len = min_t(size_t, xfer->rx.len,
87
-
ioread32(&shmem->length) - 8);
88
+
xfer->rx.len = min_t(size_t, xfer->rx.len, len > 8 ? len - 8 : 0);
88
89
89
90
/* Take a copy to the rx buffer.. */
90
91
memcpy_fromio(xfer->rx.buf, shmem->msg_payload + 4, xfer->rx.len);
···
94
93
void shmem_fetch_notification(struct scmi_shared_mem __iomem *shmem,
95
94
size_t max_len, struct scmi_xfer *xfer)
96
95
{
96
+
size_t len = ioread32(&shmem->length);
97
+
97
98
/* Skip only the length of header in shmem area i.e 4 bytes */
98
-
xfer->rx.len = min_t(size_t, max_len, ioread32(&shmem->length) - 4);
99
+
xfer->rx.len = min_t(size_t, max_len, len > 4 ? len - 4 : 0);
99
100
100
101
/* Take a copy to the rx buffer.. */
101
102
memcpy_fromio(xfer->rx.buf, shmem->msg_payload, xfer->rx.len);
+6
-1
drivers/firmware/arm_scmi/virtio.c
+6
-1
drivers/firmware/arm_scmi/virtio.c
···
160
160
}
161
161
162
162
vioch->shutdown_done = &vioch_shutdown_done;
163
-
virtio_break_device(vioch->vqueue->vdev);
164
163
if (!vioch->is_rx && vioch->deferred_tx_wq)
165
164
/* Cannot be kicked anymore after this...*/
166
165
vioch->deferred_tx_wq = NULL;
···
481
482
struct scmi_chan_info *cinfo = p;
482
483
struct scmi_vio_channel *vioch = cinfo->transport_info;
483
484
485
+
/*
486
+
* Break device to inhibit further traffic flowing while shutting down
487
+
* the channels: doing it later holding vioch->lock creates unsafe
488
+
* locking dependency chains as reported by LOCKDEP.
489
+
*/
490
+
virtio_break_device(vioch->vqueue->vdev);
484
491
scmi_vio_channel_cleanup_sync(vioch);
485
492
486
493
scmi_free_channel(cinfo, data, id);
+2
-4
drivers/memory/atmel-sdramc.c
+2
-4
drivers/memory/atmel-sdramc.c
···
47
47
caps = of_device_get_match_data(&pdev->dev);
48
48
49
49
if (caps->has_ddrck) {
50
-
clk = devm_clk_get(&pdev->dev, "ddrck");
50
+
clk = devm_clk_get_enabled(&pdev->dev, "ddrck");
51
51
if (IS_ERR(clk))
52
52
return PTR_ERR(clk);
53
-
clk_prepare_enable(clk);
54
53
}
55
54
56
55
if (caps->has_mpddr_clk) {
57
-
clk = devm_clk_get(&pdev->dev, "mpddr");
56
+
clk = devm_clk_get_enabled(&pdev->dev, "mpddr");
58
57
if (IS_ERR(clk)) {
59
58
pr_err("AT91 RAMC: couldn't get mpddr clock\n");
60
59
return PTR_ERR(clk);
61
60
}
62
-
clk_prepare_enable(clk);
63
61
}
64
62
65
63
return 0;
+1
-2
drivers/memory/mvebu-devbus.c
+1
-2
drivers/memory/mvebu-devbus.c
···
280
280
if (IS_ERR(devbus->base))
281
281
return PTR_ERR(devbus->base);
282
282
283
-
clk = devm_clk_get(&pdev->dev, NULL);
283
+
clk = devm_clk_get_enabled(&pdev->dev, NULL);
284
284
if (IS_ERR(clk))
285
285
return PTR_ERR(clk);
286
-
clk_prepare_enable(clk);
287
286
288
287
/*
289
288
* Obtain clock period in picoseconds,
+2
-1
drivers/memory/omap-gpmc.c
+2
-1
drivers/memory/omap-gpmc.c
-36
drivers/memory/tegra/tegra186.c
-36
drivers/memory/tegra/tegra186.c
···
22
22
#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
23
23
#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
24
24
25
-
static void tegra186_mc_program_sid(struct tegra_mc *mc)
26
-
{
27
-
unsigned int i;
28
-
29
-
for (i = 0; i < mc->soc->num_clients; i++) {
30
-
const struct tegra_mc_client *client = &mc->soc->clients[i];
31
-
u32 override, security;
32
-
33
-
override = readl(mc->regs + client->regs.sid.override);
34
-
security = readl(mc->regs + client->regs.sid.security);
35
-
36
-
dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
37
-
client->name, override, security);
38
-
39
-
dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
40
-
client->name);
41
-
writel(client->sid, mc->regs + client->regs.sid.override);
42
-
43
-
override = readl(mc->regs + client->regs.sid.override);
44
-
security = readl(mc->regs + client->regs.sid.security);
45
-
46
-
dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
47
-
client->name, override, security);
48
-
}
49
-
}
50
-
51
25
static int tegra186_mc_probe(struct tegra_mc *mc)
52
26
{
53
27
struct platform_device *pdev = to_platform_device(mc->dev);
···
59
85
if (err < 0)
60
86
return err;
61
87
62
-
tegra186_mc_program_sid(mc);
63
-
64
88
return 0;
65
89
}
66
90
67
91
static void tegra186_mc_remove(struct tegra_mc *mc)
68
92
{
69
93
of_platform_depopulate(mc->dev);
70
-
}
71
-
72
-
static int tegra186_mc_resume(struct tegra_mc *mc)
73
-
{
74
-
tegra186_mc_program_sid(mc);
75
-
76
-
return 0;
77
94
}
78
95
79
96
#if IS_ENABLED(CONFIG_IOMMU_API)
···
138
173
const struct tegra_mc_ops tegra186_mc_ops = {
139
174
.probe = tegra186_mc_probe,
140
175
.remove = tegra186_mc_remove,
141
-
.resume = tegra186_mc_resume,
142
176
.probe_device = tegra186_mc_probe_device,
143
177
.handle_irq = tegra30_mc_handle_irq,
144
178
};
+1
-1
drivers/reset/Kconfig
+1
-1
drivers/reset/Kconfig
···
257
257
258
258
config RESET_TI_SCI
259
259
tristate "TI System Control Interface (TI-SCI) reset driver"
260
-
depends on TI_SCI_PROTOCOL || COMPILE_TEST
260
+
depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
261
261
help
262
262
This enables the reset driver support over TI System Control Interface
263
263
available on some new TI's SoCs. If you wish to use reset resources
+1
-3
drivers/reset/reset-uniphier-glue.c
+1
-3
drivers/reset/reset-uniphier-glue.c
···
47
47
struct device *dev = &pdev->dev;
48
48
struct uniphier_glue_reset_priv *priv;
49
49
struct resource *res;
50
-
resource_size_t size;
51
50
int i, ret;
52
51
53
52
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
···
59
60
return -EINVAL;
60
61
61
62
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
62
-
size = resource_size(res);
63
63
priv->rdata.membase = devm_ioremap_resource(dev, res);
64
64
if (IS_ERR(priv->rdata.membase))
65
65
return PTR_ERR(priv->rdata.membase);
···
94
96
95
97
spin_lock_init(&priv->rdata.lock);
96
98
priv->rdata.rcdev.owner = THIS_MODULE;
97
-
priv->rdata.rcdev.nr_resets = size * BITS_PER_BYTE;
99
+
priv->rdata.rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
98
100
priv->rdata.rcdev.ops = &reset_simple_ops;
99
101
priv->rdata.rcdev.of_node = dev->of_node;
100
102
priv->rdata.active_low = true;
+4
-3
drivers/soc/imx/imx8mp-blk-ctrl.c
+4
-3
drivers/soc/imx/imx8mp-blk-ctrl.c
···
212
212
break;
213
213
case IMX8MP_HDMIBLK_PD_LCDIF:
214
214
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
215
-
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
215
+
BIT(16) | BIT(17) | BIT(18) |
216
216
BIT(19) | BIT(20));
217
217
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
218
218
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,
···
241
241
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));
242
242
break;
243
243
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
244
+
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
244
245
regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
245
246
regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
246
247
regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
···
271
270
BIT(4) | BIT(5) | BIT(6));
272
271
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));
273
272
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,
274
-
BIT(7) | BIT(16) | BIT(17) | BIT(18) |
273
+
BIT(16) | BIT(17) | BIT(18) |
275
274
BIT(19) | BIT(20));
276
275
break;
277
276
case IMX8MP_HDMIBLK_PD_PAI:
···
299
298
case IMX8MP_HDMIBLK_PD_HDMI_TX_PHY:
300
299
regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
301
300
regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
301
+
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(7));
302
302
regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
303
303
break;
304
304
case IMX8MP_HDMIBLK_PD_HDCP:
···
592
590
ret = PTR_ERR(domain->power_dev);
593
591
goto cleanup_pds;
594
592
}
595
-
dev_set_name(domain->power_dev, "%s", data->name);
596
593
597
594
domain->genpd.name = data->name;
598
595
domain->genpd.power_on = imx8mp_blk_ctrl_power_on;
+2
-2
drivers/soc/imx/soc-imx8m.c
+2
-2
drivers/soc/imx/soc-imx8m.c
+2
-1
drivers/soc/qcom/apr.c
+2
-1
drivers/soc/qcom/apr.c
···
461
461
goto out;
462
462
}
463
463
464
+
/* Protection domain is optional, it does not exist on older platforms */
464
465
ret = of_property_read_string_index(np, "qcom,protection-domain",
465
466
1, &adev->service_path);
466
-
if (ret < 0) {
467
+
if (ret < 0 && ret != -EINVAL) {
467
468
dev_err(dev, "Failed to read second value of qcom,protection-domain\n");
468
469
goto out;
469
470
}
+5
-1
drivers/soc/qcom/cpr.c
+5
-1
drivers/soc/qcom/cpr.c
···
1708
1708
1709
1709
ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
1710
1710
if (ret)
1711
-
return ret;
1711
+
goto err_remove_genpd;
1712
1712
1713
1713
platform_set_drvdata(pdev, drv);
1714
1714
cpr_debugfs_init(drv);
1715
1715
1716
1716
return 0;
1717
+
1718
+
err_remove_genpd:
1719
+
pm_genpd_remove(&drv->pd);
1720
+
return ret;
1717
1721
}
1718
1722
1719
1723
static int cpr_remove(struct platform_device *pdev)
+4
-4
include/linux/firmware/xlnx-zynqmp.h
+4
-4
include/linux/firmware/xlnx-zynqmp.h
···
545
545
const u64 address,
546
546
const enum zynqmp_pm_request_ack ack);
547
547
int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
548
-
int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1);
549
-
int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1);
548
+
int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
549
+
int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
550
550
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
551
551
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
552
552
u32 value);
···
845
845
return -ENODEV;
846
846
}
847
847
848
-
static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1)
848
+
static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
849
849
{
850
850
return -ENODEV;
851
851
}
852
852
853
-
static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1)
853
+
static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
854
854
{
855
855
return -ENODEV;
856
856
}
+2
-2
include/linux/soc/ti/omap1-io.h
+2
-2
include/linux/soc/ti/omap1-io.h
···
5
5
#ifndef __ASSEMBLER__
6
6
#include <linux/types.h>
7
7
8
-
#ifdef CONFIG_ARCH_OMAP1_ANY
8
+
#ifdef CONFIG_ARCH_OMAP1
9
9
/*
10
10
* NOTE: Please use ioremap + __raw_read/write where possible instead of these
11
11
*/
···
15
15
extern void omap_writeb(u8 v, u32 pa);
16
16
extern void omap_writew(u16 v, u32 pa);
17
17
extern void omap_writel(u32 v, u32 pa);
18
-
#else
18
+
#elif defined(CONFIG_COMPILE_TEST)
19
19
static inline u8 omap_readb(u32 pa) { return 0; }
20
20
static inline u16 omap_readw(u32 pa) { return 0; }
21
21
static inline u32 omap_readl(u32 pa) { return 0; }