+1

drivers/gpu/drm/msm/Makefile

reviewed

··· 211 211 generated/mdp4.xml.h \ 212 212 generated/mdp5.xml.h \ 213 213 generated/mdp_common.xml.h \ 214 214 + generated/mdss.xml.h \ 214 215 generated/sfpb.xml.h 215 216 216 217 $(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))

-46

drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h

reviewed

··· 8 8 #include "dpu_kms.h" 9 9 #include "dpu_hw_interrupts.h" 10 10 11 11 - /** 12 12 - * dpu_core_irq_preinstall - perform pre-installation of core IRQ handler 13 13 - * @kms: MSM KMS handle 14 14 - * @return: none 15 15 - */ 16 11 void dpu_core_irq_preinstall(struct msm_kms *kms); 17 12 18 18 - /** 19 19 - * dpu_core_irq_uninstall - uninstall core IRQ handler 20 20 - * @kms: MSM KMS handle 21 21 - * @return: none 22 22 - */ 23 13 void dpu_core_irq_uninstall(struct msm_kms *kms); 24 14 25 25 - /** 26 26 - * dpu_core_irq - core IRQ handler 27 27 - * @kms: MSM KMS handle 28 28 - * @return: interrupt handling status 29 29 - */ 30 15 irqreturn_t dpu_core_irq(struct msm_kms *kms); 31 16 32 32 - /** 33 33 - * dpu_core_irq_read - IRQ helper function for reading IRQ status 34 34 - * @dpu_kms: DPU handle 35 35 - * @irq_idx: irq index 36 36 - * @return: non-zero if irq detected; otherwise no irq detected 37 37 - */ 38 17 u32 dpu_core_irq_read( 39 18 struct dpu_kms *dpu_kms, 40 19 unsigned int irq_idx); 41 20 42 42 - /** 43 43 - * dpu_core_irq_register_callback - For registering callback function on IRQ 44 44 - * interrupt 45 45 - * @dpu_kms: DPU handle 46 46 - * @irq_idx: irq index 47 47 - * @irq_cb: IRQ callback funcion. 48 48 - * @irq_arg: IRQ callback argument. 49 49 - * @return: 0 for success registering callback, otherwise failure 50 50 - * 51 51 - * This function supports registration of multiple callbacks for each interrupt. 52 52 - */ 53 21 int dpu_core_irq_register_callback( 54 22 struct dpu_kms *dpu_kms, 55 23 unsigned int irq_idx, 56 24 void (*irq_cb)(void *arg), 57 25 void *irq_arg); 58 26 59 59 - /** 60 60 - * dpu_core_irq_unregister_callback - For unregistering callback function on IRQ 61 61 - * interrupt 62 62 - * @dpu_kms: DPU handle 63 63 - * @irq_idx: irq index 64 64 - * @return: 0 for success registering callback, otherwise failure 65 65 - * 66 66 - * This function supports registration of multiple callbacks for each interrupt. 67 67 - */ 68 27 int dpu_core_irq_unregister_callback( 69 28 struct dpu_kms *dpu_kms, 70 29 unsigned int irq_idx); 71 30 72 72 - /** 73 73 - * dpu_debugfs_core_irq_init - register core irq debugfs 74 74 - * @dpu_kms: pointer to kms 75 75 - * @parent: debugfs directory root 76 76 - */ 77 31 void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, 78 32 struct dentry *parent); 79 33

+24 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c

reviewed

··· 80 80 81 81 mode = &state->adjusted_mode; 82 82 83 83 - crtc_clk = mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 83 83 + crtc_clk = (u64)mode->vtotal * mode->hdisplay * drm_mode_vrefresh(mode); 84 84 85 85 drm_atomic_crtc_for_each_plane(plane, crtc) { 86 86 pstate = to_dpu_plane_state(plane->state); ··· 140 140 perf->max_per_pipe_ib, perf->bw_ctl); 141 141 } 142 142 143 143 + /** 144 144 + * dpu_core_perf_crtc_check - validate performance of the given crtc state 145 145 + * @crtc: Pointer to crtc 146 146 + * @state: Pointer to new crtc state 147 147 + * return: zero if success, or error code otherwise 148 148 + */ 143 149 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 144 150 struct drm_crtc_state *state) 145 151 { ··· 307 301 return clk_rate; 308 302 } 309 303 304 304 + /** 305 305 + * dpu_core_perf_crtc_update - update performance of the given crtc 306 306 + * @crtc: Pointer to crtc 307 307 + * @params_changed: true if crtc parameters are modified 308 308 + * return: zero if success, or error code otherwise 309 309 + */ 310 310 int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 311 311 int params_changed) 312 312 { ··· 458 446 .write = _dpu_core_perf_mode_write, 459 447 }; 460 448 449 449 + /** 450 450 + * dpu_core_perf_debugfs_init - initialize debugfs for core performance context 451 451 + * @dpu_kms: Pointer to the dpu_kms struct 452 452 + * @parent: Pointer to parent debugfs 453 453 + */ 461 454 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) 462 455 { 463 456 struct dpu_core_perf *perf = &dpu_kms->perf; ··· 499 482 } 500 483 #endif 501 484 485 485 + /** 486 486 + * dpu_core_perf_init - initialize the given core performance context 487 487 + * @perf: Pointer to core performance context 488 488 + * @perf_cfg: Pointer to platform performance configuration 489 489 + * @max_core_clk_rate: Maximum core clock rate 490 490 + */ 502 491 int dpu_core_perf_init(struct dpu_core_perf *perf, 503 492 const struct dpu_perf_cfg *perf_cfg, 504 493 unsigned long max_core_clk_rate)

-27

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h

reviewed

··· 54 54 u64 fix_core_ab_vote; 55 55 }; 56 56 57 57 - /** 58 58 - * dpu_core_perf_crtc_check - validate performance of the given crtc state 59 59 - * @crtc: Pointer to crtc 60 60 - * @state: Pointer to new crtc state 61 61 - * return: zero if success, or error code otherwise 62 62 - */ 63 57 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 64 58 struct drm_crtc_state *state); 65 59 66 66 - /** 67 67 - * dpu_core_perf_crtc_update - update performance of the given crtc 68 68 - * @crtc: Pointer to crtc 69 69 - * @params_changed: true if crtc parameters are modified 70 70 - * return: zero if success, or error code otherwise 71 71 - */ 72 60 int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 73 61 int params_changed); 74 62 75 75 - /** 76 76 - * dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc 77 77 - * @crtc: Pointer to crtc 78 78 - */ 79 63 void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc); 80 64 81 81 - /** 82 82 - * dpu_core_perf_init - initialize the given core performance context 83 83 - * @perf: Pointer to core performance context 84 84 - * @perf_cfg: Pointer to platform performance configuration 85 85 - * @max_core_clk_rate: Maximum core clock rate 86 86 - */ 87 65 int dpu_core_perf_init(struct dpu_core_perf *perf, 88 66 const struct dpu_perf_cfg *perf_cfg, 89 67 unsigned long max_core_clk_rate); 90 68 91 69 struct dpu_kms; 92 70 93 93 - /** 94 94 - * dpu_core_perf_debugfs_init - initialize debugfs for core performance context 95 95 - * @dpu_kms: Pointer to the dpu_kms struct 96 96 - * @debugfs_parent: Pointer to parent debugfs 97 97 - */ 98 71 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent); 99 72 100 73 #endif /* _DPU_CORE_PERF_H_ */

+30 -1

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

reviewed

··· 572 572 spin_unlock_irqrestore(&dev->event_lock, flags); 573 573 } 574 574 575 575 + /** 576 576 + * dpu_crtc_get_intf_mode - get interface mode of the given crtc 577 577 + * @crtc: Pointert to crtc 578 578 + */ 575 579 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 576 580 { 577 581 struct drm_encoder *encoder; ··· 598 594 return INTF_MODE_NONE; 599 595 } 600 596 597 597 + /** 598 598 + * dpu_crtc_vblank_callback - called on vblank irq, issues completion events 599 599 + * @crtc: Pointer to drm crtc object 600 600 + */ 601 601 void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 602 602 { 603 603 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); ··· 712 704 kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); 713 705 } 714 706 707 707 + /** 708 708 + * dpu_crtc_complete_commit - callback signalling completion of current commit 709 709 + * @crtc: Pointer to drm crtc object 710 710 + */ 715 711 void dpu_crtc_complete_commit(struct drm_crtc *crtc) 716 712 { 717 713 trace_dpu_crtc_complete_commit(DRMID(crtc)); ··· 946 934 return rc; 947 935 } 948 936 937 937 + /** 938 938 + * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 939 939 + * @crtc: Pointer to drm crtc object 940 940 + */ 949 941 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) 950 942 { 951 943 struct drm_encoder *encoder; ··· 1259 1243 4096); 1260 1244 } 1261 1245 1246 1246 + /** 1247 1247 + * dpu_crtc_vblank - enable or disable vblanks for this crtc 1248 1248 + * @crtc: Pointer to drm crtc object 1249 1249 + * @en: true to enable vblanks, false to disable 1250 1250 + */ 1262 1251 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 1263 1252 { 1264 1253 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); ··· 1483 1462 .get_scanout_position = dpu_crtc_get_scanout_position, 1484 1463 }; 1485 1464 1486 1486 - /* initialize crtc */ 1465 1465 + /** 1466 1466 + * dpu_crtc_init - create a new crtc object 1467 1467 + * @dev: dpu device 1468 1468 + * @plane: base plane 1469 1469 + * @cursor: cursor plane 1470 1470 + * @return: new crtc object or error 1471 1471 + * 1472 1472 + * initialize CRTC 1473 1473 + */ 1487 1474 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 1488 1475 struct drm_plane *cursor) 1489 1476 {

-38

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

reviewed

··· 239 239 return crtc ? atomic_read(&to_dpu_crtc(crtc)->frame_pending) : -EINVAL; 240 240 } 241 241 242 242 - /** 243 243 - * dpu_crtc_vblank - enable or disable vblanks for this crtc 244 244 - * @crtc: Pointer to drm crtc object 245 245 - * @en: true to enable vblanks, false to disable 246 246 - */ 247 242 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en); 248 243 249 249 - /** 250 250 - * dpu_crtc_vblank_callback - called on vblank irq, issues completion events 251 251 - * @crtc: Pointer to drm crtc object 252 252 - */ 253 244 void dpu_crtc_vblank_callback(struct drm_crtc *crtc); 254 245 255 255 - /** 256 256 - * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 257 257 - * @crtc: Pointer to drm crtc object 258 258 - */ 259 246 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc); 260 247 261 261 - /** 262 262 - * dpu_crtc_complete_commit - callback signalling completion of current commit 263 263 - * @crtc: Pointer to drm crtc object 264 264 - */ 265 248 void dpu_crtc_complete_commit(struct drm_crtc *crtc); 266 249 267 267 - /** 268 268 - * dpu_crtc_init - create a new crtc object 269 269 - * @dev: dpu device 270 270 - * @plane: base plane 271 271 - * @cursor: cursor plane 272 272 - * @Return: new crtc object or error 273 273 - */ 274 250 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 275 251 struct drm_plane *cursor); 276 252 277 277 - /** 278 278 - * dpu_crtc_register_custom_event - api for enabling/disabling crtc event 279 279 - * @kms: Pointer to dpu_kms 280 280 - * @crtc_drm: Pointer to crtc object 281 281 - * @event: Event that client is interested 282 282 - * @en: Flag to enable/disable the event 283 283 - */ 284 284 - int dpu_crtc_register_custom_event(struct dpu_kms *kms, 285 285 - struct drm_crtc *crtc_drm, u32 event, bool en); 286 286 - 287 287 - /** 288 288 - * dpu_crtc_get_intf_mode - get interface mode of the given crtc 289 289 - * @crtc: Pointert to crtc 290 290 - */ 291 253 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc); 292 254 293 255 /**

+179

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

reviewed

··· 217 217 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 218 218 }; 219 219 220 220 + /** 221 221 + * dpu_encoder_get_drm_fmt - return DRM fourcc format 222 222 + * @phys_enc: Pointer to physical encoder structure 223 223 + */ 220 224 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) 221 225 { 222 226 struct drm_encoder *drm_enc; ··· 239 235 return DRM_FORMAT_RGB888; 240 236 } 241 237 238 238 + /** 239 239 + * dpu_encoder_needs_periph_flush - return true if physical encoder requires 240 240 + * peripheral flush 241 241 + * @phys_enc: Pointer to physical encoder structure 242 242 + */ 242 243 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) 243 244 { 244 245 struct drm_encoder *drm_enc; ··· 262 253 msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode); 263 254 } 264 255 256 256 + /** 257 257 + * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 258 258 + * @drm_enc: Pointer to previously created drm encoder structure 259 259 + */ 265 260 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) 266 261 { 267 262 const struct dpu_encoder_virt *dpu_enc; ··· 285 272 return false; 286 273 } 287 274 275 275 + /** 276 276 + * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 277 277 + * for the encoder. 278 278 + * @drm_enc: Pointer to previously created drm encoder structure 279 279 + */ 288 280 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) 289 281 { 290 282 const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 297 279 return dpu_enc->dsc ? true : false; 298 280 } 299 281 282 282 + /** 283 283 + * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 284 284 + * in virtual encoder that can collect CRC values 285 285 + * @drm_enc: Pointer to previously created drm encoder structure 286 286 + * Returns: Number of physical encoders for given drm encoder 287 287 + */ 300 288 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) 301 289 { 302 290 struct dpu_encoder_virt *dpu_enc; ··· 321 297 return num_intf; 322 298 } 323 299 300 300 + /** 301 301 + * dpu_encoder_setup_misr - enable misr calculations 302 302 + * @drm_enc: Pointer to previously created drm encoder structure 303 303 + */ 324 304 void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) 325 305 { 326 306 struct dpu_encoder_virt *dpu_enc; ··· 343 315 } 344 316 } 345 317 318 318 + /** 319 319 + * dpu_encoder_get_crc - get the crc value from interface blocks 320 320 + * @drm_enc: Pointer to previously created drm encoder structure 321 321 + * @crcs: array to fill with CRC data 322 322 + * @pos: offset into the @crcs array 323 323 + * Returns: 0 on success, error otherwise 324 324 + */ 346 325 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) 347 326 { 348 327 struct dpu_encoder_virt *dpu_enc; ··· 420 385 } 421 386 } 422 387 388 388 + /** 389 389 + * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 390 390 + * timed out, including reporting frame error event to crtc and debug dump 391 391 + * @phys_enc: Pointer to physical encoder structure 392 392 + * @intr_idx: Failing interrupt index 393 393 + */ 423 394 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 424 395 enum dpu_intr_idx intr_idx) 425 396 { ··· 443 402 static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, 444 403 u32 irq_idx, struct dpu_encoder_wait_info *info); 445 404 405 405 + /** 406 406 + * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 407 407 + * note: will call dpu_encoder_helper_wait_for_irq on timeout 408 408 + * @phys_enc: Pointer to physical encoder structure 409 409 + * @irq_idx: IRQ index 410 410 + * @func: IRQ callback to be called in case of timeout 411 411 + * @wait_info: wait info struct 412 412 + * @return: 0 or -ERROR 413 413 + */ 446 414 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 447 415 unsigned int irq_idx, 448 416 void (*func)(void *arg), ··· 523 473 return ret; 524 474 } 525 475 476 476 + /** 477 477 + * dpu_encoder_get_vsync_count - get vsync count for the encoder. 478 478 + * @drm_enc: Pointer to previously created drm encoder structure 479 479 + */ 526 480 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc) 527 481 { 528 482 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 534 480 return phys ? atomic_read(&phys->vsync_cnt) : 0; 535 481 } 536 482 483 483 + /** 484 484 + * dpu_encoder_get_linecount - get interface line count for the encoder. 485 485 + * @drm_enc: Pointer to previously created drm encoder structure 486 486 + */ 537 487 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 538 488 { 539 489 struct dpu_encoder_virt *dpu_enc; ··· 553 495 return linecount; 554 496 } 555 497 498 498 + /** 499 499 + * dpu_encoder_helper_split_config - split display configuration helper function 500 500 + * This helper function may be used by physical encoders to configure 501 501 + * the split display related registers. 502 502 + * @phys_enc: Pointer to physical encoder structure 503 503 + * @interface: enum dpu_intf setting 504 504 + */ 556 505 void dpu_encoder_helper_split_config( 557 506 struct dpu_encoder_phys *phys_enc, 558 507 enum dpu_intf interface) ··· 609 544 } 610 545 } 611 546 547 547 + /** 548 548 + * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 549 549 + * @drm_enc: Pointer to previously created drm encoder structure 550 550 + */ 612 551 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) 613 552 { 614 553 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 629 560 return (num_dsc > 0) && (num_dsc > intf_count); 630 561 } 631 562 563 563 + /** 564 564 + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 565 565 + * This helper function is used by physical encoder to get DSC config 566 566 + * used for this encoder. 567 567 + * @drm_enc: Pointer to encoder structure 568 568 + */ 632 569 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) 633 570 { 634 571 struct msm_drm_private *priv = drm_enc->dev->dev_private; ··· 1164 1089 return 0; 1165 1090 } 1166 1091 1092 1092 + /** 1093 1093 + * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 1094 1094 + * @drm_enc: Pointer to previously created drm encoder structure 1095 1095 + * @job: Pointer to the current drm writeback job 1096 1096 + */ 1167 1097 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 1168 1098 struct drm_writeback_job *job) 1169 1099 { ··· 1186 1106 } 1187 1107 } 1188 1108 1109 1109 + /** 1110 1110 + * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 1111 1111 + * @drm_enc: Pointer to previously created drm encoder structure 1112 1112 + * @job: Pointer to the current drm writeback job 1113 1113 + */ 1189 1114 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 1190 1115 struct drm_writeback_job *job) 1191 1116 { ··· 1333 1248 } 1334 1249 } 1335 1250 1251 1251 + /** 1252 1252 + * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 1253 1253 + * @drm_enc: encoder pointer 1254 1254 + */ 1336 1255 void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc) 1337 1256 { 1338 1257 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 1478 1389 return NULL; 1479 1390 } 1480 1391 1392 1392 + /** 1393 1393 + * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 1394 1394 + * @drm_enc: Pointer to drm encoder structure 1395 1395 + * @phy_enc: Pointer to physical encoder 1396 1396 + * Note: This is called from IRQ handler context. 1397 1397 + */ 1481 1398 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 1482 1399 struct dpu_encoder_phys *phy_enc) 1483 1400 { ··· 1506 1411 DPU_ATRACE_END("encoder_vblank_callback"); 1507 1412 } 1508 1413 1414 1414 + /** 1415 1415 + * dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 1416 1416 + * @drm_enc: Pointer to drm encoder structure 1417 1417 + * @phy_enc: Pointer to physical encoder 1418 1418 + * Note: This is called from IRQ handler context. 1419 1419 + */ 1509 1420 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 1510 1421 struct dpu_encoder_phys *phy_enc) 1511 1422 { ··· 1530 1429 DPU_ATRACE_END("encoder_underrun_callback"); 1531 1430 } 1532 1431 1432 1432 + /** 1433 1433 + * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 1434 1434 + * @drm_enc: encoder pointer 1435 1435 + * @crtc: crtc pointer 1436 1436 + */ 1533 1437 void dpu_encoder_assign_crtc(struct drm_encoder *drm_enc, struct drm_crtc *crtc) 1534 1438 { 1535 1439 struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); ··· 1547 1441 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1548 1442 } 1549 1443 1444 1444 + /** 1445 1445 + * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 1446 1446 + * the encoder is assigned to the given crtc 1447 1447 + * @drm_enc: encoder pointer 1448 1448 + * @crtc: crtc pointer 1449 1449 + * @enable: true if vblank should be enabled 1450 1450 + */ 1550 1451 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc, 1551 1452 struct drm_crtc *crtc, bool enable) 1552 1453 { ··· 1578 1465 } 1579 1466 } 1580 1467 1468 1468 + /** 1469 1469 + * dpu_encoder_frame_done_callback - Notify virtual encoder that this phys 1470 1470 + * encoder completes last request frame 1471 1471 + * @drm_enc: Pointer to drm encoder structure 1472 1472 + * @ready_phys: Pointer to physical encoder 1473 1473 + * @event: Event to process 1474 1474 + */ 1581 1475 void dpu_encoder_frame_done_callback( 1582 1476 struct drm_encoder *drm_enc, 1583 1477 struct dpu_encoder_phys *ready_phys, u32 event) ··· 1707 1587 phys->ops.trigger_start(phys); 1708 1588 } 1709 1589 1590 1590 + /** 1591 1591 + * dpu_encoder_helper_trigger_start - control start helper function 1592 1592 + * This helper function may be optionally specified by physical 1593 1593 + * encoders if they require ctl_start triggering. 1594 1594 + * @phys_enc: Pointer to physical encoder structure 1595 1595 + */ 1710 1596 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) 1711 1597 { 1712 1598 struct dpu_hw_ctl *ctl; ··· 1834 1708 spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags); 1835 1709 } 1836 1710 1711 1711 + /** 1712 1712 + * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 1713 1713 + * kickoff and trigger the ctl prepare progress for command mode display. 1714 1714 + * @drm_enc: encoder pointer 1715 1715 + */ 1837 1716 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) 1838 1717 { 1839 1718 struct dpu_encoder_virt *dpu_enc; ··· 1915 1784 return line_time; 1916 1785 } 1917 1786 1787 1787 + /** 1788 1788 + * dpu_encoder_vsync_time - get the time of the next vsync 1789 1789 + * @drm_enc: encoder pointer 1790 1790 + * @wakeup_time: pointer to ktime_t to write the vsync time to 1791 1791 + */ 1918 1792 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) 1919 1793 { 1920 1794 struct drm_display_mode *mode; ··· 2066 1930 dsc, dsc_common_mode, initial_lines); 2067 1931 } 2068 1932 1933 1933 + /** 1934 1934 + * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 1935 1935 + * path (i.e. ctl flush and start) at next appropriate time. 1936 1936 + * Immediately: if no previous commit is outstanding. 1937 1937 + * Delayed: Block until next trigger can be issued. 1938 1938 + * @drm_enc: encoder pointer 1939 1939 + */ 2069 1940 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc) 2070 1941 { 2071 1942 struct dpu_encoder_virt *dpu_enc; ··· 2109 1966 dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc); 2110 1967 } 2111 1968 1969 1969 + /** 1970 1970 + * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 1971 1971 + * @drm_enc: Pointer to drm encoder structure 1972 1972 + */ 2112 1973 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc) 2113 1974 { 2114 1975 struct dpu_encoder_virt *dpu_enc; ··· 2134 1987 return true; 2135 1988 } 2136 1989 1990 1990 + /** 1991 1991 + * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 1992 1992 + * (i.e. ctl flush and start) immediately. 1993 1993 + * @drm_enc: encoder pointer 1994 1994 + */ 2137 1995 void dpu_encoder_kickoff(struct drm_encoder *drm_enc) 2138 1996 { 2139 1997 struct dpu_encoder_virt *dpu_enc; ··· 2237 2085 } 2238 2086 } 2239 2087 2088 2088 + /** 2089 2089 + * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 2090 2090 + * @phys_enc: Pointer to physical encoder structure 2091 2091 + */ 2240 2092 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) 2241 2093 { 2242 2094 struct dpu_hw_ctl *ctl = phys_enc->hw_ctl; ··· 2324 2168 ctl->ops.clear_pending_flush(ctl); 2325 2169 } 2326 2170 2171 2171 + /** 2172 2172 + * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 2173 2173 + * @phys_enc: Pointer to physical encoder 2174 2174 + * @dpu_fmt: Pinter to the format description 2175 2175 + * @output_type: HDMI/WB 2176 2176 + */ 2327 2177 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 2328 2178 const struct msm_format *dpu_fmt, 2329 2179 u32 output_type) ··· 2634 2472 .debugfs_init = dpu_encoder_debugfs_init, 2635 2473 }; 2636 2474 2475 2475 + /** 2476 2476 + * dpu_encoder_init - initialize virtual encoder object 2477 2477 + * @dev: Pointer to drm device structure 2478 2478 + * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 2479 2479 + * @disp_info: Pointer to display information structure 2480 2480 + * Returns: Pointer to newly created drm encoder 2481 2481 + */ 2637 2482 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 2638 2483 int drm_enc_mode, 2639 2484 struct msm_display_info *disp_info) ··· 2762 2593 return ret; 2763 2594 } 2764 2595 2596 2596 + /** 2597 2597 + * dpu_encoder_get_intf_mode - get interface mode of the given encoder 2598 2598 + * @encoder: Pointer to drm encoder object 2599 2599 + */ 2765 2600 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) 2766 2601 { 2767 2602 struct dpu_encoder_virt *dpu_enc = NULL; ··· 2785 2612 return INTF_MODE_NONE; 2786 2613 } 2787 2614 2615 2615 + /** 2616 2616 + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 2617 2617 + * This helper function is used by physical encoder to get DSC blocks mask 2618 2618 + * used for this encoder. 2619 2619 + * @phys_enc: Pointer to physical encoder structure 2620 2620 + */ 2788 2621 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) 2789 2622 { 2790 2623 struct drm_encoder *encoder = phys_enc->parent;

+2 -105

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

reviewed

··· 19 19 20 20 #define IDLE_TIMEOUT (66 - 16/2) 21 21 22 22 + #define MAX_H_TILES_PER_DISPLAY 2 23 23 + 22 24 /** 23 25 * struct msm_display_info - defines display properties 24 26 * @intf_type: INTF_ type ··· 38 36 enum dpu_vsync_source vsync_source; 39 37 }; 40 38 41 41 - /** 42 42 - * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 43 43 - * @encoder: encoder pointer 44 44 - * @crtc: crtc pointer 45 45 - */ 46 39 void dpu_encoder_assign_crtc(struct drm_encoder *encoder, 47 40 struct drm_crtc *crtc); 48 41 49 49 - /** 50 50 - * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 51 51 - * the encoder is assigned to the given crtc 52 52 - * @encoder: encoder pointer 53 53 - * @crtc: crtc pointer 54 54 - * @enable: true if vblank should be enabled 55 55 - */ 56 42 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder, 57 43 struct drm_crtc *crtc, bool enable); 58 44 59 59 - /** 60 60 - * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 61 61 - * path (i.e. ctl flush and start) at next appropriate time. 62 62 - * Immediately: if no previous commit is outstanding. 63 63 - * Delayed: Block until next trigger can be issued. 64 64 - * @encoder: encoder pointer 65 65 - */ 66 45 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder); 67 46 68 68 - /** 69 69 - * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 70 70 - * kickoff and trigger the ctl prepare progress for command mode display. 71 71 - * @encoder: encoder pointer 72 72 - */ 73 47 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder); 74 48 75 75 - /** 76 76 - * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 77 77 - * (i.e. ctl flush and start) immediately. 78 78 - * @encoder: encoder pointer 79 79 - */ 80 49 void dpu_encoder_kickoff(struct drm_encoder *encoder); 81 50 82 82 - /** 83 83 - * dpu_encoder_wakeup_time - get the time of the next vsync 84 84 - */ 85 51 int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time); 86 52 87 53 int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); 88 54 89 55 int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); 90 56 91 91 - /* 92 92 - * dpu_encoder_get_intf_mode - get interface mode of the given encoder 93 93 - * @encoder: Pointer to drm encoder object 94 94 - */ 95 57 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); 96 58 97 97 - /** 98 98 - * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 99 99 - * @encoder: encoder pointer 100 100 - */ 101 59 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder); 102 60 103 103 - /** 104 104 - * dpu_encoder_init - initialize virtual encoder object 105 105 - * @dev: Pointer to drm device structure 106 106 - * @drm_enc_mode: corresponding DRM_MODE_ENCODER_* constant 107 107 - * @disp_info: Pointer to display information structure 108 108 - * Returns: Pointer to newly created drm encoder 109 109 - */ 110 61 struct drm_encoder *dpu_encoder_init(struct drm_device *dev, 111 62 int drm_enc_mode, 112 63 struct msm_display_info *disp_info); 113 64 114 114 - /** 115 115 - * dpu_encoder_set_idle_timeout - set the idle timeout for video 116 116 - * and command mode encoders. 117 117 - * @drm_enc: Pointer to previously created drm encoder structure 118 118 - * @idle_timeout: idle timeout duration in milliseconds 119 119 - */ 120 120 - void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, 121 121 - u32 idle_timeout); 122 122 - /** 123 123 - * dpu_encoder_get_linecount - get interface line count for the encoder. 124 124 - * @drm_enc: Pointer to previously created drm encoder structure 125 125 - */ 126 65 int dpu_encoder_get_linecount(struct drm_encoder *drm_enc); 127 66 128 128 - /** 129 129 - * dpu_encoder_get_vsync_count - get vsync count for the encoder. 130 130 - * @drm_enc: Pointer to previously created drm encoder structure 131 131 - */ 132 67 int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc); 133 68 134 134 - /** 135 135 - * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled 136 136 - * @drm_enc: Pointer to previously created drm encoder structure 137 137 - */ 138 69 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc); 139 70 140 140 - /** 141 141 - * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled 142 142 - * for the encoder. 143 143 - * @drm_enc: Pointer to previously created drm encoder structure 144 144 - */ 145 71 bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc); 146 72 147 147 - /** 148 148 - * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained 149 149 - * in virtual encoder that can collect CRC values 150 150 - * @drm_enc: Pointer to previously created drm encoder structure 151 151 - * Returns: Number of physical encoders for given drm encoder 152 152 - */ 153 73 int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc); 154 74 155 155 - /** 156 156 - * dpu_encoder_setup_misr - enable misr calculations 157 157 - * @drm_enc: Pointer to previously created drm encoder structure 158 158 - */ 159 75 void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder); 160 76 161 161 - /** 162 162 - * dpu_encoder_get_crc - get the crc value from interface blocks 163 163 - * @drm_enc: Pointer to previously created drm encoder structure 164 164 - * Returns: 0 on success, error otherwise 165 165 - */ 166 77 int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos); 167 78 168 168 - /** 169 169 - * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. 170 170 - * @drm_enc: Pointer to previously created drm encoder structure 171 171 - */ 172 79 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc); 173 80 174 174 - /** 175 175 - * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder. 176 176 - * @drm_enc: Pointer to previously created drm encoder structure 177 177 - * @job: Pointer to the current drm writeback job 178 178 - */ 179 81 void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc, 180 82 struct drm_writeback_job *job); 181 83 182 182 - /** 183 183 - * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder. 184 184 - * @drm_enc: Pointer to previously created drm encoder structure 185 185 - * @job: Pointer to the current drm writeback job 186 186 - */ 187 84 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, 188 85 struct drm_writeback_job *job); 189 86 190 190 - /** 191 191 - * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for commit. 192 192 - * @drm_enc: Pointer to drm encoder structure 193 193 - */ 194 87 bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); 195 88 196 89 #endif /* __DPU_ENCODER_H__ */

-90

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

reviewed

··· 279 279 s64 timeout_ms; 280 280 }; 281 281 282 282 - /** 283 283 - * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 284 284 - * @p: Pointer to init params structure 285 285 - * Return: Error code or newly allocated encoder 286 286 - */ 287 282 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, 288 283 struct dpu_enc_phys_init_params *p); 289 284 290 290 - /** 291 291 - * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 292 292 - * @dev: Corresponding device for devres management 293 293 - * @p: Pointer to init params structure 294 294 - * Return: Error code or newly allocated encoder 295 295 - */ 296 285 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, 297 286 struct dpu_enc_phys_init_params *p); 298 287 299 299 - /** 300 300 - * dpu_encoder_phys_wb_init - initialize writeback encoder 301 301 - * @dev: Corresponding device for devres management 302 302 - * @init: Pointer to init info structure with initialization params 303 303 - */ 304 288 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, 305 289 struct dpu_enc_phys_init_params *p); 306 290 307 307 - /** 308 308 - * dpu_encoder_helper_trigger_start - control start helper function 309 309 - * This helper function may be optionally specified by physical 310 310 - * encoders if they require ctl_start triggering. 311 311 - * @phys_enc: Pointer to physical encoder structure 312 312 - */ 313 291 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 314 292 315 293 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( ··· 309 331 return BLEND_3D_NONE; 310 332 } 311 333 312 312 - /** 313 313 - * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 314 314 - * This helper function is used by physical encoder to get DSC blocks mask 315 315 - * used for this encoder. 316 316 - * @phys_enc: Pointer to physical encoder structure 317 317 - */ 318 334 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); 319 335 320 320 - /** 321 321 - * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder 322 322 - * This helper function is used by physical encoder to get DSC config 323 323 - * used for this encoder. 324 324 - * @drm_enc: Pointer to encoder structure 325 325 - */ 326 336 struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); 327 337 328 328 - /** 329 329 - * dpu_encoder_get_drm_fmt - return DRM fourcc format 330 330 - * @phys_enc: Pointer to physical encoder structure 331 331 - */ 332 338 u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc); 333 339 334 334 - /** 335 335 - * dpu_encoder_needs_periph_flush - return true if physical encoder requires 336 336 - * peripheral flush 337 337 - * @phys_enc: Pointer to physical encoder structure 338 338 - */ 339 340 bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc); 340 341 341 341 - /** 342 342 - * dpu_encoder_helper_split_config - split display configuration helper function 343 343 - * This helper function may be used by physical encoders to configure 344 344 - * the split display related registers. 345 345 - * @phys_enc: Pointer to physical encoder structure 346 346 - * @interface: enum dpu_intf setting 347 347 - */ 348 342 void dpu_encoder_helper_split_config( 349 343 struct dpu_encoder_phys *phys_enc, 350 344 enum dpu_intf interface); 351 345 352 352 - /** 353 353 - * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 354 354 - * timed out, including reporting frame error event to crtc and debug dump 355 355 - * @phys_enc: Pointer to physical encoder structure 356 356 - * @intr_idx: Failing interrupt index 357 357 - */ 358 346 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 359 347 enum dpu_intr_idx intr_idx); 360 348 361 361 - /** 362 362 - * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 363 363 - * note: will call dpu_encoder_helper_wait_for_irq on timeout 364 364 - * @phys_enc: Pointer to physical encoder structure 365 365 - * @irq: IRQ index 366 366 - * @func: IRQ callback to be called in case of timeout 367 367 - * @wait_info: wait info struct 368 368 - * @Return: 0 or -ERROR 369 369 - */ 370 349 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 371 350 unsigned int irq, 372 351 void (*func)(void *arg), 373 352 struct dpu_encoder_wait_info *wait_info); 374 353 375 375 - /** 376 376 - * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 377 377 - * @phys_enc: Pointer to physical encoder structure 378 378 - */ 379 354 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 380 355 381 381 - /** 382 382 - * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block 383 383 - * @phys_enc: Pointer to physical encoder 384 384 - * @output_type: HDMI/WB 385 385 - */ 386 356 void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, 387 357 const struct msm_format *dpu_fmt, 388 358 u32 output_type); 389 359 390 390 - /** 391 391 - * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 392 392 - * @drm_enc: Pointer to drm encoder structure 393 393 - * @phys_enc: Pointer to physical encoder 394 394 - * Note: This is called from IRQ handler context. 395 395 - */ 396 360 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 397 361 struct dpu_encoder_phys *phy_enc); 398 362 399 399 - /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 400 400 - * @drm_enc: Pointer to drm encoder structure 401 401 - * @phys_enc: Pointer to physical encoder 402 402 - * Note: This is called from IRQ handler context. 403 403 - */ 404 363 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 405 364 struct dpu_encoder_phys *phy_enc); 406 365 407 407 - /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame 408 408 - * @drm_enc: Pointer to drm encoder structure 409 409 - * @phys_enc: Pointer to physical encoder 410 410 - * @event: Event to process 411 411 - */ 412 366 void dpu_encoder_frame_done_callback( 413 367 struct drm_encoder *drm_enc, 414 368 struct dpu_encoder_phys *ready_phys, u32 event);

+6

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

reviewed

··· 720 720 ops->get_line_count = dpu_encoder_phys_cmd_get_line_count; 721 721 } 722 722 723 723 + /** 724 724 + * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 725 725 + * @dev: Corresponding device for devres management 726 726 + * @p: Pointer to init params structure 727 727 + * Return: Error code or newly allocated encoder 728 728 + */ 723 729 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, 724 730 struct dpu_enc_phys_init_params *p) 725 731 {

+6

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

reviewed

··· 746 746 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; 747 747 } 748 748 749 749 + /** 750 750 + * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 751 751 + * @dev: Corresponding device for devres management 752 752 + * @p: Pointer to init params structure 753 753 + * Return: Error code or newly allocated encoder 754 754 + */ 749 755 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, 750 756 struct dpu_enc_phys_init_params *p) 751 757 {

+9 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c

reviewed

··· 241 241 return 0; 242 242 } 243 243 244 244 - /* 245 245 - * dpu_format_populate_addrs - populate non-address part of the layout based on 244 244 + /** 245 245 + * dpu_format_populate_plane_sizes - populate non-address part of the layout based on 246 246 * fb, and format found in the fb 247 247 * @fb: framebuffer pointer 248 248 * @layout: format layout structure to populate ··· 366 366 layout->plane_addr[i] = msm_framebuffer_iova(fb, aspace, i); 367 367 } 368 368 369 369 + /** 370 370 + * dpu_format_populate_addrs - populate buffer addresses based on 371 371 + * mmu, fb, and format found in the fb 372 372 + * @aspace: address space pointer 373 373 + * @fb: framebuffer pointer 374 374 + * @layout: format layout structure to populate 375 375 + */ 369 376 void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, 370 377 struct drm_framebuffer *fb, 371 378 struct dpu_hw_fmt_layout *layout)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h

reviewed

··· 31 31 return false; 32 32 } 33 33 34 34 - /** 35 35 - * dpu_format_populate_addrs - populate buffer addresses based on 36 36 - * mmu, fb, and format found in the fb 37 37 - * @aspace: address space pointer 38 38 - * @fb: framebuffer pointer 39 39 - * @fmtl: format layout structure to populate 40 40 - */ 41 34 void dpu_format_populate_addrs(struct msm_gem_address_space *aspace, 42 35 struct drm_framebuffer *fb, 43 36 struct dpu_hw_fmt_layout *layout);

-28

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

reviewed

··· 147 147 #define MAX_HORZ_DECIMATION 4 148 148 #define MAX_VERT_DECIMATION 4 149 149 150 150 - #define MAX_UPSCALE_RATIO 20 151 151 - #define MAX_DOWNSCALE_RATIO 4 152 152 - #define SSPP_UNITY_SCALE 1 153 153 - 154 150 #define STRCAT(X, Y) (X Y) 155 151 156 152 static const uint32_t plane_formats[] = { ··· 304 308 /* SSPP common configuration */ 305 309 #define _VIG_SBLK(scaler_ver) \ 306 310 { \ 307 307 - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 308 308 - .maxupscale = MAX_UPSCALE_RATIO, \ 309 311 .scaler_blk = {.name = "scaler", \ 310 312 .version = scaler_ver, \ 311 313 .base = 0xa00, .len = 0xa0,}, \ ··· 311 317 .base = 0x1a00, .len = 0x100,}, \ 312 318 .format_list = plane_formats_yuv, \ 313 319 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 314 314 - .virt_format_list = plane_formats, \ 315 315 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 316 320 .rotation_cfg = NULL, \ 317 321 } 318 322 319 323 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 320 324 { \ 321 321 - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 322 322 - .maxupscale = MAX_UPSCALE_RATIO, \ 323 325 .scaler_blk = {.name = "scaler", \ 324 326 .version = scaler_ver, \ 325 327 .base = 0xa00, .len = 0xa0,}, \ ··· 323 333 .base = 0x1a00, .len = 0x100,}, \ 324 334 .format_list = plane_formats_yuv, \ 325 335 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 326 326 - .virt_format_list = plane_formats, \ 327 327 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 328 336 .rotation_cfg = rot_cfg, \ 329 337 } 330 338 331 339 #define _VIG_SBLK_NOSCALE() \ 332 340 { \ 333 333 - .maxdwnscale = SSPP_UNITY_SCALE, \ 334 334 - .maxupscale = SSPP_UNITY_SCALE, \ 335 341 .format_list = plane_formats, \ 336 342 .num_formats = ARRAY_SIZE(plane_formats), \ 337 337 - .virt_format_list = plane_formats, \ 338 338 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 339 343 } 340 344 341 345 /* qseed2 is not supported, so disabled scaling */ 342 346 #define _VIG_SBLK_QSEED2() \ 343 347 { \ 344 344 - .maxdwnscale = SSPP_UNITY_SCALE, \ 345 345 - .maxupscale = SSPP_UNITY_SCALE, \ 346 348 .scaler_blk = {.name = "scaler", \ 347 349 /* no version for qseed2 */ \ 348 350 .base = 0x200, .len = 0xa0,}, \ ··· 342 360 .base = 0x320, .len = 0x100,}, \ 343 361 .format_list = plane_formats_yuv, \ 344 362 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 345 345 - .virt_format_list = plane_formats, \ 346 346 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 347 363 .rotation_cfg = NULL, \ 348 364 } 349 365 350 366 #define _RGB_SBLK() \ 351 367 { \ 352 352 - .maxdwnscale = SSPP_UNITY_SCALE, \ 353 353 - .maxupscale = SSPP_UNITY_SCALE, \ 354 368 .scaler_blk = {.name = "scaler", \ 355 369 .base = 0x200, .len = 0x28,}, \ 356 370 .format_list = plane_formats, \ 357 371 .num_formats = ARRAY_SIZE(plane_formats), \ 358 358 - .virt_format_list = plane_formats, \ 359 359 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 360 372 } 361 373 362 374 #define _DMA_SBLK() \ 363 375 { \ 364 364 - .maxdwnscale = SSPP_UNITY_SCALE, \ 365 365 - .maxupscale = SSPP_UNITY_SCALE, \ 366 376 .format_list = plane_formats, \ 367 377 .num_formats = ARRAY_SIZE(plane_formats), \ 368 368 - .virt_format_list = plane_formats, \ 369 369 - .virt_num_formats = ARRAY_SIZE(plane_formats), \ 370 378 } 371 379 372 380 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

reviewed

··· 364 364 /** 365 365 * struct dpu_sspp_sub_blks : SSPP sub-blocks 366 366 * common: Pointer to common configurations shared by sub blocks 367 367 - * @maxdwnscale: max downscale ratio supported(without DECIMATION) 368 368 - * @maxupscale: maxupscale ratio supported 369 367 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 370 368 * @qseed_ver: qseed version 371 369 * @scaler_blk: 372 370 * @csc_blk: 373 371 * @format_list: Pointer to list of supported formats 374 372 * @num_formats: Number of supported formats 375 375 - * @virt_format_list: Pointer to list of supported formats for virtual planes 376 376 - * @virt_num_formats: Number of supported formats for virtual planes 377 373 * @dpu_rotation_cfg: inline rotation configuration 378 374 */ 379 375 struct dpu_sspp_sub_blks { 380 380 - u32 maxdwnscale; 381 381 - u32 maxupscale; 382 376 u32 max_per_pipe_bw; 383 377 u32 qseed_ver; 384 378 struct dpu_scaler_blk scaler_blk; ··· 380 386 381 387 const u32 *format_list; 382 388 u32 num_formats; 383 383 - const u32 *virt_format_list; 384 384 - u32 virt_num_formats; 385 389 const struct dpu_rotation_cfg *rotation_cfg; 386 390 }; 387 391

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c

reviewed

··· 222 222 DPU_REG_WRITE(c, CDM_MUX, mux_cfg); 223 223 } 224 224 225 225 + /** 226 226 + * dpu_hw_cdm_init - initializes the cdm hw driver object. 227 227 + * should be called once before accessing every cdm. 228 228 + * @dev: DRM device handle 229 229 + * @cfg: CDM catalog entry for which driver object is required 230 230 + * @addr : mapped register io address of MDSS 231 231 + * @mdss_rev: mdss hw core revision 232 232 + */ 225 233 struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev, 226 234 const struct dpu_cdm_cfg *cfg, void __iomem *addr, 227 235 const struct dpu_mdss_version *mdss_rev)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

reviewed

··· 122 122 struct dpu_hw_cdm_ops ops; 123 123 }; 124 124 125 125 - /** 126 126 - * dpu_hw_cdm_init - initializes the cdm hw driver object. 127 127 - * should be called once before accessing every cdm. 128 128 - * @dev: DRM device handle 129 129 - * @cdm: CDM catalog entry for which driver object is required 130 130 - * @addr : mapped register io address of MDSS 131 131 - * @mdss_rev: mdss hw core revision 132 132 - */ 133 125 struct dpu_hw_cdm *dpu_hw_cdm_init(struct drm_device *dev, 134 126 const struct dpu_cdm_cfg *cdm, void __iomem *addr, 135 127 const struct dpu_mdss_version *mdss_rev);

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c

reviewed

··· 736 736 ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; 737 737 }; 738 738 739 739 + /** 740 740 + * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. 741 741 + * Should be called before accessing any ctl_path register. 742 742 + * @dev: Corresponding device for devres management 743 743 + * @cfg: ctl_path catalog entry for which driver object is required 744 744 + * @addr: mapped register io address of MDP 745 745 + * @mixer_count: Number of mixers in @mixer 746 746 + * @mixer: Pointer to an array of Layer Mixers defined in the catalog 747 747 + */ 739 748 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 740 749 const struct dpu_ctl_cfg *cfg, 741 750 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

reviewed

··· 294 294 return container_of(hw, struct dpu_hw_ctl, base); 295 295 } 296 296 297 297 - /** 298 298 - * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. 299 299 - * Should be called before accessing any ctl_path register. 300 300 - * @dev: Corresponding device for devres management 301 301 - * @cfg: ctl_path catalog entry for which driver object is required 302 302 - * @addr: mapped register io address of MDP 303 303 - * @mixer_count: Number of mixers in @mixer 304 304 - * @mixer: Pointer to an array of Layer Mixers defined in the catalog 305 305 - */ 306 297 struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, 307 298 const struct dpu_ctl_cfg *cfg, 308 299 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

reviewed

··· 190 190 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 191 191 }; 192 192 193 193 + /** 194 194 + * dpu_hw_dsc_init() - Initializes the DSC hw driver object. 195 195 + * @dev: Corresponding device for devres management 196 196 + * @cfg: DSC catalog entry for which driver object is required 197 197 + * @addr: Mapped register io address of MDP 198 198 + * Return: Error code or allocated dpu_hw_dsc context 199 199 + */ 193 200 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 194 201 const struct dpu_dsc_cfg *cfg, 195 202 void __iomem *addr)

-14

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

reviewed

··· 62 62 struct dpu_hw_dsc_ops ops; 63 63 }; 64 64 65 65 - /** 66 66 - * dpu_hw_dsc_init() - Initializes the DSC hw driver object. 67 67 - * @dev: Corresponding device for devres management 68 68 - * @cfg: DSC catalog entry for which driver object is required 69 69 - * @addr: Mapped register io address of MDP 70 70 - * Return: Error code or allocated dpu_hw_dsc context 71 71 - */ 72 65 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 73 66 const struct dpu_dsc_cfg *cfg, 74 67 void __iomem *addr); 75 68 76 76 - /** 77 77 - * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object 78 78 - * @dev: Corresponding device for devres management 79 79 - * @cfg: DSC catalog entry for which driver object is required 80 80 - * @addr: Mapped register io address of MDP 81 81 - * Returns: Error code or allocated dpu_hw_dsc context 82 82 - */ 83 69 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, 84 70 const struct dpu_dsc_cfg *cfg, 85 71 void __iomem *addr);

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

reviewed

··· 369 369 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk_1_2; 370 370 } 371 371 372 372 + /** 373 373 + * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object 374 374 + * @dev: Corresponding device for devres management 375 375 + * @cfg: DSC catalog entry for which driver object is required 376 376 + * @addr: Mapped register io address of MDP 377 377 + * Returns: Error code or allocated dpu_hw_dsc context 378 378 + */ 372 379 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, 373 380 const struct dpu_dsc_cfg *cfg, 374 381 void __iomem *addr)

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c

reviewed

··· 70 70 c->ops.setup_pcc = dpu_setup_dspp_pcc; 71 71 } 72 72 73 73 + /** 74 74 + * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. 75 75 + * should be called once before accessing every DSPP. 76 76 + * @dev: Corresponding device for devres management 77 77 + * @cfg: DSPP catalog entry for which driver object is required 78 78 + * @addr: Mapped register io address of MDP 79 79 + * Return: pointer to structure or ERR_PTR 80 80 + */ 73 81 struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev, 74 82 const struct dpu_dspp_cfg *cfg, 75 83 void __iomem *addr)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h

reviewed

··· 78 78 return container_of(hw, struct dpu_hw_dspp, base); 79 79 } 80 80 81 81 - /** 82 82 - * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. 83 83 - * should be called once before accessing every DSPP. 84 84 - * @dev: Corresponding device for devres management 85 85 - * @cfg: DSPP catalog entry for which driver object is required 86 86 - * @addr: Mapped register io address of MDP 87 87 - * Return: pointer to structure or ERR_PTR 88 88 - */ 89 81 struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev, 90 82 const struct dpu_dspp_cfg *cfg, 91 83 void __iomem *addr);

+52

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

reviewed

··· 237 237 irq_entry->cb(irq_entry->arg); 238 238 } 239 239 240 240 + /** 241 241 + * dpu_core_irq - core IRQ handler 242 242 + * @kms: MSM KMS handle 243 243 + * @return: interrupt handling status 244 244 + */ 240 245 irqreturn_t dpu_core_irq(struct msm_kms *kms) 241 246 { 242 247 struct dpu_kms *dpu_kms = to_dpu_kms(kms); ··· 447 442 wmb(); 448 443 } 449 444 445 445 + /** 446 446 + * dpu_core_irq_read - IRQ helper function for reading IRQ status 447 447 + * @dpu_kms: DPU handle 448 448 + * @irq_idx: irq index 449 449 + * @return: non-zero if irq detected; otherwise no irq detected 450 450 + */ 450 451 u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, 451 452 unsigned int irq_idx) 452 453 { ··· 487 476 return intr_status; 488 477 } 489 478 479 479 + /** 480 480 + * dpu_hw_intr_init(): Initializes the interrupts hw object 481 481 + * @dev: Corresponding device for devres management 482 482 + * @addr: mapped register io address of MDP 483 483 + * @m: pointer to MDSS catalog data 484 484 + */ 490 485 struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev, 491 486 void __iomem *addr, 492 487 const struct dpu_mdss_cfg *m) ··· 534 517 return intr; 535 518 } 536 519 520 520 + /** 521 521 + * dpu_core_irq_register_callback - For registering callback function on IRQ 522 522 + * interrupt 523 523 + * @dpu_kms: DPU handle 524 524 + * @irq_idx: irq index 525 525 + * @irq_cb: IRQ callback function. 526 526 + * @irq_arg: IRQ callback argument. 527 527 + * @return: 0 for success registering callback, otherwise failure 528 528 + * 529 529 + * This function supports registration of multiple callbacks for each interrupt. 530 530 + */ 537 531 int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, 538 532 unsigned int irq_idx, 539 533 void (*irq_cb)(void *arg), ··· 595 567 return 0; 596 568 } 597 569 570 570 + /** 571 571 + * dpu_core_irq_unregister_callback - For unregistering callback function on IRQ 572 572 + * interrupt 573 573 + * @dpu_kms: DPU handle 574 574 + * @irq_idx: irq index 575 575 + * @return: 0 for success registering callback, otherwise failure 576 576 + * 577 577 + * This function supports registration of multiple callbacks for each interrupt. 578 578 + */ 598 579 int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, 599 580 unsigned int irq_idx) 600 581 { ··· 665 628 666 629 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); 667 630 631 631 + /** 632 632 + * dpu_debugfs_core_irq_init - register core irq debugfs 633 633 + * @dpu_kms: pointer to kms 634 634 + * @parent: debugfs directory root 635 635 + */ 668 636 void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, 669 637 struct dentry *parent) 670 638 { ··· 678 636 } 679 637 #endif 680 638 639 639 + /** 640 640 + * dpu_core_irq_preinstall - perform pre-installation of core IRQ handler 641 641 + * @kms: MSM KMS handle 642 642 + * @return: none 643 643 + */ 681 644 void dpu_core_irq_preinstall(struct msm_kms *kms) 682 645 { 683 646 struct dpu_kms *dpu_kms = to_dpu_kms(kms); ··· 700 653 } 701 654 } 702 655 656 656 + /** 657 657 + * dpu_core_irq_uninstall - uninstall core IRQ handler 658 658 + * @kms: MSM KMS handle 659 659 + * @return: none 660 660 + */ 703 661 void dpu_core_irq_uninstall(struct msm_kms *kms) 704 662 { 705 663 struct dpu_kms *dpu_kms = to_dpu_kms(kms);

-6

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h

reviewed

··· 68 68 struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS]; 69 69 }; 70 70 71 71 - /** 72 72 - * dpu_hw_intr_init(): Initializes the interrupts hw object 73 73 - * @dev: Corresponding device for devres management 74 74 - * @addr: mapped register io address of MDP 75 75 - * @m: pointer to MDSS catalog data 76 76 - */ 77 71 struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev, 78 72 void __iomem *addr, 79 73 const struct dpu_mdss_cfg *m);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

reviewed

··· 547 547 DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); 548 548 } 549 549 550 550 + /** 551 551 + * dpu_hw_intf_init() - Initializes the INTF driver for the passed 552 552 + * interface catalog entry. 553 553 + * @dev: Corresponding device for devres management 554 554 + * @cfg: interface catalog entry for which driver object is required 555 555 + * @addr: mapped register io address of MDP 556 556 + * @mdss_rev: dpu core's major and minor versions 557 557 + */ 550 558 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 551 559 const struct dpu_intf_cfg *cfg, 552 560 void __iomem *addr,

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

reviewed

··· 130 130 struct dpu_hw_intf_ops ops; 131 131 }; 132 132 133 133 - /** 134 134 - * dpu_hw_intf_init() - Initializes the INTF driver for the passed 135 135 - * interface catalog entry. 136 136 - * @dev: Corresponding device for devres management 137 137 - * @cfg: interface catalog entry for which driver object is required 138 138 - * @addr: mapped register io address of MDP 139 139 - * @mdss_rev: dpu core's major and minor versions 140 140 - */ 141 133 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 142 134 const struct dpu_intf_cfg *cfg, 143 135 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

reviewed

··· 158 158 ops->collect_misr = dpu_hw_lm_collect_misr; 159 159 } 160 160 161 161 + /** 162 162 + * dpu_hw_lm_init() - Initializes the mixer hw driver object. 163 163 + * should be called once before accessing every mixer. 164 164 + * @dev: Corresponding device for devres management 165 165 + * @cfg: mixer catalog entry for which driver object is required 166 166 + * @addr: mapped register io address of MDP 167 167 + */ 161 168 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 162 169 const struct dpu_lm_cfg *cfg, 163 170 void __iomem *addr)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

reviewed

··· 93 93 return container_of(hw, struct dpu_hw_mixer, base); 94 94 } 95 95 96 96 - /** 97 97 - * dpu_hw_lm_init() - Initializes the mixer hw driver object. 98 98 - * should be called once before accessing every mixer. 99 99 - * @dev: Corresponding device for devres management 100 100 - * @cfg: mixer catalog entry for which driver object is required 101 101 - * @addr: mapped register io address of MDP 102 102 - */ 103 96 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, 104 97 const struct dpu_lm_cfg *cfg, 105 98 void __iomem *addr);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c

reviewed

··· 39 39 c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; 40 40 }; 41 41 42 42 + /** 43 43 + * dpu_hw_merge_3d_init() - Initializes the merge_3d driver for the passed 44 44 + * merge3d catalog entry. 45 45 + * @dev: Corresponding device for devres management 46 46 + * @cfg: Pingpong catalog entry for which driver object is required 47 47 + * @addr: Mapped register io address of MDP 48 48 + * Return: Error code or allocated dpu_hw_merge_3d context 49 49 + */ 42 50 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev, 43 51 const struct dpu_merge_3d_cfg *cfg, 44 52 void __iomem *addr)

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h

reviewed

··· 45 45 return container_of(hw, struct dpu_hw_merge_3d, base); 46 46 } 47 47 48 48 - /** 49 49 - * dpu_hw_merge_3d_init() - Initializes the merge_3d driver for the passed 50 50 - * merge3d catalog entry. 51 51 - * @dev: Corresponding device for devres management 52 52 - * @cfg: Pingpong catalog entry for which driver object is required 53 53 - * @addr: Mapped register io address of MDP 54 54 - * Return: Error code or allocated dpu_hw_merge_3d context 55 55 - */ 56 48 struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev, 57 49 const struct dpu_merge_3d_cfg *cfg, 58 50 void __iomem *addr);

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c

reviewed

··· 283 283 return 0; 284 284 } 285 285 286 286 + /** 287 287 + * dpu_hw_pingpong_init() - initializes the pingpong driver for the passed 288 288 + * pingpong catalog entry. 289 289 + * @dev: Corresponding device for devres management 290 290 + * @cfg: Pingpong catalog entry for which driver object is required 291 291 + * @addr: Mapped register io address of MDP 292 292 + * @mdss_rev: dpu core's major and minor versions 293 293 + * Return: Error code or allocated dpu_hw_pingpong context 294 294 + */ 286 295 struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, 287 296 const struct dpu_pingpong_cfg *cfg, 288 297 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h

reviewed

··· 118 118 return container_of(hw, struct dpu_hw_pingpong, base); 119 119 } 120 120 121 121 - /** 122 122 - * dpu_hw_pingpong_init() - initializes the pingpong driver for the passed 123 123 - * pingpong catalog entry. 124 124 - * @dev: Corresponding device for devres management 125 125 - * @cfg: Pingpong catalog entry for which driver object is required 126 126 - * @addr: Mapped register io address of MDP 127 127 - * @mdss_rev: dpu core's major and minor versions 128 128 - * Return: Error code or allocated dpu_hw_pingpong context 129 129 - */ 130 121 struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev, 131 122 const struct dpu_pingpong_cfg *cfg, 132 123 void __iomem *addr,

+9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

reviewed

··· 672 672 } 673 673 #endif 674 674 675 675 + /** 676 676 + * dpu_hw_sspp_init() - Initializes the sspp hw driver object. 677 677 + * Should be called once before accessing every pipe. 678 678 + * @dev: Corresponding device for devres management 679 679 + * @cfg: Pipe catalog entry for which driver object is required 680 680 + * @addr: Mapped register io address of MDP 681 681 + * @mdss_data: UBWC / MDSS configuration data 682 682 + * @mdss_rev: dpu core's major and minor versions 683 683 + */ 675 684 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, 676 685 const struct dpu_sspp_cfg *cfg, 677 686 void __iomem *addr,

+3 -9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

reviewed

··· 144 144 * @src_rect: src ROI, caller takes into account the different operations 145 145 * such as decimation, flip etc to program this field 146 146 * @dest_rect: destination ROI. 147 147 + * @rotation: simplified drm rotation hint 147 148 */ 148 149 struct dpu_sw_pipe_cfg { 149 150 struct drm_rect src_rect; 150 151 struct drm_rect dst_rect; 152 152 + unsigned int rotation; 151 153 }; 152 154 153 155 /** ··· 319 317 }; 320 318 321 319 struct dpu_kms; 322 322 - /** 323 323 - * dpu_hw_sspp_init() - Initializes the sspp hw driver object. 324 324 - * Should be called once before accessing every pipe. 325 325 - * @dev: Corresponding device for devres management 326 326 - * @cfg: Pipe catalog entry for which driver object is required 327 327 - * @addr: Mapped register io address of MDP 328 328 - * @mdss_data: UBWC / MDSS configuration data 329 329 - * @mdss_rev: dpu core's major and minor versions 330 330 - */ 320 320 + 331 321 struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev, 332 322 const struct dpu_sspp_cfg *cfg, 333 323 void __iomem *addr,

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

reviewed

··· 284 284 ops->intf_audio_select = dpu_hw_intf_audio_select; 285 285 } 286 286 287 287 + /** 288 288 + * dpu_hw_mdptop_init - initializes the top driver for the passed config 289 289 + * @dev: Corresponding device for devres management 290 290 + * @cfg: MDP TOP configuration from catalog 291 291 + * @addr: Mapped register io address of MDP 292 292 + * @mdss_rev: dpu core's major and minor versions 293 293 + */ 287 294 struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev, 288 295 const struct dpu_mdp_cfg *cfg, 289 296 void __iomem *addr,

-9

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

reviewed

··· 157 157 struct dpu_hw_mdp_ops ops; 158 158 }; 159 159 160 160 - /** 161 161 - * dpu_hw_mdptop_init - initializes the top driver for the passed config 162 162 - * @dev: Corresponding device for devres management 163 163 - * @cfg: MDP TOP configuration from catalog 164 164 - * @addr: Mapped register io address of MDP 165 165 - * @mdss_rev: dpu core's major and minor versions 166 166 - */ 167 160 struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev, 168 161 const struct dpu_mdp_cfg *cfg, 169 162 void __iomem *addr, 170 163 const struct dpu_mdss_version *mdss_rev); 171 171 - 172 172 - void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp); 173 164 174 165 #endif /*_DPU_HW_TOP_H */

+7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c

reviewed

··· 213 213 ops->set_write_gather_en = dpu_hw_set_write_gather_en; 214 214 } 215 215 216 216 + /** 217 217 + * dpu_hw_vbif_init() - Initializes the VBIF driver for the passed 218 218 + * VBIF catalog entry. 219 219 + * @dev: Corresponding device for devres management 220 220 + * @cfg: VBIF catalog entry for which driver object is required 221 221 + * @addr: Mapped register io address of MDSS 222 222 + */ 216 223 struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev, 217 224 const struct dpu_vbif_cfg *cfg, 218 225 void __iomem *addr)

-7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h

reviewed

··· 105 105 struct dpu_hw_vbif_ops ops; 106 106 }; 107 107 108 108 - /** 109 109 - * dpu_hw_vbif_init() - Initializes the VBIF driver for the passed 110 110 - * VBIF catalog entry. 111 111 - * @dev: Corresponding device for devres management 112 112 - * @cfg: VBIF catalog entry for which driver object is required 113 113 - * @addr: Mapped register io address of MDSS 114 114 - */ 115 108 struct dpu_hw_vbif *dpu_hw_vbif_init(struct drm_device *dev, 116 109 const struct dpu_vbif_cfg *cfg, 117 110 void __iomem *addr);

+8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

reviewed

··· 213 213 ops->setup_clk_force_ctrl = dpu_hw_wb_setup_clk_force_ctrl; 214 214 } 215 215 216 216 + /** 217 217 + * dpu_hw_wb_init() - Initializes the writeback hw driver object. 218 218 + * @dev: Corresponding device for devres management 219 219 + * @cfg: wb_path catalog entry for which driver object is required 220 220 + * @addr: mapped register io address of MDP 221 221 + * @mdss_rev: dpu core's major and minor versions 222 222 + * Return: Error code or allocated dpu_hw_wb context 223 223 + */ 216 224 struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, 217 225 const struct dpu_wb_cfg *cfg, 218 226 void __iomem *addr,

-8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h

reviewed

··· 75 75 struct dpu_hw_wb_ops ops; 76 76 }; 77 77 78 78 - /** 79 79 - * dpu_hw_wb_init() - Initializes the writeback hw driver object. 80 80 - * @dev: Corresponding device for devres management 81 81 - * @cfg: wb_path catalog entry for which driver object is required 82 82 - * @addr: mapped register io address of MDP 83 83 - * @mdss_rev: dpu core's major and minor versions 84 84 - * Return: Error code or allocated dpu_hw_wb context 85 85 - */ 86 78 struct dpu_hw_wb *dpu_hw_wb_init(struct drm_device *dev, 87 79 const struct dpu_wb_cfg *cfg, 88 80 void __iomem *addr,

+22

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

reviewed

··· 230 230 } 231 231 DEFINE_SHOW_ATTRIBUTE(dpu_regset32); 232 232 233 233 + /** 234 234 + * dpu_debugfs_create_regset32 - Create register read back file for debugfs 235 235 + * 236 236 + * This function is almost identical to the standard debugfs_create_regset32() 237 237 + * function, with the main difference being that a list of register 238 238 + * names/offsets do not need to be provided. The 'read' function simply outputs 239 239 + * sequential register values over a specified range. 240 240 + * 241 241 + * @name: File name within debugfs 242 242 + * @mode: File mode within debugfs 243 243 + * @parent: Parent directory entry within debugfs, can be NULL 244 244 + * @offset: sub-block offset 245 245 + * @length: sub-block length, in bytes 246 246 + * @dpu_kms: pointer to dpu kms structure 247 247 + */ 233 248 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 234 249 void *parent, 235 250 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms) ··· 1075 1060 return 0; 1076 1061 } 1077 1062 1063 1063 + /** 1064 1064 + * dpu_kms_get_clk_rate() - get the clock rate 1065 1065 + * @dpu_kms: pointer to dpu_kms structure 1066 1066 + * @clock_name: clock name to get the rate 1067 1067 + * 1068 1068 + * Return: current clock rate 1069 1069 + */ 1078 1070 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) 1079 1071 { 1080 1072 struct clk *clk;

-34

drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

reviewed

··· 145 145 * @dpu_debugfs_create_regset32: Create 32-bit register dump file 146 146 */ 147 147 148 148 - /** 149 149 - * dpu_debugfs_create_regset32 - Create register read back file for debugfs 150 150 - * 151 151 - * This function is almost identical to the standard debugfs_create_regset32() 152 152 - * function, with the main difference being that a list of register 153 153 - * names/offsets do not need to be provided. The 'read' function simply outputs 154 154 - * sequential register values over a specified range. 155 155 - * 156 156 - * @name: File name within debugfs 157 157 - * @mode: File mode within debugfs 158 158 - * @parent: Parent directory entry within debugfs, can be NULL 159 159 - * @offset: sub-block offset 160 160 - * @length: sub-block length, in bytes 161 161 - * @dpu_kms: pointer to dpu kms structure 162 162 - */ 163 148 void dpu_debugfs_create_regset32(const char *name, umode_t mode, 164 149 void *parent, 165 150 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms); 166 166 - 167 167 - /** 168 168 - * dpu_debugfs_get_root - Return root directory entry for KMS's debugfs 169 169 - * 170 170 - * The return value should be passed as the 'parent' argument to subsequent 171 171 - * debugfs create calls. 172 172 - * 173 173 - * @dpu_kms: Pointer to DPU's KMS structure 174 174 - * 175 175 - * Return: dentry pointer for DPU's debugfs location 176 176 - */ 177 177 - void *dpu_debugfs_get_root(struct dpu_kms *dpu_kms); 178 151 179 152 /** 180 153 * DPU info management functions ··· 162 189 int dpu_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 163 190 void dpu_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc); 164 191 165 165 - /** 166 166 - * dpu_kms_get_clk_rate() - get the clock rate 167 167 - * @dpu_kms: pointer to dpu_kms structure 168 168 - * @clock_name: clock name to get the rate 169 169 - * 170 170 - * Return: current clock rate 171 171 - */ 172 192 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name); 173 193 174 194 #endif /* __dpu_kms_H__ */

+159 -96

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

reviewed

··· 528 528 529 529 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, 530 530 const struct msm_format *fmt, bool color_fill, 531 531 - struct dpu_sw_pipe_cfg *pipe_cfg, 532 532 - unsigned int rotation) 531 531 + struct dpu_sw_pipe_cfg *pipe_cfg) 533 532 { 534 533 struct dpu_hw_sspp *pipe_hw = pipe->sspp; 535 534 const struct drm_format_info *info = drm_format_info(fmt->pixel_format); ··· 551 552 dst_height, 552 553 &scaler3_cfg, fmt, 553 554 info->hsub, info->vsub, 554 554 - rotation); 555 555 + pipe_cfg->rotation); 555 556 556 557 /* configure pixel extension based on scalar config */ 557 558 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, ··· 603 604 if (pipe->sspp->ops.setup_rects) 604 605 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); 605 606 606 606 - _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); 607 607 + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); 607 608 } 608 609 609 610 /** ··· 695 696 } 696 697 697 698 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, 698 698 - const struct dpu_sspp_sub_blks *sblk, 699 699 - struct drm_rect src, const struct msm_format *fmt) 699 699 + struct dpu_sw_pipe *pipe, 700 700 + struct drm_rect src, 701 701 + const struct msm_format *fmt) 700 702 { 703 703 + const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; 701 704 size_t num_formats; 702 705 const u32 *supported_formats; 706 706 + 707 707 + if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) 708 708 + return -EINVAL; 703 709 704 710 if (!sblk->rotation_cfg) { 705 711 DPU_ERROR("invalid rotation cfg\n"); ··· 735 731 { 736 732 uint32_t min_src_size; 737 733 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 734 734 + int ret; 738 735 739 736 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; 740 737 ··· 773 768 return -EINVAL; 774 769 } 775 770 771 771 + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { 772 772 + ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); 773 773 + if (ret) 774 774 + return ret; 775 775 + } 776 776 + 776 777 /* max clk check */ 777 778 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 778 779 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); ··· 788 777 return 0; 789 778 } 790 779 791 791 - static int dpu_plane_atomic_check(struct drm_plane *plane, 792 792 - struct drm_atomic_state *state) 780 780 + #define MAX_UPSCALE_RATIO 20 781 781 + #define MAX_DOWNSCALE_RATIO 4 782 782 + 783 783 + static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane, 784 784 + struct drm_plane_state *new_plane_state, 785 785 + const struct drm_crtc_state *crtc_state) 793 786 { 794 794 - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 795 795 - plane); 796 796 - int i, ret = 0, min_scale; 787 787 + int i, ret = 0, min_scale, max_scale; 797 788 struct dpu_plane *pdpu = to_dpu_plane(plane); 798 789 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 799 790 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; 800 791 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 801 801 - struct dpu_sw_pipe *pipe = &pstate->pipe; 802 802 - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 803 803 - const struct drm_crtc_state *crtc_state = NULL; 804 804 - const struct msm_format *fmt; 805 792 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 806 793 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 807 794 struct drm_rect fb_rect = { 0 }; 808 795 uint32_t max_linewidth; 809 809 - unsigned int rotation; 810 810 - uint32_t supported_rotations; 811 811 - const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; 812 812 - const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; 813 796 814 814 - if (new_plane_state->crtc) 815 815 - crtc_state = drm_atomic_get_new_crtc_state(state, 816 816 - new_plane_state->crtc); 797 797 + min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); 798 798 + max_scale = MAX_DOWNSCALE_RATIO << 16; 817 799 818 818 - min_scale = FRAC_16_16(1, sblk->maxupscale); 819 800 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 820 801 min_scale, 821 821 - sblk->maxdwnscale << 16, 802 802 + max_scale, 822 803 true, true); 823 804 if (ret) { 824 805 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); ··· 819 816 if (!new_plane_state->visible) 820 817 return 0; 821 818 822 822 - pipe->multirect_index = DPU_SSPP_RECT_SOLO; 823 823 - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 824 824 - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 825 825 - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 826 826 - r_pipe->sspp = NULL; 827 827 - 828 819 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; 829 820 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { 830 821 DPU_ERROR("> %d plane stages assigned\n", ··· 826 829 return -EINVAL; 827 830 } 828 831 829 829 - pipe_cfg->src_rect = new_plane_state->src; 830 830 - 831 832 /* state->src is 16.16, src_rect is not */ 832 832 - pipe_cfg->src_rect.x1 >>= 16; 833 833 - pipe_cfg->src_rect.x2 >>= 16; 834 834 - pipe_cfg->src_rect.y1 >>= 16; 835 835 - pipe_cfg->src_rect.y2 >>= 16; 833 833 + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); 836 834 837 835 pipe_cfg->dst_rect = new_plane_state->dst; 838 836 ··· 852 860 if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE) 853 861 return -E2BIG; 854 862 855 855 - fmt = msm_framebuffer_format(new_plane_state->fb); 856 856 - 857 863 max_linewidth = pdpu->catalog->caps->max_linewidth; 858 864 859 865 drm_rect_rotate(&pipe_cfg->src_rect, ··· 860 870 861 871 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || 862 872 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { 873 873 + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 874 874 + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 875 875 + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 876 876 + return -E2BIG; 877 877 + } 878 878 + 879 879 + *r_pipe_cfg = *pipe_cfg; 880 880 + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 881 881 + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 882 882 + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 883 883 + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 884 884 + } else { 885 885 + memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); 886 886 + } 887 887 + 888 888 + drm_rect_rotate_inv(&pipe_cfg->src_rect, 889 889 + new_plane_state->fb->width, new_plane_state->fb->height, 890 890 + new_plane_state->rotation); 891 891 + if (r_pipe_cfg->src_rect.x1 != 0) 892 892 + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, 893 893 + new_plane_state->fb->width, new_plane_state->fb->height, 894 894 + new_plane_state->rotation); 895 895 + 896 896 + pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 897 897 + 898 898 + return 0; 899 899 + } 900 900 + 901 901 + static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, 902 902 + struct drm_atomic_state *state, 903 903 + const struct drm_crtc_state *crtc_state) 904 904 + { 905 905 + struct drm_plane_state *new_plane_state = 906 906 + drm_atomic_get_new_plane_state(state, plane); 907 907 + struct dpu_plane *pdpu = to_dpu_plane(plane); 908 908 + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 909 909 + struct dpu_sw_pipe *pipe = &pstate->pipe; 910 910 + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 911 911 + const struct msm_format *fmt; 912 912 + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; 913 913 + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; 914 914 + uint32_t max_linewidth; 915 915 + uint32_t supported_rotations; 916 916 + const struct dpu_sspp_cfg *pipe_hw_caps; 917 917 + const struct dpu_sspp_sub_blks *sblk; 918 918 + int ret = 0; 919 919 + 920 920 + pipe_hw_caps = pipe->sspp->cap; 921 921 + sblk = pipe->sspp->cap->sblk; 922 922 + 923 923 + /* 924 924 + * We already have verified scaling against platform limitations. 925 925 + * Now check if the SSPP supports scaling at all. 926 926 + */ 927 927 + if (!sblk->scaler_blk.len && 928 928 + ((drm_rect_width(&new_plane_state->src) >> 16 != 929 929 + drm_rect_width(&new_plane_state->dst)) || 930 930 + (drm_rect_height(&new_plane_state->src) >> 16 != 931 931 + drm_rect_height(&new_plane_state->dst)))) 932 932 + return -ERANGE; 933 933 + 934 934 + fmt = msm_framebuffer_format(new_plane_state->fb); 935 935 + 936 936 + max_linewidth = pdpu->catalog->caps->max_linewidth; 937 937 + 938 938 + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 939 939 + 940 940 + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 941 941 + supported_rotations |= DRM_MODE_ROTATE_90; 942 942 + 943 943 + pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, 944 944 + supported_rotations); 945 945 + r_pipe_cfg->rotation = pipe_cfg->rotation; 946 946 + 947 947 + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, 948 948 + &crtc_state->adjusted_mode); 949 949 + if (ret) 950 950 + return ret; 951 951 + 952 952 + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { 863 953 /* 864 954 * In parallel multirect case only the half of the usual width 865 955 * is supported for tiled formats. If we are here, we know that ··· 953 883 return -E2BIG; 954 884 } 955 885 956 956 - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { 957 957 - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", 958 958 - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); 959 959 - return -E2BIG; 960 960 - } 961 961 - 962 886 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || 963 887 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || 964 888 (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && 965 889 !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || 890 890 + pipe_cfg->rotation & DRM_MODE_ROTATE_90 || 966 891 MSM_FORMAT_IS_YUV(fmt)) { 967 892 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", 968 893 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); ··· 975 910 r_pipe->multirect_index = DPU_SSPP_RECT_1; 976 911 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; 977 912 978 978 - *r_pipe_cfg = *pipe_cfg; 979 979 - pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; 980 980 - pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; 981 981 - r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; 982 982 - r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 983 983 - } 984 984 - 985 985 - drm_rect_rotate_inv(&pipe_cfg->src_rect, 986 986 - new_plane_state->fb->width, new_plane_state->fb->height, 987 987 - new_plane_state->rotation); 988 988 - if (r_pipe->sspp) 989 989 - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, 990 990 - new_plane_state->fb->width, new_plane_state->fb->height, 991 991 - new_plane_state->rotation); 992 992 - 993 993 - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); 994 994 - if (ret) 995 995 - return ret; 996 996 - 997 997 - if (r_pipe->sspp) { 998 913 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, 999 914 &crtc_state->adjusted_mode); 1000 915 if (ret) 1001 916 return ret; 1002 917 } 1003 918 1004 1004 - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; 1005 1005 - 1006 1006 - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) 1007 1007 - supported_rotations |= DRM_MODE_ROTATE_90; 1008 1008 - 1009 1009 - rotation = drm_rotation_simplify(new_plane_state->rotation, 1010 1010 - supported_rotations); 1011 1011 - 1012 1012 - if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && 1013 1013 - (rotation & DRM_MODE_ROTATE_90)) { 1014 1014 - ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); 1015 1015 - if (ret) 1016 1016 - return ret; 1017 1017 - } 1018 1018 - 1019 1019 - pstate->rotation = rotation; 1020 1020 - pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); 1021 1021 - 1022 919 return 0; 920 920 + } 921 921 + 922 922 + static int dpu_plane_atomic_check(struct drm_plane *plane, 923 923 + struct drm_atomic_state *state) 924 924 + { 925 925 + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 926 926 + plane); 927 927 + int ret = 0; 928 928 + struct dpu_plane *pdpu = to_dpu_plane(plane); 929 929 + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); 930 930 + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 931 931 + struct dpu_sw_pipe *pipe = &pstate->pipe; 932 932 + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; 933 933 + const struct drm_crtc_state *crtc_state = NULL; 934 934 + 935 935 + if (new_plane_state->crtc) 936 936 + crtc_state = drm_atomic_get_new_crtc_state(state, 937 937 + new_plane_state->crtc); 938 938 + 939 939 + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 940 940 + r_pipe->sspp = NULL; 941 941 + 942 942 + ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state); 943 943 + if (ret) 944 944 + return ret; 945 945 + 946 946 + if (!new_plane_state->visible) 947 947 + return 0; 948 948 + 949 949 + pipe->multirect_index = DPU_SSPP_RECT_SOLO; 950 950 + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 951 951 + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; 952 952 + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; 953 953 + 954 954 + return dpu_plane_atomic_check_sspp(plane, state, crtc_state); 1023 955 } 1024 956 1025 957 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) ··· 1041 979 1042 980 } 1043 981 982 982 + /** 983 983 + * dpu_plane_flush - final plane operations before commit flush 984 984 + * @plane: Pointer to drm plane structure 985 985 + */ 1044 986 void dpu_plane_flush(struct drm_plane *plane) 1045 987 { 1046 988 struct dpu_plane *pdpu; ··· 1124 1058 pipe_cfg); 1125 1059 } 1126 1060 1127 1127 - _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); 1061 1061 + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); 1128 1062 1129 1063 if (pipe->sspp->ops.setup_multirect) 1130 1064 pipe->sspp->ops.setup_multirect( 1131 1065 pipe); 1132 1066 1133 1067 if (pipe->sspp->ops.setup_format) { 1134 1134 - unsigned int rotation = pstate->rotation; 1068 1068 + unsigned int rotation = pipe_cfg->rotation; 1135 1069 1136 1070 src_flags = 0x0; 1137 1071 ··· 1357 1291 { 1358 1292 struct dpu_plane *pdpu; 1359 1293 struct dpu_plane_state *pstate; 1360 1360 - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); 1361 1294 1362 1295 if (!plane) { 1363 1296 DPU_ERROR("invalid plane\n"); ··· 1377 1312 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n"); 1378 1313 return; 1379 1314 } 1380 1380 - 1381 1381 - /* 1382 1382 - * Set the SSPP here until we have proper virtualized DPU planes. 1383 1383 - * This is the place where the state is allocated, so fill it fully. 1384 1384 - */ 1385 1385 - pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); 1386 1386 - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; 1387 1387 - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; 1388 1388 - 1389 1389 - pstate->r_pipe.sspp = NULL; 1390 1315 1391 1316 __drm_atomic_helper_plane_reset(plane, &pstate->base); 1392 1317 } ··· 1433 1378 .atomic_update = dpu_plane_atomic_update, 1434 1379 }; 1435 1380 1436 1436 - /* initialize plane */ 1381 1381 + /** 1382 1382 + * dpu_plane_init - create new dpu plane for the given pipe 1383 1383 + * @dev: Pointer to DRM device 1384 1384 + * @pipe: dpu hardware pipe identifier 1385 1385 + * @type: Plane type - PRIMARY/OVERLAY/CURSOR 1386 1386 + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 1387 1387 + * 1388 1388 + * Initialize the plane. 1389 1389 + */ 1437 1390 struct drm_plane *dpu_plane_init(struct drm_device *dev, 1438 1391 uint32_t pipe, enum drm_plane_type type, 1439 1392 unsigned long possible_crtcs)

-28

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

reviewed

··· 30 30 * @plane_fetch_bw: calculated BW per plane 31 31 * @plane_clk: calculated clk per plane 32 32 * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed 33 33 - * @rotation: simplified drm rotation hint 34 33 * @layout: framebuffer memory layout 35 34 */ 36 35 struct dpu_plane_state { ··· 47 48 u64 plane_clk; 48 49 49 50 bool needs_dirtyfb; 50 50 - unsigned int rotation; 51 51 52 52 struct dpu_hw_fmt_layout layout; 53 53 }; ··· 54 56 #define to_dpu_plane_state(x) \ 55 57 container_of(x, struct dpu_plane_state, base) 56 58 57 57 - /** 58 58 - * dpu_plane_flush - final plane operations before commit flush 59 59 - * @plane: Pointer to drm plane structure 60 60 - */ 61 59 void dpu_plane_flush(struct drm_plane *plane); 62 60 63 63 - /** 64 64 - * dpu_plane_set_error: enable/disable error condition 65 65 - * @plane: pointer to drm_plane structure 66 66 - */ 67 61 void dpu_plane_set_error(struct drm_plane *plane, bool error); 68 62 69 69 - /** 70 70 - * dpu_plane_init - create new dpu plane for the given pipe 71 71 - * @dev: Pointer to DRM device 72 72 - * @pipe: dpu hardware pipe identifier 73 73 - * @type: Plane type - PRIMARY/OVERLAY/CURSOR 74 74 - * @possible_crtcs: bitmask of crtc that can be attached to the given pipe 75 75 - * 76 76 - */ 77 63 struct drm_plane *dpu_plane_init(struct drm_device *dev, 78 64 uint32_t pipe, enum drm_plane_type type, 79 65 unsigned long possible_crtcs); 80 80 - 81 81 - /** 82 82 - * dpu_plane_color_fill - enables color fill on plane 83 83 - * @plane: Pointer to DRM plane object 84 84 - * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red 85 85 - * @alpha: 8-bit fill alpha value, 255 selects 100% alpha 86 86 - * Returns: 0 on success 87 87 - */ 88 88 - int dpu_plane_color_fill(struct drm_plane *plane, 89 89 - uint32_t color, uint32_t alpha); 90 66 91 67 #ifdef CONFIG_DEBUG_FS 92 68 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable);

+46

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

reviewed

··· 34 34 struct msm_display_topology topology; 35 35 }; 36 36 37 37 + /** 38 38 + * dpu_rm_init - Read hardware catalog and create reservation tracking objects 39 39 + * for all HW blocks. 40 40 + * @dev: Corresponding device for devres management 41 41 + * @rm: DPU Resource Manager handle 42 42 + * @cat: Pointer to hardware catalog 43 43 + * @mdss_data: Pointer to MDSS / UBWC configuration 44 44 + * @mmio: mapped register io address of MDP 45 45 + * @return: 0 on Success otherwise -ERROR 46 46 + */ 37 47 int dpu_rm_init(struct drm_device *dev, 38 48 struct dpu_rm *rm, 39 49 const struct dpu_mdss_cfg *cat, ··· 651 641 } 652 642 } 653 643 644 644 + /** 645 645 + * dpu_rm_release - Given the encoder for the display chain, release any 646 646 + * HW blocks previously reserved for that use case. 647 647 + * @global_state: resources shared across multiple kms objects 648 648 + * @enc: DRM Encoder handle 649 649 + * @return: 0 on Success otherwise -ERROR 650 650 + */ 654 651 void dpu_rm_release(struct dpu_global_state *global_state, 655 652 struct drm_encoder *enc) 656 653 { ··· 674 657 _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); 675 658 } 676 659 660 660 + /** 661 661 + * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 662 662 + * the use connections and user requirements, specified through related 663 663 + * topology control properties, and reserve hardware blocks to that 664 664 + * display chain. 665 665 + * HW blocks can then be accessed through dpu_rm_get_* functions. 666 666 + * HW Reservations should be released via dpu_rm_release_hw. 667 667 + * @rm: DPU Resource Manager handle 668 668 + * @global_state: resources shared across multiple kms objects 669 669 + * @enc: DRM Encoder handle 670 670 + * @crtc_state: Proposed Atomic DRM CRTC State handle 671 671 + * @topology: Pointer to topology info for the display 672 672 + * @return: 0 on Success otherwise -ERROR 673 673 + */ 677 674 int dpu_rm_reserve( 678 675 struct dpu_rm *rm, 679 676 struct dpu_global_state *global_state, ··· 725 694 return ret; 726 695 } 727 696 697 697 + /** 698 698 + * dpu_rm_get_assigned_resources - Get hw resources of the given type that are 699 699 + * assigned to this encoder 700 700 + * @rm: DPU Resource Manager handle 701 701 + * @global_state: resources shared across multiple kms objects 702 702 + * @enc_id: encoder id requesting for allocation 703 703 + * @type: resource type to return data for 704 704 + * @blks: pointer to the array to be filled by HW resources 705 705 + * @blks_size: size of the @blks array 706 706 + */ 728 707 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 729 708 struct dpu_global_state *global_state, uint32_t enc_id, 730 709 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) ··· 813 772 } 814 773 815 774 775 775 + /** 776 776 + * dpu_rm_print_state - output the RM private state 777 777 + * @p: DRM printer 778 778 + * @global_state: global state 779 779 + */ 816 780 void dpu_rm_print_state(struct drm_printer *p, 817 781 const struct dpu_global_state *global_state) 818 782 {

+14 -36

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

reviewed

··· 38 38 }; 39 39 40 40 /** 41 41 - * dpu_rm_init - Read hardware catalog and create reservation tracking objects 42 42 - * for all HW blocks. 43 43 - * @dev: Corresponding device for devres management 44 44 - * @rm: DPU Resource Manager handle 45 45 - * @cat: Pointer to hardware catalog 46 46 - * @mdss_data: Pointer to MDSS / UBWC configuration 47 47 - * @mmio: mapped register io address of MDP 48 48 - * @Return: 0 on Success otherwise -ERROR 41 41 + * struct msm_display_topology - defines a display topology pipeline 42 42 + * @num_lm: number of layer mixers used 43 43 + * @num_intf: number of interfaces the panel is mounted on 44 44 + * @num_dspp: number of dspp blocks used 45 45 + * @num_dsc: number of Display Stream Compression (DSC) blocks used 46 46 + * @needs_cdm: indicates whether cdm block is needed for this display topology 49 47 */ 48 48 + struct msm_display_topology { 49 49 + u32 num_lm; 50 50 + u32 num_intf; 51 51 + u32 num_dspp; 52 52 + u32 num_dsc; 53 53 + bool needs_cdm; 54 54 + }; 55 55 + 50 56 int dpu_rm_init(struct drm_device *dev, 51 57 struct dpu_rm *rm, 52 58 const struct dpu_mdss_cfg *cat, 53 59 const struct msm_mdss_data *mdss_data, 54 60 void __iomem *mmio); 55 61 56 56 - /** 57 57 - * dpu_rm_reserve - Given a CRTC->Encoder->Connector display chain, analyze 58 58 - * the use connections and user requirements, specified through related 59 59 - * topology control properties, and reserve hardware blocks to that 60 60 - * display chain. 61 61 - * HW blocks can then be accessed through dpu_rm_get_* functions. 62 62 - * HW Reservations should be released via dpu_rm_release_hw. 63 63 - * @rm: DPU Resource Manager handle 64 64 - * @drm_enc: DRM Encoder handle 65 65 - * @crtc_state: Proposed Atomic DRM CRTC State handle 66 66 - * @topology: Pointer to topology info for the display 67 67 - * @Return: 0 on Success otherwise -ERROR 68 68 - */ 69 62 int dpu_rm_reserve(struct dpu_rm *rm, 70 63 struct dpu_global_state *global_state, 71 64 struct drm_encoder *drm_enc, 72 65 struct drm_crtc_state *crtc_state, 73 66 struct msm_display_topology topology); 74 67 75 75 - /** 76 76 - * dpu_rm_reserve - Given the encoder for the display chain, release any 77 77 - * HW blocks previously reserved for that use case. 78 78 - * @rm: DPU Resource Manager handle 79 79 - * @enc: DRM Encoder handle 80 80 - * @Return: 0 on Success otherwise -ERROR 81 81 - */ 82 68 void dpu_rm_release(struct dpu_global_state *global_state, 83 69 struct drm_encoder *enc); 84 70 85 85 - /** 86 86 - * Get hw resources of the given type that are assigned to this encoder. 87 87 - */ 88 71 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, 89 72 struct dpu_global_state *global_state, uint32_t enc_id, 90 73 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); 91 74 92 92 - /** 93 93 - * dpu_rm_print_state - output the RM private state 94 94 - * @p: DRM printer 95 95 - * @global_state: global state 96 96 - */ 97 75 void dpu_rm_print_state(struct drm_printer *p, 98 76 const struct dpu_global_state *global_state); 99 77

+13

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c

reviewed

··· 204 204 vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); 205 205 } 206 206 207 207 + /** 208 208 + * dpu_vbif_set_qos_remap - set QoS priority level remap 209 209 + * @dpu_kms: DPU handler 210 210 + * @params: Pointer to QoS configuration parameters 211 211 + */ 207 212 void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, 208 213 struct dpu_vbif_set_qos_params *params) 209 214 { ··· 250 245 } 251 246 } 252 247 248 248 + /** 249 249 + * dpu_vbif_clear_errors - clear any vbif errors 250 250 + * @dpu_kms: DPU handler 251 251 + */ 253 252 void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms) 254 253 { 255 254 struct dpu_hw_vbif *vbif; ··· 271 262 } 272 263 } 273 264 265 265 + /** 266 266 + * dpu_vbif_init_memtypes - initialize xin memory types for vbif 267 267 + * @dpu_kms: DPU handler 268 268 + */ 274 269 void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms) 275 270 { 276 271 struct dpu_hw_vbif *vbif;

-18

drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h

reviewed

··· 38 38 bool is_rt; 39 39 }; 40 40 41 41 - /** 42 42 - * dpu_vbif_set_ot_limit - set OT limit for vbif client 43 43 - * @dpu_kms: DPU handler 44 44 - * @params: Pointer to OT configuration parameters 45 45 - */ 46 41 void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, 47 42 struct dpu_vbif_set_ot_params *params); 48 43 49 49 - /** 50 50 - * dpu_vbif_set_qos_remap - set QoS priority level remap 51 51 - * @dpu_kms: DPU handler 52 52 - * @params: Pointer to QoS configuration parameters 53 53 - */ 54 44 void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, 55 45 struct dpu_vbif_set_qos_params *params); 56 46 57 57 - /** 58 58 - * dpu_vbif_clear_errors - clear any vbif errors 59 59 - * @dpu_kms: DPU handler 60 60 - */ 61 47 void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms); 62 48 63 63 - /** 64 64 - * dpu_vbif_init_memtypes - initialize xin memory types for vbif 65 65 - * @dpu_kms: DPU handler 66 66 - */ 67 49 void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms); 68 50 69 51 void dpu_debugfs_vbif_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root);

+147 -147

drivers/gpu/drm/msm/dp/dp_audio.c

reviewed

··· 17 17 #include "dp_display.h" 18 18 #include "dp_utils.h" 19 19 20 20 - struct dp_audio_private { 20 20 + struct msm_dp_audio_private { 21 21 struct platform_device *audio_pdev; 22 22 struct platform_device *pdev; 23 23 struct drm_device *drm_dev; 24 24 - struct dp_catalog *catalog; 24 24 + struct msm_dp_catalog *catalog; 25 25 26 26 u32 channels; 27 27 28 28 - struct dp_audio dp_audio; 28 28 + struct msm_dp_audio msm_dp_audio; 29 29 }; 30 30 31 31 - static u32 dp_audio_get_header(struct dp_catalog *catalog, 32 32 - enum dp_catalog_audio_sdp_type sdp, 33 33 - enum dp_catalog_audio_header_type header) 31 31 + static u32 msm_dp_audio_get_header(struct msm_dp_catalog *catalog, 32 32 + enum msm_dp_catalog_audio_sdp_type sdp, 33 33 + enum msm_dp_catalog_audio_header_type header) 34 34 { 35 35 - return dp_catalog_audio_get_header(catalog, sdp, header); 35 35 + return msm_dp_catalog_audio_get_header(catalog, sdp, header); 36 36 } 37 37 38 38 - static void dp_audio_set_header(struct dp_catalog *catalog, 38 38 + static void msm_dp_audio_set_header(struct msm_dp_catalog *catalog, 39 39 u32 data, 40 40 - enum dp_catalog_audio_sdp_type sdp, 41 41 - enum dp_catalog_audio_header_type header) 40 40 + enum msm_dp_catalog_audio_sdp_type sdp, 41 41 + enum msm_dp_catalog_audio_header_type header) 42 42 { 43 43 - dp_catalog_audio_set_header(catalog, sdp, header, data); 43 43 + msm_dp_catalog_audio_set_header(catalog, sdp, header, data); 44 44 } 45 45 46 46 - static void dp_audio_stream_sdp(struct dp_audio_private *audio) 46 46 + static void msm_dp_audio_stream_sdp(struct msm_dp_audio_private *audio) 47 47 { 48 48 - struct dp_catalog *catalog = audio->catalog; 48 48 + struct msm_dp_catalog *catalog = audio->catalog; 49 49 u32 value, new_value; 50 50 u8 parity_byte; 51 51 52 52 /* Config header and parity byte 1 */ 53 53 - value = dp_audio_get_header(catalog, 53 53 + value = msm_dp_audio_get_header(catalog, 54 54 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_1); 55 55 56 56 new_value = 0x02; 57 57 - parity_byte = dp_utils_calculate_parity(new_value); 57 57 + parity_byte = msm_dp_utils_calculate_parity(new_value); 58 58 value |= ((new_value << HEADER_BYTE_1_BIT) 59 59 | (parity_byte << PARITY_BYTE_1_BIT)); 60 60 drm_dbg_dp(audio->drm_dev, 61 61 "Header Byte 1: value = 0x%x, parity_byte = 0x%x\n", 62 62 value, parity_byte); 63 63 - dp_audio_set_header(catalog, value, 63 63 + msm_dp_audio_set_header(catalog, value, 64 64 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_1); 65 65 66 66 /* Config header and parity byte 2 */ 67 67 - value = dp_audio_get_header(catalog, 67 67 + value = msm_dp_audio_get_header(catalog, 68 68 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_2); 69 69 new_value = value; 70 70 - parity_byte = dp_utils_calculate_parity(new_value); 70 70 + parity_byte = msm_dp_utils_calculate_parity(new_value); 71 71 value |= ((new_value << HEADER_BYTE_2_BIT) 72 72 | (parity_byte << PARITY_BYTE_2_BIT)); 73 73 drm_dbg_dp(audio->drm_dev, 74 74 "Header Byte 2: value = 0x%x, parity_byte = 0x%x\n", 75 75 value, parity_byte); 76 76 77 77 - dp_audio_set_header(catalog, value, 77 77 + msm_dp_audio_set_header(catalog, value, 78 78 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_2); 79 79 80 80 /* Config header and parity byte 3 */ 81 81 - value = dp_audio_get_header(catalog, 81 81 + value = msm_dp_audio_get_header(catalog, 82 82 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_3); 83 83 84 84 new_value = audio->channels - 1; 85 85 - parity_byte = dp_utils_calculate_parity(new_value); 85 85 + parity_byte = msm_dp_utils_calculate_parity(new_value); 86 86 value |= ((new_value << HEADER_BYTE_3_BIT) 87 87 | (parity_byte << PARITY_BYTE_3_BIT)); 88 88 drm_dbg_dp(audio->drm_dev, 89 89 "Header Byte 3: value = 0x%x, parity_byte = 0x%x\n", 90 90 value, parity_byte); 91 91 92 92 - dp_audio_set_header(catalog, value, 92 92 + msm_dp_audio_set_header(catalog, value, 93 93 DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_3); 94 94 } 95 95 96 96 - static void dp_audio_timestamp_sdp(struct dp_audio_private *audio) 96 96 + static void msm_dp_audio_timestamp_sdp(struct msm_dp_audio_private *audio) 97 97 { 98 98 - struct dp_catalog *catalog = audio->catalog; 98 98 + struct msm_dp_catalog *catalog = audio->catalog; 99 99 u32 value, new_value; 100 100 u8 parity_byte; 101 101 102 102 /* Config header and parity byte 1 */ 103 103 - value = dp_audio_get_header(catalog, 103 103 + value = msm_dp_audio_get_header(catalog, 104 104 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_1); 105 105 106 106 new_value = 0x1; 107 107 - parity_byte = dp_utils_calculate_parity(new_value); 107 107 + parity_byte = msm_dp_utils_calculate_parity(new_value); 108 108 value |= ((new_value << HEADER_BYTE_1_BIT) 109 109 | (parity_byte << PARITY_BYTE_1_BIT)); 110 110 drm_dbg_dp(audio->drm_dev, 111 111 "Header Byte 1: value = 0x%x, parity_byte = 0x%x\n", 112 112 value, parity_byte); 113 113 - dp_audio_set_header(catalog, value, 113 113 + msm_dp_audio_set_header(catalog, value, 114 114 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_1); 115 115 116 116 /* Config header and parity byte 2 */ 117 117 - value = dp_audio_get_header(catalog, 117 117 + value = msm_dp_audio_get_header(catalog, 118 118 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_2); 119 119 120 120 new_value = 0x17; 121 121 - parity_byte = dp_utils_calculate_parity(new_value); 121 121 + parity_byte = msm_dp_utils_calculate_parity(new_value); 122 122 value |= ((new_value << HEADER_BYTE_2_BIT) 123 123 | (parity_byte << PARITY_BYTE_2_BIT)); 124 124 drm_dbg_dp(audio->drm_dev, 125 125 "Header Byte 2: value = 0x%x, parity_byte = 0x%x\n", 126 126 value, parity_byte); 127 127 - dp_audio_set_header(catalog, value, 127 127 + msm_dp_audio_set_header(catalog, value, 128 128 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_2); 129 129 130 130 /* Config header and parity byte 3 */ 131 131 - value = dp_audio_get_header(catalog, 131 131 + value = msm_dp_audio_get_header(catalog, 132 132 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_3); 133 133 134 134 new_value = (0x0 | (0x11 << 2)); 135 135 - parity_byte = dp_utils_calculate_parity(new_value); 135 135 + parity_byte = msm_dp_utils_calculate_parity(new_value); 136 136 value |= ((new_value << HEADER_BYTE_3_BIT) 137 137 | (parity_byte << PARITY_BYTE_3_BIT)); 138 138 drm_dbg_dp(audio->drm_dev, 139 139 "Header Byte 3: value = 0x%x, parity_byte = 0x%x\n", 140 140 value, parity_byte); 141 141 - dp_audio_set_header(catalog, value, 141 141 + msm_dp_audio_set_header(catalog, value, 142 142 DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_3); 143 143 } 144 144 145 145 - static void dp_audio_infoframe_sdp(struct dp_audio_private *audio) 145 145 + static void msm_dp_audio_infoframe_sdp(struct msm_dp_audio_private *audio) 146 146 { 147 147 - struct dp_catalog *catalog = audio->catalog; 147 147 + struct msm_dp_catalog *catalog = audio->catalog; 148 148 u32 value, new_value; 149 149 u8 parity_byte; 150 150 151 151 /* Config header and parity byte 1 */ 152 152 - value = dp_audio_get_header(catalog, 152 152 + value = msm_dp_audio_get_header(catalog, 153 153 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_1); 154 154 155 155 new_value = 0x84; 156 156 - parity_byte = dp_utils_calculate_parity(new_value); 156 156 + parity_byte = msm_dp_utils_calculate_parity(new_value); 157 157 value |= ((new_value << HEADER_BYTE_1_BIT) 158 158 | (parity_byte << PARITY_BYTE_1_BIT)); 159 159 drm_dbg_dp(audio->drm_dev, 160 160 "Header Byte 1: value = 0x%x, parity_byte = 0x%x\n", 161 161 value, parity_byte); 162 162 - dp_audio_set_header(catalog, value, 162 162 + msm_dp_audio_set_header(catalog, value, 163 163 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_1); 164 164 165 165 /* Config header and parity byte 2 */ 166 166 - value = dp_audio_get_header(catalog, 166 166 + value = msm_dp_audio_get_header(catalog, 167 167 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_2); 168 168 169 169 new_value = 0x1b; 170 170 - parity_byte = dp_utils_calculate_parity(new_value); 170 170 + parity_byte = msm_dp_utils_calculate_parity(new_value); 171 171 value |= ((new_value << HEADER_BYTE_2_BIT) 172 172 | (parity_byte << PARITY_BYTE_2_BIT)); 173 173 drm_dbg_dp(audio->drm_dev, 174 174 "Header Byte 2: value = 0x%x, parity_byte = 0x%x\n", 175 175 value, parity_byte); 176 176 - dp_audio_set_header(catalog, value, 176 176 + msm_dp_audio_set_header(catalog, value, 177 177 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_2); 178 178 179 179 /* Config header and parity byte 3 */ 180 180 - value = dp_audio_get_header(catalog, 180 180 + value = msm_dp_audio_get_header(catalog, 181 181 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_3); 182 182 183 183 new_value = (0x0 | (0x11 << 2)); 184 184 - parity_byte = dp_utils_calculate_parity(new_value); 184 184 + parity_byte = msm_dp_utils_calculate_parity(new_value); 185 185 value |= ((new_value << HEADER_BYTE_3_BIT) 186 186 | (parity_byte << PARITY_BYTE_3_BIT)); 187 187 drm_dbg_dp(audio->drm_dev, 188 188 "Header Byte 3: value = 0x%x, parity_byte = 0x%x\n", 189 189 new_value, parity_byte); 190 190 - dp_audio_set_header(catalog, value, 190 190 + msm_dp_audio_set_header(catalog, value, 191 191 DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_3); 192 192 } 193 193 194 194 - static void dp_audio_copy_management_sdp(struct dp_audio_private *audio) 194 194 + static void msm_dp_audio_copy_management_sdp(struct msm_dp_audio_private *audio) 195 195 { 196 196 - struct dp_catalog *catalog = audio->catalog; 196 196 + struct msm_dp_catalog *catalog = audio->catalog; 197 197 u32 value, new_value; 198 198 u8 parity_byte; 199 199 200 200 /* Config header and parity byte 1 */ 201 201 - value = dp_audio_get_header(catalog, 201 201 + value = msm_dp_audio_get_header(catalog, 202 202 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_1); 203 203 204 204 new_value = 0x05; 205 205 - parity_byte = dp_utils_calculate_parity(new_value); 205 205 + parity_byte = msm_dp_utils_calculate_parity(new_value); 206 206 value |= ((new_value << HEADER_BYTE_1_BIT) 207 207 | (parity_byte << PARITY_BYTE_1_BIT)); 208 208 drm_dbg_dp(audio->drm_dev, 209 209 "Header Byte 1: value = 0x%x, parity_byte = 0x%x\n", 210 210 value, parity_byte); 211 211 - dp_audio_set_header(catalog, value, 211 211 + msm_dp_audio_set_header(catalog, value, 212 212 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_1); 213 213 214 214 /* Config header and parity byte 2 */ 215 215 - value = dp_audio_get_header(catalog, 215 215 + value = msm_dp_audio_get_header(catalog, 216 216 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_2); 217 217 218 218 new_value = 0x0F; 219 219 - parity_byte = dp_utils_calculate_parity(new_value); 219 219 + parity_byte = msm_dp_utils_calculate_parity(new_value); 220 220 value |= ((new_value << HEADER_BYTE_2_BIT) 221 221 | (parity_byte << PARITY_BYTE_2_BIT)); 222 222 drm_dbg_dp(audio->drm_dev, 223 223 "Header Byte 2: value = 0x%x, parity_byte = 0x%x\n", 224 224 value, parity_byte); 225 225 - dp_audio_set_header(catalog, value, 225 225 + msm_dp_audio_set_header(catalog, value, 226 226 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_2); 227 227 228 228 /* Config header and parity byte 3 */ 229 229 - value = dp_audio_get_header(catalog, 229 229 + value = msm_dp_audio_get_header(catalog, 230 230 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_3); 231 231 232 232 new_value = 0x0; 233 233 - parity_byte = dp_utils_calculate_parity(new_value); 233 233 + parity_byte = msm_dp_utils_calculate_parity(new_value); 234 234 value |= ((new_value << HEADER_BYTE_3_BIT) 235 235 | (parity_byte << PARITY_BYTE_3_BIT)); 236 236 drm_dbg_dp(audio->drm_dev, 237 237 "Header Byte 3: value = 0x%x, parity_byte = 0x%x\n", 238 238 value, parity_byte); 239 239 - dp_audio_set_header(catalog, value, 239 239 + msm_dp_audio_set_header(catalog, value, 240 240 DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_3); 241 241 } 242 242 243 243 - static void dp_audio_isrc_sdp(struct dp_audio_private *audio) 243 243 + static void msm_dp_audio_isrc_sdp(struct msm_dp_audio_private *audio) 244 244 { 245 245 - struct dp_catalog *catalog = audio->catalog; 245 245 + struct msm_dp_catalog *catalog = audio->catalog; 246 246 u32 value, new_value; 247 247 u8 parity_byte; 248 248 249 249 /* Config header and parity byte 1 */ 250 250 - value = dp_audio_get_header(catalog, 250 250 + value = msm_dp_audio_get_header(catalog, 251 251 DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_1); 252 252 253 253 new_value = 0x06; 254 254 - parity_byte = dp_utils_calculate_parity(new_value); 254 254 + parity_byte = msm_dp_utils_calculate_parity(new_value); 255 255 value |= ((new_value << HEADER_BYTE_1_BIT) 256 256 | (parity_byte << PARITY_BYTE_1_BIT)); 257 257 drm_dbg_dp(audio->drm_dev, 258 258 "Header Byte 1: value = 0x%x, parity_byte = 0x%x\n", 259 259 value, parity_byte); 260 260 - dp_audio_set_header(catalog, value, 260 260 + msm_dp_audio_set_header(catalog, value, 261 261 DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_1); 262 262 263 263 /* Config header and parity byte 2 */ 264 264 - value = dp_audio_get_header(catalog, 264 264 + value = msm_dp_audio_get_header(catalog, 265 265 DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_2); 266 266 267 267 new_value = 0x0F; 268 268 - parity_byte = dp_utils_calculate_parity(new_value); 268 268 + parity_byte = msm_dp_utils_calculate_parity(new_value); 269 269 value |= ((new_value << HEADER_BYTE_2_BIT) 270 270 | (parity_byte << PARITY_BYTE_2_BIT)); 271 271 drm_dbg_dp(audio->drm_dev, 272 272 "Header Byte 2: value = 0x%x, parity_byte = 0x%x\n", 273 273 value, parity_byte); 274 274 - dp_audio_set_header(catalog, value, 274 274 + msm_dp_audio_set_header(catalog, value, 275 275 DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_2); 276 276 } 277 277 278 278 - static void dp_audio_setup_sdp(struct dp_audio_private *audio) 278 278 + static void msm_dp_audio_setup_sdp(struct msm_dp_audio_private *audio) 279 279 { 280 280 - dp_catalog_audio_config_sdp(audio->catalog); 280 280 + msm_dp_catalog_audio_config_sdp(audio->catalog); 281 281 282 282 - dp_audio_stream_sdp(audio); 283 283 - dp_audio_timestamp_sdp(audio); 284 284 - dp_audio_infoframe_sdp(audio); 285 285 - dp_audio_copy_management_sdp(audio); 286 286 - dp_audio_isrc_sdp(audio); 282 282 + msm_dp_audio_stream_sdp(audio); 283 283 + msm_dp_audio_timestamp_sdp(audio); 284 284 + msm_dp_audio_infoframe_sdp(audio); 285 285 + msm_dp_audio_copy_management_sdp(audio); 286 286 + msm_dp_audio_isrc_sdp(audio); 287 287 } 288 288 289 289 - static void dp_audio_setup_acr(struct dp_audio_private *audio) 289 289 + static void msm_dp_audio_setup_acr(struct msm_dp_audio_private *audio) 290 290 { 291 291 u32 select = 0; 292 292 - struct dp_catalog *catalog = audio->catalog; 292 292 + struct msm_dp_catalog *catalog = audio->catalog; 293 293 294 294 - switch (audio->dp_audio.bw_code) { 294 294 + switch (audio->msm_dp_audio.bw_code) { 295 295 case DP_LINK_BW_1_62: 296 296 select = 0; 297 297 break; ··· 310 310 break; 311 311 } 312 312 313 313 - dp_catalog_audio_config_acr(catalog, select); 313 313 + msm_dp_catalog_audio_config_acr(catalog, select); 314 314 } 315 315 316 316 - static void dp_audio_safe_to_exit_level(struct dp_audio_private *audio) 316 316 + static void msm_dp_audio_safe_to_exit_level(struct msm_dp_audio_private *audio) 317 317 { 318 318 - struct dp_catalog *catalog = audio->catalog; 318 318 + struct msm_dp_catalog *catalog = audio->catalog; 319 319 u32 safe_to_exit_level = 0; 320 320 321 321 - switch (audio->dp_audio.lane_count) { 321 321 + switch (audio->msm_dp_audio.lane_count) { 322 322 case 1: 323 323 safe_to_exit_level = 14; 324 324 break; ··· 336 336 break; 337 337 } 338 338 339 339 - dp_catalog_audio_sfe_level(catalog, safe_to_exit_level); 339 339 + msm_dp_catalog_audio_sfe_level(catalog, safe_to_exit_level); 340 340 } 341 341 342 342 - static void dp_audio_enable(struct dp_audio_private *audio, bool enable) 342 342 + static void msm_dp_audio_enable(struct msm_dp_audio_private *audio, bool enable) 343 343 { 344 344 - struct dp_catalog *catalog = audio->catalog; 344 344 + struct msm_dp_catalog *catalog = audio->catalog; 345 345 346 346 - dp_catalog_audio_enable(catalog, enable); 346 346 + msm_dp_catalog_audio_enable(catalog, enable); 347 347 } 348 348 349 349 - static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev) 349 349 + static struct msm_dp_audio_private *msm_dp_audio_get_data(struct platform_device *pdev) 350 350 { 351 351 - struct dp_audio *dp_audio; 352 352 - struct msm_dp *dp_display; 351 351 + struct msm_dp_audio *msm_dp_audio; 352 352 + struct msm_dp *msm_dp_display; 353 353 354 354 if (!pdev) { 355 355 DRM_ERROR("invalid input\n"); 356 356 return ERR_PTR(-ENODEV); 357 357 } 358 358 359 359 - dp_display = platform_get_drvdata(pdev); 360 360 - if (!dp_display) { 359 359 + msm_dp_display = platform_get_drvdata(pdev); 360 360 + if (!msm_dp_display) { 361 361 DRM_ERROR("invalid input\n"); 362 362 return ERR_PTR(-ENODEV); 363 363 } 364 364 365 365 - dp_audio = dp_display->dp_audio; 365 365 + msm_dp_audio = msm_dp_display->msm_dp_audio; 366 366 367 367 - if (!dp_audio) { 368 368 - DRM_ERROR("invalid dp_audio data\n"); 367 367 + if (!msm_dp_audio) { 368 368 + DRM_ERROR("invalid msm_dp_audio data\n"); 369 369 return ERR_PTR(-EINVAL); 370 370 } 371 371 372 372 - return container_of(dp_audio, struct dp_audio_private, dp_audio); 372 372 + return container_of(msm_dp_audio, struct msm_dp_audio_private, msm_dp_audio); 373 373 } 374 374 375 375 - static int dp_audio_hook_plugged_cb(struct device *dev, void *data, 375 375 + static int msm_dp_audio_hook_plugged_cb(struct device *dev, void *data, 376 376 hdmi_codec_plugged_cb fn, 377 377 struct device *codec_dev) 378 378 { 379 379 380 380 struct platform_device *pdev; 381 381 - struct msm_dp *dp_display; 381 381 + struct msm_dp *msm_dp_display; 382 382 383 383 pdev = to_platform_device(dev); 384 384 if (!pdev) { ··· 386 386 return -ENODEV; 387 387 } 388 388 389 389 - dp_display = platform_get_drvdata(pdev); 390 390 - if (!dp_display) { 389 389 + msm_dp_display = platform_get_drvdata(pdev); 390 390 + if (!msm_dp_display) { 391 391 pr_err("invalid input\n"); 392 392 return -ENODEV; 393 393 } 394 394 395 395 - return dp_display_set_plugged_cb(dp_display, fn, codec_dev); 395 395 + return msm_dp_display_set_plugged_cb(msm_dp_display, fn, codec_dev); 396 396 } 397 397 398 398 - static int dp_audio_get_eld(struct device *dev, 398 398 + static int msm_dp_audio_get_eld(struct device *dev, 399 399 void *data, uint8_t *buf, size_t len) 400 400 { 401 401 struct platform_device *pdev; 402 402 - struct msm_dp *dp_display; 402 402 + struct msm_dp *msm_dp_display; 403 403 404 404 pdev = to_platform_device(dev); 405 405 ··· 408 408 return -ENODEV; 409 409 } 410 410 411 411 - dp_display = platform_get_drvdata(pdev); 412 412 - if (!dp_display) { 411 411 + msm_dp_display = platform_get_drvdata(pdev); 412 412 + if (!msm_dp_display) { 413 413 DRM_ERROR("invalid input\n"); 414 414 return -ENODEV; 415 415 } 416 416 417 417 - memcpy(buf, dp_display->connector->eld, 418 418 - min(sizeof(dp_display->connector->eld), len)); 417 417 + memcpy(buf, msm_dp_display->connector->eld, 418 418 + min(sizeof(msm_dp_display->connector->eld), len)); 419 419 420 420 return 0; 421 421 } 422 422 423 423 - int dp_audio_hw_params(struct device *dev, 423 423 + int msm_dp_audio_hw_params(struct device *dev, 424 424 void *data, 425 425 struct hdmi_codec_daifmt *daifmt, 426 426 struct hdmi_codec_params *params) 427 427 { 428 428 int rc = 0; 429 429 - struct dp_audio_private *audio; 429 429 + struct msm_dp_audio_private *audio; 430 430 struct platform_device *pdev; 431 431 - struct msm_dp *dp_display; 431 431 + struct msm_dp *msm_dp_display; 432 432 433 433 pdev = to_platform_device(dev); 434 434 - dp_display = platform_get_drvdata(pdev); 434 434 + msm_dp_display = platform_get_drvdata(pdev); 435 435 436 436 /* 437 437 * there could be cases where sound card can be opened even ··· 441 441 * such cases check for connection status and bail out if not 442 442 * connected. 443 443 */ 444 444 - if (!dp_display->power_on) { 444 444 + if (!msm_dp_display->power_on) { 445 445 rc = -EINVAL; 446 446 goto end; 447 447 } 448 448 449 449 - audio = dp_audio_get_data(pdev); 449 449 + audio = msm_dp_audio_get_data(pdev); 450 450 if (IS_ERR(audio)) { 451 451 rc = PTR_ERR(audio); 452 452 goto end; ··· 454 454 455 455 audio->channels = params->channels; 456 456 457 457 - dp_audio_setup_sdp(audio); 458 458 - dp_audio_setup_acr(audio); 459 459 - dp_audio_safe_to_exit_level(audio); 460 460 - dp_audio_enable(audio, true); 461 461 - dp_display_signal_audio_start(dp_display); 462 462 - dp_display->audio_enabled = true; 457 457 + msm_dp_audio_setup_sdp(audio); 458 458 + msm_dp_audio_setup_acr(audio); 459 459 + msm_dp_audio_safe_to_exit_level(audio); 460 460 + msm_dp_audio_enable(audio, true); 461 461 + msm_dp_display_signal_audio_start(msm_dp_display); 462 462 + msm_dp_display->audio_enabled = true; 463 463 464 464 end: 465 465 return rc; 466 466 } 467 467 468 468 - static void dp_audio_shutdown(struct device *dev, void *data) 468 468 + static void msm_dp_audio_shutdown(struct device *dev, void *data) 469 469 { 470 470 - struct dp_audio_private *audio; 470 470 + struct msm_dp_audio_private *audio; 471 471 struct platform_device *pdev; 472 472 - struct msm_dp *dp_display; 472 472 + struct msm_dp *msm_dp_display; 473 473 474 474 pdev = to_platform_device(dev); 475 475 - dp_display = platform_get_drvdata(pdev); 476 476 - audio = dp_audio_get_data(pdev); 475 475 + msm_dp_display = platform_get_drvdata(pdev); 476 476 + audio = msm_dp_audio_get_data(pdev); 477 477 if (IS_ERR(audio)) { 478 478 DRM_ERROR("failed to get audio data\n"); 479 479 return; ··· 487 487 * connected. is_connected cannot be used here as its set 488 488 * to false earlier than this call 489 489 */ 490 490 - if (!dp_display->audio_enabled) 490 490 + if (!msm_dp_display->audio_enabled) 491 491 return; 492 492 493 493 - dp_audio_enable(audio, false); 493 493 + msm_dp_audio_enable(audio, false); 494 494 /* signal the dp display to safely shutdown clocks */ 495 495 - dp_display_signal_audio_complete(dp_display); 495 495 + msm_dp_display_signal_audio_complete(msm_dp_display); 496 496 } 497 497 498 498 - static const struct hdmi_codec_ops dp_audio_codec_ops = { 499 499 - .hw_params = dp_audio_hw_params, 500 500 - .audio_shutdown = dp_audio_shutdown, 501 501 - .get_eld = dp_audio_get_eld, 502 502 - .hook_plugged_cb = dp_audio_hook_plugged_cb, 498 498 + static const struct hdmi_codec_ops msm_dp_audio_codec_ops = { 499 499 + .hw_params = msm_dp_audio_hw_params, 500 500 + .audio_shutdown = msm_dp_audio_shutdown, 501 501 + .get_eld = msm_dp_audio_get_eld, 502 502 + .hook_plugged_cb = msm_dp_audio_hook_plugged_cb, 503 503 }; 504 504 505 505 static struct hdmi_codec_pdata codec_data = { 506 506 - .ops = &dp_audio_codec_ops, 506 506 + .ops = &msm_dp_audio_codec_ops, 507 507 .max_i2s_channels = 8, 508 508 .i2s = 1, 509 509 }; 510 510 511 511 - void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio) 511 511 + void msm_dp_unregister_audio_driver(struct device *dev, struct msm_dp_audio *msm_dp_audio) 512 512 { 513 513 - struct dp_audio_private *audio_priv; 513 513 + struct msm_dp_audio_private *audio_priv; 514 514 515 515 - audio_priv = container_of(dp_audio, struct dp_audio_private, dp_audio); 515 515 + audio_priv = container_of(msm_dp_audio, struct msm_dp_audio_private, msm_dp_audio); 516 516 517 517 if (audio_priv->audio_pdev) { 518 518 platform_device_unregister(audio_priv->audio_pdev); ··· 520 520 } 521 521 } 522 522 523 523 - int dp_register_audio_driver(struct device *dev, 524 524 - struct dp_audio *dp_audio) 523 523 + int msm_dp_register_audio_driver(struct device *dev, 524 524 + struct msm_dp_audio *msm_dp_audio) 525 525 { 526 526 - struct dp_audio_private *audio_priv; 526 526 + struct msm_dp_audio_private *audio_priv; 527 527 528 528 - audio_priv = container_of(dp_audio, 529 529 - struct dp_audio_private, dp_audio); 528 528 + audio_priv = container_of(msm_dp_audio, 529 529 + struct msm_dp_audio_private, msm_dp_audio); 530 530 531 531 audio_priv->audio_pdev = platform_device_register_data(dev, 532 532 HDMI_CODEC_DRV_NAME, ··· 536 536 return PTR_ERR_OR_ZERO(audio_priv->audio_pdev); 537 537 } 538 538 539 539 - struct dp_audio *dp_audio_get(struct platform_device *pdev, 540 540 - struct dp_panel *panel, 541 541 - struct dp_catalog *catalog) 539 539 + struct msm_dp_audio *msm_dp_audio_get(struct platform_device *pdev, 540 540 + struct msm_dp_panel *panel, 541 541 + struct msm_dp_catalog *catalog) 542 542 { 543 543 int rc = 0; 544 544 - struct dp_audio_private *audio; 545 545 - struct dp_audio *dp_audio; 544 544 + struct msm_dp_audio_private *audio; 545 545 + struct msm_dp_audio *msm_dp_audio; 546 546 547 547 if (!pdev || !panel || !catalog) { 548 548 DRM_ERROR("invalid input\n"); ··· 559 559 audio->pdev = pdev; 560 560 audio->catalog = catalog; 561 561 562 562 - dp_audio = &audio->dp_audio; 562 562 + msm_dp_audio = &audio->msm_dp_audio; 563 563 564 564 - dp_catalog_audio_init(catalog); 564 564 + msm_dp_catalog_audio_init(catalog); 565 565 566 566 - return dp_audio; 566 566 + return msm_dp_audio; 567 567 error: 568 568 return ERR_PTR(rc); 569 569 } 570 570 571 571 - void dp_audio_put(struct dp_audio *dp_audio) 571 571 + void msm_dp_audio_put(struct msm_dp_audio *msm_dp_audio) 572 572 { 573 573 - struct dp_audio_private *audio; 573 573 + struct msm_dp_audio_private *audio; 574 574 575 575 - if (!dp_audio) 575 575 + if (!msm_dp_audio) 576 576 return; 577 577 578 578 - audio = container_of(dp_audio, struct dp_audio_private, dp_audio); 578 578 + audio = container_of(msm_dp_audio, struct msm_dp_audio_private, msm_dp_audio); 579 579 580 580 devm_kfree(&audio->pdev->dev, audio); 581 581 }

+19 -19

drivers/gpu/drm/msm/dp/dp_audio.h

reviewed

··· 13 13 #include <sound/hdmi-codec.h> 14 14 15 15 /** 16 16 - * struct dp_audio 16 16 + * struct msm_dp_audio 17 17 * @lane_count: number of lanes configured in current session 18 18 * @bw_code: link rate's bandwidth code for current session 19 19 */ 20 20 - struct dp_audio { 20 20 + struct msm_dp_audio { 21 21 u32 lane_count; 22 22 u32 bw_code; 23 23 }; 24 24 25 25 /** 26 26 - * dp_audio_get() 26 26 + * msm_dp_audio_get() 27 27 * 28 28 * Creates and instance of dp audio. 29 29 * 30 30 * @pdev: caller's platform device instance. 31 31 - * @panel: an instance of dp_panel module. 32 32 - * @catalog: an instance of dp_catalog module. 31 31 + * @panel: an instance of msm_dp_panel module. 32 32 + * @catalog: an instance of msm_dp_catalog module. 33 33 * 34 34 * Returns the error code in case of failure, otherwize 35 35 - * an instance of newly created dp_module. 35 35 + * an instance of newly created msm_dp_module. 36 36 */ 37 37 - struct dp_audio *dp_audio_get(struct platform_device *pdev, 38 38 - struct dp_panel *panel, 39 39 - struct dp_catalog *catalog); 37 37 + struct msm_dp_audio *msm_dp_audio_get(struct platform_device *pdev, 38 38 + struct msm_dp_panel *panel, 39 39 + struct msm_dp_catalog *catalog); 40 40 41 41 /** 42 42 - * dp_register_audio_driver() 42 42 + * msm_dp_register_audio_driver() 43 43 * 44 44 * Registers DP device with hdmi_codec interface. 45 45 * 46 46 * @dev: DP device instance. 47 47 - * @dp_audio: an instance of dp_audio module. 47 47 + * @msm_dp_audio: an instance of msm_dp_audio module. 48 48 * 49 49 * 50 50 * Returns the error code in case of failure, otherwise 51 51 * zero on success. 52 52 */ 53 53 - int dp_register_audio_driver(struct device *dev, 54 54 - struct dp_audio *dp_audio); 53 53 + int msm_dp_register_audio_driver(struct device *dev, 54 54 + struct msm_dp_audio *msm_dp_audio); 55 55 56 56 - void dp_unregister_audio_driver(struct device *dev, struct dp_audio *dp_audio); 56 56 + void msm_dp_unregister_audio_driver(struct device *dev, struct msm_dp_audio *msm_dp_audio); 57 57 58 58 /** 59 59 - * dp_audio_put() 59 59 + * msm_dp_audio_put() 60 60 * 61 61 - * Cleans the dp_audio instance. 61 61 + * Cleans the msm_dp_audio instance. 62 62 * 63 63 - * @dp_audio: an instance of dp_audio. 63 63 + * @msm_dp_audio: an instance of msm_dp_audio. 64 64 */ 65 65 - void dp_audio_put(struct dp_audio *dp_audio); 65 65 + void msm_dp_audio_put(struct msm_dp_audio *msm_dp_audio); 66 66 67 67 - int dp_audio_hw_params(struct device *dev, 67 67 + int msm_dp_audio_hw_params(struct device *dev, 68 68 void *data, 69 69 struct hdmi_codec_daifmt *daifmt, 70 70 struct hdmi_codec_params *params);

+74 -74

drivers/gpu/drm/msm/dp/dp_aux.c

reviewed

··· 20 20 DP_AUX_ERR_PHY, 21 21 }; 22 22 23 23 - struct dp_aux_private { 23 23 + struct msm_dp_aux_private { 24 24 struct device *dev; 25 25 - struct dp_catalog *catalog; 25 25 + struct msm_dp_catalog *catalog; 26 26 27 27 struct phy *phy; 28 28 ··· 42 42 u32 offset; 43 43 u32 segment; 44 44 45 45 - struct drm_dp_aux dp_aux; 45 45 + struct drm_dp_aux msm_dp_aux; 46 46 }; 47 47 48 48 #define MAX_AUX_RETRIES 5 49 49 50 50 - static ssize_t dp_aux_write(struct dp_aux_private *aux, 50 50 + static ssize_t msm_dp_aux_write(struct msm_dp_aux_private *aux, 51 51 struct drm_dp_aux_msg *msg) 52 52 { 53 53 u8 data[4]; ··· 88 88 /* index = 0, write */ 89 89 if (i == 0) 90 90 reg |= DP_AUX_DATA_INDEX_WRITE; 91 91 - dp_catalog_aux_write_data(aux->catalog, reg); 91 91 + msm_dp_catalog_aux_write_data(aux->catalog, reg); 92 92 } 93 93 94 94 - dp_catalog_aux_clear_trans(aux->catalog, false); 95 95 - dp_catalog_aux_clear_hw_interrupts(aux->catalog); 94 94 + msm_dp_catalog_aux_clear_trans(aux->catalog, false); 95 95 + msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); 96 96 97 97 reg = 0; /* Transaction number == 1 */ 98 98 if (!aux->native) { /* i2c */ ··· 106 106 } 107 107 108 108 reg |= DP_AUX_TRANS_CTRL_GO; 109 109 - dp_catalog_aux_write_trans(aux->catalog, reg); 109 109 + msm_dp_catalog_aux_write_trans(aux->catalog, reg); 110 110 111 111 return len; 112 112 } 113 113 114 114 - static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux, 114 114 + static ssize_t msm_dp_aux_cmd_fifo_tx(struct msm_dp_aux_private *aux, 115 115 struct drm_dp_aux_msg *msg) 116 116 { 117 117 ssize_t ret; ··· 119 119 120 120 reinit_completion(&aux->comp); 121 121 122 122 - ret = dp_aux_write(aux, msg); 122 122 + ret = msm_dp_aux_write(aux, msg); 123 123 if (ret < 0) 124 124 return ret; 125 125 ··· 131 131 return ret; 132 132 } 133 133 134 134 - static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, 134 134 + static ssize_t msm_dp_aux_cmd_fifo_rx(struct msm_dp_aux_private *aux, 135 135 struct drm_dp_aux_msg *msg) 136 136 { 137 137 u32 data; ··· 139 139 u32 i, actual_i; 140 140 u32 len = msg->size; 141 141 142 142 - dp_catalog_aux_clear_trans(aux->catalog, true); 142 142 + msm_dp_catalog_aux_clear_trans(aux->catalog, true); 143 143 144 144 data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */ 145 145 data |= DP_AUX_DATA_READ; /* read */ 146 146 147 147 - dp_catalog_aux_write_data(aux->catalog, data); 147 147 + msm_dp_catalog_aux_write_data(aux->catalog, data); 148 148 149 149 dp = msg->buffer; 150 150 151 151 /* discard first byte */ 152 152 - data = dp_catalog_aux_read_data(aux->catalog); 152 152 + data = msm_dp_catalog_aux_read_data(aux->catalog); 153 153 154 154 for (i = 0; i < len; i++) { 155 155 - data = dp_catalog_aux_read_data(aux->catalog); 155 155 + data = msm_dp_catalog_aux_read_data(aux->catalog); 156 156 *dp++ = (u8)((data >> DP_AUX_DATA_OFFSET) & 0xff); 157 157 158 158 actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; ··· 163 163 return i; 164 164 } 165 165 166 166 - static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux, 166 166 + static void msm_dp_aux_update_offset_and_segment(struct msm_dp_aux_private *aux, 167 167 struct drm_dp_aux_msg *input_msg) 168 168 { 169 169 u32 edid_address = 0x50; ··· 185 185 } 186 186 187 187 /** 188 188 - * dp_aux_transfer_helper() - helper function for EDID read transactions 188 188 + * msm_dp_aux_transfer_helper() - helper function for EDID read transactions 189 189 * 190 190 * @aux: DP AUX private structure 191 191 * @input_msg: input message from DRM upstream APIs ··· 196 196 * This helper function is used to fix EDID reads for non-compliant 197 197 * sinks that do not handle the i2c middle-of-transaction flag correctly. 198 198 */ 199 199 - static void dp_aux_transfer_helper(struct dp_aux_private *aux, 199 199 + static void msm_dp_aux_transfer_helper(struct msm_dp_aux_private *aux, 200 200 struct drm_dp_aux_msg *input_msg, 201 201 bool send_seg) 202 202 { ··· 238 238 helper_msg.address = segment_address; 239 239 helper_msg.buffer = &aux->segment; 240 240 helper_msg.size = 1; 241 241 - dp_aux_cmd_fifo_tx(aux, &helper_msg); 241 241 + msm_dp_aux_cmd_fifo_tx(aux, &helper_msg); 242 242 } 243 243 244 244 /* ··· 252 252 helper_msg.address = input_msg->address; 253 253 helper_msg.buffer = &aux->offset; 254 254 helper_msg.size = 1; 255 255 - dp_aux_cmd_fifo_tx(aux, &helper_msg); 255 255 + msm_dp_aux_cmd_fifo_tx(aux, &helper_msg); 256 256 257 257 end: 258 258 aux->offset += message_size; ··· 265 265 * It will call aux_reset() function to reset the AUX channel, 266 266 * if the waiting is timeout. 267 267 */ 268 268 - static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, 268 268 + static ssize_t msm_dp_aux_transfer(struct drm_dp_aux *msm_dp_aux, 269 269 struct drm_dp_aux_msg *msg) 270 270 { 271 271 ssize_t ret; 272 272 int const aux_cmd_native_max = 16; 273 273 int const aux_cmd_i2c_max = 128; 274 274 - struct dp_aux_private *aux; 274 274 + struct msm_dp_aux_private *aux; 275 275 276 276 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 276 276 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 277 277 278 278 aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); 279 279 ··· 292 292 return -EINVAL; 293 293 } 294 294 295 295 - ret = pm_runtime_resume_and_get(dp_aux->dev); 295 295 + ret = pm_runtime_resume_and_get(msm_dp_aux->dev); 296 296 if (ret) 297 297 return ret; 298 298 ··· 313 313 goto exit; 314 314 } 315 315 316 316 - dp_aux_update_offset_and_segment(aux, msg); 317 317 - dp_aux_transfer_helper(aux, msg, true); 316 316 + msm_dp_aux_update_offset_and_segment(aux, msg); 317 317 + msm_dp_aux_transfer_helper(aux, msg, true); 318 318 319 319 aux->read = msg->request & (DP_AUX_I2C_READ & DP_AUX_NATIVE_READ); 320 320 aux->cmd_busy = true; ··· 327 327 aux->no_send_stop = true; 328 328 } 329 329 330 330 - ret = dp_aux_cmd_fifo_tx(aux, msg); 330 330 + ret = msm_dp_aux_cmd_fifo_tx(aux, msg); 331 331 if (ret < 0) { 332 332 if (aux->native) { 333 333 aux->retry_cnt++; ··· 335 335 phy_calibrate(aux->phy); 336 336 } 337 337 /* reset aux if link is in connected state */ 338 338 - if (dp_catalog_link_is_connected(aux->catalog)) 339 339 - dp_catalog_aux_reset(aux->catalog); 338 338 + if (msm_dp_catalog_link_is_connected(aux->catalog)) 339 339 + msm_dp_catalog_aux_reset(aux->catalog); 340 340 } else { 341 341 aux->retry_cnt = 0; 342 342 switch (aux->aux_error_num) { 343 343 case DP_AUX_ERR_NONE: 344 344 if (aux->read) 345 345 - ret = dp_aux_cmd_fifo_rx(aux, msg); 345 345 + ret = msm_dp_aux_cmd_fifo_rx(aux, msg); 346 346 msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; 347 347 break; 348 348 case DP_AUX_ERR_DEFER: ··· 364 364 365 365 exit: 366 366 mutex_unlock(&aux->mutex); 367 367 - pm_runtime_put_sync(dp_aux->dev); 367 367 + pm_runtime_put_sync(msm_dp_aux->dev); 368 368 369 369 return ret; 370 370 } 371 371 372 372 - irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux) 372 372 + irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux) 373 373 { 374 374 u32 isr; 375 375 - struct dp_aux_private *aux; 375 375 + struct msm_dp_aux_private *aux; 376 376 377 377 - if (!dp_aux) { 377 377 + if (!msm_dp_aux) { 378 378 DRM_ERROR("invalid input\n"); 379 379 return IRQ_NONE; 380 380 } 381 381 382 382 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 382 382 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 383 383 384 384 - isr = dp_catalog_aux_get_irq(aux->catalog); 384 384 + isr = msm_dp_catalog_aux_get_irq(aux->catalog); 385 385 386 386 /* no interrupts pending, return immediately */ 387 387 if (!isr) ··· 403 403 404 404 if (isr & DP_INTR_AUX_ERROR) { 405 405 aux->aux_error_num = DP_AUX_ERR_PHY; 406 406 - dp_catalog_aux_clear_hw_interrupts(aux->catalog); 406 406 + msm_dp_catalog_aux_clear_hw_interrupts(aux->catalog); 407 407 } else if (isr & DP_INTR_NACK_DEFER) { 408 408 aux->aux_error_num = DP_AUX_ERR_NACK_DEFER; 409 409 } else if (isr & DP_INTR_WRONG_ADDR) { ··· 429 429 return IRQ_HANDLED; 430 430 } 431 431 432 432 - void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled) 432 432 + void msm_dp_aux_enable_xfers(struct drm_dp_aux *msm_dp_aux, bool enabled) 433 433 { 434 434 - struct dp_aux_private *aux; 434 434 + struct msm_dp_aux_private *aux; 435 435 436 436 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 436 436 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 437 437 aux->enable_xfers = enabled; 438 438 } 439 439 440 440 - void dp_aux_reconfig(struct drm_dp_aux *dp_aux) 440 440 + void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux) 441 441 { 442 442 - struct dp_aux_private *aux; 442 442 + struct msm_dp_aux_private *aux; 443 443 444 444 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 444 444 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 445 445 446 446 phy_calibrate(aux->phy); 447 447 - dp_catalog_aux_reset(aux->catalog); 447 447 + msm_dp_catalog_aux_reset(aux->catalog); 448 448 } 449 449 450 450 - void dp_aux_init(struct drm_dp_aux *dp_aux) 450 450 + void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux) 451 451 { 452 452 - struct dp_aux_private *aux; 452 452 + struct msm_dp_aux_private *aux; 453 453 454 454 - if (!dp_aux) { 454 454 + if (!msm_dp_aux) { 455 455 DRM_ERROR("invalid input\n"); 456 456 return; 457 457 } 458 458 459 459 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 459 459 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 460 460 461 461 mutex_lock(&aux->mutex); 462 462 463 463 - dp_catalog_aux_enable(aux->catalog, true); 463 463 + msm_dp_catalog_aux_enable(aux->catalog, true); 464 464 aux->retry_cnt = 0; 465 465 aux->initted = true; 466 466 467 467 mutex_unlock(&aux->mutex); 468 468 } 469 469 470 470 - void dp_aux_deinit(struct drm_dp_aux *dp_aux) 470 470 + void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux) 471 471 { 472 472 - struct dp_aux_private *aux; 472 472 + struct msm_dp_aux_private *aux; 473 473 474 474 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 474 474 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 475 475 476 476 mutex_lock(&aux->mutex); 477 477 478 478 aux->initted = false; 479 479 - dp_catalog_aux_enable(aux->catalog, false); 479 479 + msm_dp_catalog_aux_enable(aux->catalog, false); 480 480 481 481 mutex_unlock(&aux->mutex); 482 482 } 483 483 484 484 - int dp_aux_register(struct drm_dp_aux *dp_aux) 484 484 + int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux) 485 485 { 486 486 int ret; 487 487 488 488 - if (!dp_aux) { 488 488 + if (!msm_dp_aux) { 489 489 DRM_ERROR("invalid input\n"); 490 490 return -EINVAL; 491 491 } 492 492 493 493 - ret = drm_dp_aux_register(dp_aux); 493 493 + ret = drm_dp_aux_register(msm_dp_aux); 494 494 if (ret) { 495 495 DRM_ERROR("%s: failed to register drm aux: %d\n", __func__, 496 496 ret); ··· 500 500 return 0; 501 501 } 502 502 503 503 - void dp_aux_unregister(struct drm_dp_aux *dp_aux) 503 503 + void msm_dp_aux_unregister(struct drm_dp_aux *msm_dp_aux) 504 504 { 505 505 - drm_dp_aux_unregister(dp_aux); 505 505 + drm_dp_aux_unregister(msm_dp_aux); 506 506 } 507 507 508 508 - static int dp_wait_hpd_asserted(struct drm_dp_aux *dp_aux, 508 508 + static int msm_dp_wait_hpd_asserted(struct drm_dp_aux *msm_dp_aux, 509 509 unsigned long wait_us) 510 510 { 511 511 int ret; 512 512 - struct dp_aux_private *aux; 512 512 + struct msm_dp_aux_private *aux; 513 513 514 514 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 514 514 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 515 515 516 516 ret = pm_runtime_resume_and_get(aux->dev); 517 517 if (ret) 518 518 return ret; 519 519 520 520 - ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_us); 520 520 + ret = msm_dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_us); 521 521 pm_runtime_put_sync(aux->dev); 522 522 523 523 return ret; 524 524 } 525 525 526 526 - struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, 526 526 + struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalog *catalog, 527 527 struct phy *phy, 528 528 bool is_edp) 529 529 { 530 530 - struct dp_aux_private *aux; 530 530 + struct msm_dp_aux_private *aux; 531 531 532 532 if (!catalog) { 533 533 DRM_ERROR("invalid input\n"); ··· 553 553 * before registering AUX with the DRM device so that 554 554 * msm eDP panel can be detected by generic_dep_panel_probe(). 555 555 */ 556 556 - aux->dp_aux.name = "dpu_dp_aux"; 557 557 - aux->dp_aux.dev = dev; 558 558 - aux->dp_aux.transfer = dp_aux_transfer; 559 559 - aux->dp_aux.wait_hpd_asserted = dp_wait_hpd_asserted; 560 560 - drm_dp_aux_init(&aux->dp_aux); 556 556 + aux->msm_dp_aux.name = "dpu_dp_aux"; 557 557 + aux->msm_dp_aux.dev = dev; 558 558 + aux->msm_dp_aux.transfer = msm_dp_aux_transfer; 559 559 + aux->msm_dp_aux.wait_hpd_asserted = msm_dp_wait_hpd_asserted; 560 560 + drm_dp_aux_init(&aux->msm_dp_aux); 561 561 562 562 - return &aux->dp_aux; 562 562 + return &aux->msm_dp_aux; 563 563 } 564 564 565 565 - void dp_aux_put(struct drm_dp_aux *dp_aux) 565 565 + void msm_dp_aux_put(struct drm_dp_aux *msm_dp_aux) 566 566 { 567 567 - struct dp_aux_private *aux; 567 567 + struct msm_dp_aux_private *aux; 568 568 569 569 - if (!dp_aux) 569 569 + if (!msm_dp_aux) 570 570 return; 571 571 572 572 - aux = container_of(dp_aux, struct dp_aux_private, dp_aux); 572 572 + aux = container_of(msm_dp_aux, struct msm_dp_aux_private, msm_dp_aux); 573 573 574 574 mutex_destroy(&aux->mutex); 575 575

+9 -9

drivers/gpu/drm/msm/dp/dp_aux.h

reviewed

··· 9 9 #include "dp_catalog.h" 10 10 #include <drm/display/drm_dp_helper.h> 11 11 12 12 - int dp_aux_register(struct drm_dp_aux *dp_aux); 13 13 - void dp_aux_unregister(struct drm_dp_aux *dp_aux); 14 14 - irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux); 15 15 - void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled); 16 16 - void dp_aux_init(struct drm_dp_aux *dp_aux); 17 17 - void dp_aux_deinit(struct drm_dp_aux *dp_aux); 18 18 - void dp_aux_reconfig(struct drm_dp_aux *dp_aux); 12 12 + int msm_dp_aux_register(struct drm_dp_aux *msm_dp_aux); 13 13 + void msm_dp_aux_unregister(struct drm_dp_aux *msm_dp_aux); 14 14 + irqreturn_t msm_dp_aux_isr(struct drm_dp_aux *msm_dp_aux); 15 15 + void msm_dp_aux_enable_xfers(struct drm_dp_aux *msm_dp_aux, bool enabled); 16 16 + void msm_dp_aux_init(struct drm_dp_aux *msm_dp_aux); 17 17 + void msm_dp_aux_deinit(struct drm_dp_aux *msm_dp_aux); 18 18 + void msm_dp_aux_reconfig(struct drm_dp_aux *msm_dp_aux); 19 19 20 20 struct phy; 21 21 - struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, 21 21 + struct drm_dp_aux *msm_dp_aux_get(struct device *dev, struct msm_dp_catalog *catalog, 22 22 struct phy *phy, 23 23 bool is_edp); 24 24 - void dp_aux_put(struct drm_dp_aux *aux); 24 24 + void msm_dp_aux_put(struct drm_dp_aux *aux); 25 25 26 26 #endif /*__DP_AUX_H_*/

+366 -366

drivers/gpu/drm/msm/dp/dp_catalog.c

reviewed

··· 75 75 struct dss_io_region p0; 76 76 }; 77 77 78 78 - struct dp_catalog_private { 78 78 + struct msm_dp_catalog_private { 79 79 struct device *dev; 80 80 struct drm_device *drm_dev; 81 81 struct dss_io_data io; 82 82 u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX]; 83 83 - struct dp_catalog dp_catalog; 83 83 + struct msm_dp_catalog msm_dp_catalog; 84 84 }; 85 85 86 86 - void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state) 86 86 + void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct msm_disp_state *disp_state) 87 87 { 88 88 - struct dp_catalog_private *catalog = container_of(dp_catalog, 89 89 - struct dp_catalog_private, dp_catalog); 88 88 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 89 89 + struct msm_dp_catalog_private, msm_dp_catalog); 90 90 struct dss_io_data *dss = &catalog->io; 91 91 92 92 msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb"); ··· 95 95 msm_disp_snapshot_add_block(disp_state, dss->p0.len, dss->p0.base, "dp_p0"); 96 96 } 97 97 98 98 - static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) 98 98 + static inline u32 msm_dp_read_aux(struct msm_dp_catalog_private *catalog, u32 offset) 99 99 { 100 100 return readl_relaxed(catalog->io.aux.base + offset); 101 101 } 102 102 103 103 - static inline void dp_write_aux(struct dp_catalog_private *catalog, 103 103 + static inline void msm_dp_write_aux(struct msm_dp_catalog_private *catalog, 104 104 u32 offset, u32 data) 105 105 { 106 106 /* ··· 110 110 writel(data, catalog->io.aux.base + offset); 111 111 } 112 112 113 113 - static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset) 113 113 + static inline u32 msm_dp_read_ahb(const struct msm_dp_catalog_private *catalog, u32 offset) 114 114 { 115 115 return readl_relaxed(catalog->io.ahb.base + offset); 116 116 } 117 117 118 118 - static inline void dp_write_ahb(struct dp_catalog_private *catalog, 118 118 + static inline void msm_dp_write_ahb(struct msm_dp_catalog_private *catalog, 119 119 u32 offset, u32 data) 120 120 { 121 121 /* ··· 125 125 writel(data, catalog->io.ahb.base + offset); 126 126 } 127 127 128 128 - static inline void dp_write_p0(struct dp_catalog_private *catalog, 128 128 + static inline void msm_dp_write_p0(struct msm_dp_catalog_private *catalog, 129 129 u32 offset, u32 data) 130 130 { 131 131 /* ··· 135 135 writel(data, catalog->io.p0.base + offset); 136 136 } 137 137 138 138 - static inline u32 dp_read_p0(struct dp_catalog_private *catalog, 138 138 + static inline u32 msm_dp_read_p0(struct msm_dp_catalog_private *catalog, 139 139 u32 offset) 140 140 { 141 141 /* ··· 145 145 return readl_relaxed(catalog->io.p0.base + offset); 146 146 } 147 147 148 148 - static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) 148 148 + static inline u32 msm_dp_read_link(struct msm_dp_catalog_private *catalog, u32 offset) 149 149 { 150 150 return readl_relaxed(catalog->io.link.base + offset); 151 151 } 152 152 153 153 - static inline void dp_write_link(struct dp_catalog_private *catalog, 153 153 + static inline void msm_dp_write_link(struct msm_dp_catalog_private *catalog, 154 154 u32 offset, u32 data) 155 155 { 156 156 /* ··· 161 161 } 162 162 163 163 /* aux related catalog functions */ 164 164 - u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog) 164 164 + u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog) 165 165 { 166 166 - struct dp_catalog_private *catalog = container_of(dp_catalog, 167 167 - struct dp_catalog_private, dp_catalog); 166 166 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 167 167 + struct msm_dp_catalog_private, msm_dp_catalog); 168 168 169 169 - return dp_read_aux(catalog, REG_DP_AUX_DATA); 169 169 + return msm_dp_read_aux(catalog, REG_DP_AUX_DATA); 170 170 } 171 171 172 172 - int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data) 172 172 + int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u32 data) 173 173 { 174 174 - struct dp_catalog_private *catalog = container_of(dp_catalog, 175 175 - struct dp_catalog_private, dp_catalog); 174 174 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 175 175 + struct msm_dp_catalog_private, msm_dp_catalog); 176 176 177 177 - dp_write_aux(catalog, REG_DP_AUX_DATA, data); 177 177 + msm_dp_write_aux(catalog, REG_DP_AUX_DATA, data); 178 178 return 0; 179 179 } 180 180 181 181 - int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data) 181 181 + int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, u32 data) 182 182 { 183 183 - struct dp_catalog_private *catalog = container_of(dp_catalog, 184 184 - struct dp_catalog_private, dp_catalog); 183 183 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 184 184 + struct msm_dp_catalog_private, msm_dp_catalog); 185 185 186 186 - dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); 186 186 + msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); 187 187 return 0; 188 188 } 189 189 190 190 - int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read) 190 190 + int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, bool read) 191 191 { 192 192 u32 data; 193 193 - struct dp_catalog_private *catalog = container_of(dp_catalog, 194 194 - struct dp_catalog_private, dp_catalog); 193 193 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 194 194 + struct msm_dp_catalog_private, msm_dp_catalog); 195 195 196 196 if (read) { 197 197 - data = dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL); 197 197 + data = msm_dp_read_aux(catalog, REG_DP_AUX_TRANS_CTRL); 198 198 data &= ~DP_AUX_TRANS_CTRL_GO; 199 199 - dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); 199 199 + msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data); 200 200 } else { 201 201 - dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0); 201 201 + msm_dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, 0); 202 202 } 203 203 return 0; 204 204 } 205 205 206 206 - int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog) 206 206 + int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_catalog) 207 207 { 208 208 - struct dp_catalog_private *catalog = container_of(dp_catalog, 209 209 - struct dp_catalog_private, dp_catalog); 208 208 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 209 209 + struct msm_dp_catalog_private, msm_dp_catalog); 210 210 211 211 - dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); 212 212 - dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); 213 213 - dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); 214 214 - dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); 211 211 + msm_dp_read_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_STATUS); 212 212 + msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x1f); 213 213 + msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0x9f); 214 214 + msm_dp_write_aux(catalog, REG_DP_PHY_AUX_INTERRUPT_CLEAR, 0); 215 215 return 0; 216 216 } 217 217 218 218 /** 219 219 - * dp_catalog_aux_reset() - reset AUX controller 219 219 + * msm_dp_catalog_aux_reset() - reset AUX controller 220 220 * 221 221 - * @dp_catalog: DP catalog structure 221 221 + * @msm_dp_catalog: DP catalog structure 222 222 * 223 223 * return: void 224 224 * ··· 227 227 * NOTE: reset AUX controller will also clear any pending HPD related interrupts 228 228 * 229 229 */ 230 230 - void dp_catalog_aux_reset(struct dp_catalog *dp_catalog) 230 230 + void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog) 231 231 { 232 232 u32 aux_ctrl; 233 233 - struct dp_catalog_private *catalog = container_of(dp_catalog, 234 234 - struct dp_catalog_private, dp_catalog); 233 233 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 234 234 + struct msm_dp_catalog_private, msm_dp_catalog); 235 235 236 236 - aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL); 236 236 + aux_ctrl = msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); 237 237 238 238 aux_ctrl |= DP_AUX_CTRL_RESET; 239 239 - dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 239 239 + msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 240 240 usleep_range(1000, 1100); /* h/w recommended delay */ 241 241 242 242 aux_ctrl &= ~DP_AUX_CTRL_RESET; 243 243 - dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 243 243 + msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 244 244 } 245 245 246 246 - void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable) 246 246 + void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool enable) 247 247 { 248 248 u32 aux_ctrl; 249 249 - struct dp_catalog_private *catalog = container_of(dp_catalog, 250 250 - struct dp_catalog_private, dp_catalog); 249 249 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 250 250 + struct msm_dp_catalog_private, msm_dp_catalog); 251 251 252 252 - aux_ctrl = dp_read_aux(catalog, REG_DP_AUX_CTRL); 252 252 + aux_ctrl = msm_dp_read_aux(catalog, REG_DP_AUX_CTRL); 253 253 254 254 if (enable) { 255 255 - dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff); 256 256 - dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff); 255 255 + msm_dp_write_aux(catalog, REG_DP_TIMEOUT_COUNT, 0xffff); 256 256 + msm_dp_write_aux(catalog, REG_DP_AUX_LIMITS, 0xffff); 257 257 aux_ctrl |= DP_AUX_CTRL_ENABLE; 258 258 } else { 259 259 aux_ctrl &= ~DP_AUX_CTRL_ENABLE; 260 260 } 261 261 262 262 - dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 262 262 + msm_dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); 263 263 } 264 264 265 265 - int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog, 265 265 + int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *msm_dp_catalog, 266 266 unsigned long wait_us) 267 267 { 268 268 u32 state; 269 269 - struct dp_catalog_private *catalog = container_of(dp_catalog, 270 270 - struct dp_catalog_private, dp_catalog); 269 269 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 270 270 + struct msm_dp_catalog_private, msm_dp_catalog); 271 271 272 272 /* poll for hpd connected status every 2ms and timeout after wait_us */ 273 273 return readl_poll_timeout(catalog->io.aux.base + ··· 294 294 } 295 295 } 296 296 297 297 - void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) 297 297 + void msm_dp_catalog_dump_regs(struct msm_dp_catalog *msm_dp_catalog) 298 298 { 299 299 - struct dp_catalog_private *catalog = container_of(dp_catalog, 300 300 - struct dp_catalog_private, dp_catalog); 299 299 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 300 300 + struct msm_dp_catalog_private, msm_dp_catalog); 301 301 struct dss_io_data *io = &catalog->io; 302 302 303 303 pr_info("AHB regs\n"); ··· 313 313 dump_regs(io->p0.base, io->p0.len); 314 314 } 315 315 316 316 - u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) 316 316 + u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog) 317 317 { 318 318 - struct dp_catalog_private *catalog = container_of(dp_catalog, 319 319 - struct dp_catalog_private, dp_catalog); 318 318 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 319 319 + struct msm_dp_catalog_private, msm_dp_catalog); 320 320 u32 intr, intr_ack; 321 321 322 322 - intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS); 322 322 + intr = msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS); 323 323 intr &= ~DP_INTERRUPT_STATUS1_MASK; 324 324 intr_ack = (intr & DP_INTERRUPT_STATUS1) 325 325 << DP_INTERRUPT_STATUS_ACK_SHIFT; 326 326 - dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack | 326 326 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, intr_ack | 327 327 DP_INTERRUPT_STATUS1_MASK); 328 328 329 329 return intr; ··· 331 331 } 332 332 333 333 /* controller related catalog functions */ 334 334 - void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog, 335 335 - u32 dp_tu, u32 valid_boundary, 334 334 + void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_dp_catalog, 335 335 + u32 msm_dp_tu, u32 valid_boundary, 336 336 u32 valid_boundary2) 337 337 { 338 338 - struct dp_catalog_private *catalog = container_of(dp_catalog, 339 339 - struct dp_catalog_private, dp_catalog); 338 338 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 339 339 + struct msm_dp_catalog_private, msm_dp_catalog); 340 340 341 341 - dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary); 342 342 - dp_write_link(catalog, REG_DP_TU, dp_tu); 343 343 - dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2); 341 341 + msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY, valid_boundary); 342 342 + msm_dp_write_link(catalog, REG_DP_TU, msm_dp_tu); 343 343 + msm_dp_write_link(catalog, REG_DP_VALID_BOUNDARY_2, valid_boundary2); 344 344 } 345 345 346 346 - void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state) 346 346 + void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog, u32 state) 347 347 { 348 348 - struct dp_catalog_private *catalog = container_of(dp_catalog, 349 349 - struct dp_catalog_private, dp_catalog); 348 348 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 349 349 + struct msm_dp_catalog_private, msm_dp_catalog); 350 350 351 351 - dp_write_link(catalog, REG_DP_STATE_CTRL, state); 351 351 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, state); 352 352 } 353 353 354 354 - void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 cfg) 354 354 + void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog, u32 cfg) 355 355 { 356 356 - struct dp_catalog_private *catalog = container_of(dp_catalog, 357 357 - struct dp_catalog_private, dp_catalog); 356 356 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 357 357 + struct msm_dp_catalog_private, msm_dp_catalog); 358 358 359 359 drm_dbg_dp(catalog->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", cfg); 360 360 361 361 - dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg); 361 361 + msm_dp_write_link(catalog, REG_DP_CONFIGURATION_CTRL, cfg); 362 362 } 363 363 364 364 - void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog) 364 364 + void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalog) 365 365 { 366 366 - struct dp_catalog_private *catalog = container_of(dp_catalog, 367 367 - struct dp_catalog_private, dp_catalog); 366 366 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 367 367 + struct msm_dp_catalog_private, msm_dp_catalog); 368 368 u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */ 369 369 u32 ln_mapping; 370 370 ··· 373 373 ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT; 374 374 ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT; 375 375 376 376 - dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, 376 376 + msm_dp_write_link(catalog, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, 377 377 ln_mapping); 378 378 } 379 379 380 380 - void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, 380 380 + void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp_catalog, 381 381 bool enable) 382 382 { 383 383 u32 val; 384 384 - struct dp_catalog_private *catalog = container_of(dp_catalog, 385 385 - struct dp_catalog_private, dp_catalog); 384 384 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 385 385 + struct msm_dp_catalog_private, msm_dp_catalog); 386 386 387 387 - val = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 387 387 + val = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 388 388 389 389 if (enable) 390 390 val |= DP_MAINLINK_CTRL_ENABLE; 391 391 else 392 392 val &= ~DP_MAINLINK_CTRL_ENABLE; 393 393 394 394 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); 394 394 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, val); 395 395 } 396 396 397 397 - void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, 397 397 + void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catalog, 398 398 bool enable) 399 399 { 400 400 u32 mainlink_ctrl; 401 401 - struct dp_catalog_private *catalog = container_of(dp_catalog, 402 402 - struct dp_catalog_private, dp_catalog); 401 401 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 402 402 + struct msm_dp_catalog_private, msm_dp_catalog); 403 403 404 404 drm_dbg_dp(catalog->drm_dev, "enable=%d\n", enable); 405 405 if (enable) { 406 406 /* 407 407 * To make sure link reg writes happens before other operation, 408 408 - * dp_write_link() function uses writel() 408 408 + * msm_dp_write_link() function uses writel() 409 409 */ 410 410 - mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 410 410 + mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 411 411 412 412 mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | 413 413 DP_MAINLINK_CTRL_ENABLE); 414 414 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 414 414 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 415 415 416 416 mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; 417 417 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 417 417 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 418 418 419 419 mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; 420 420 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 420 420 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 421 421 422 422 mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | 423 423 DP_MAINLINK_FB_BOUNDARY_SEL); 424 424 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 424 424 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 425 425 } else { 426 426 - mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 426 426 + mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 427 427 mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; 428 428 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 428 428 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 429 429 } 430 430 } 431 431 432 432 - void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, 432 432 + void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, 433 433 u32 colorimetry_cfg, 434 434 u32 test_bits_depth) 435 435 { 436 436 u32 misc_val; 437 437 - struct dp_catalog_private *catalog = container_of(dp_catalog, 438 438 - struct dp_catalog_private, dp_catalog); 437 437 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 438 438 + struct msm_dp_catalog_private, msm_dp_catalog); 439 439 440 440 - misc_val = dp_read_link(catalog, REG_DP_MISC1_MISC0); 440 440 + misc_val = msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); 441 441 442 442 /* clear bpp bits */ 443 443 misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); ··· 447 447 misc_val |= DP_MISC0_SYNCHRONOUS_CLK; 448 448 449 449 drm_dbg_dp(catalog->drm_dev, "misc settings = 0x%x\n", misc_val); 450 450 - dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); 450 450 + msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); 451 451 } 452 452 453 453 - void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) 453 453 + void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_catalog) 454 454 { 455 455 u32 mainlink_ctrl, hw_revision; 456 456 - struct dp_catalog_private *catalog = container_of(dp_catalog, 457 457 - struct dp_catalog_private, dp_catalog); 456 456 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 457 457 + struct msm_dp_catalog_private, msm_dp_catalog); 458 458 459 459 - mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 459 459 + mainlink_ctrl = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 460 460 461 461 - hw_revision = dp_catalog_hw_revision(dp_catalog); 461 461 + hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog); 462 462 if (hw_revision >= DP_HW_VERSION_1_2) 463 463 mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; 464 464 else 465 465 mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; 466 466 467 467 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 467 467 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); 468 468 } 469 469 470 470 - void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, 470 470 + void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, 471 471 u32 rate, u32 stream_rate_khz, 472 472 bool is_ycbcr_420) 473 473 { ··· 478 478 u32 const link_rate_hbr3 = 810000; 479 479 unsigned long den, num; 480 480 481 481 - struct dp_catalog_private *catalog = container_of(dp_catalog, 482 482 - struct dp_catalog_private, dp_catalog); 481 481 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 482 482 + struct msm_dp_catalog_private, msm_dp_catalog); 483 483 484 484 if (rate == link_rate_hbr3) 485 485 pixel_div = 6; ··· 522 522 nvid *= 3; 523 523 524 524 drm_dbg_dp(catalog->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); 525 525 - dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); 526 526 - dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); 527 527 - dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); 525 525 + msm_dp_write_link(catalog, REG_DP_SOFTWARE_MVID, mvid); 526 526 + msm_dp_write_link(catalog, REG_DP_SOFTWARE_NVID, nvid); 527 527 + msm_dp_write_p0(catalog, MMSS_DP_DSC_DTO, 0x0); 528 528 } 529 529 530 530 - int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, 530 530 + int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_dp_catalog, 531 531 u32 state_bit) 532 532 { 533 533 int bit, ret; 534 534 u32 data; 535 535 - struct dp_catalog_private *catalog = container_of(dp_catalog, 536 536 - struct dp_catalog_private, dp_catalog); 535 535 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 536 536 + struct msm_dp_catalog_private, msm_dp_catalog); 537 537 538 538 bit = BIT(state_bit - 1); 539 539 drm_dbg_dp(catalog->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); 540 540 - dp_catalog_ctrl_state_ctrl(dp_catalog, bit); 540 540 + msm_dp_catalog_ctrl_state_ctrl(msm_dp_catalog, bit); 541 541 542 542 bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; 543 543 ··· 554 554 } 555 555 556 556 /** 557 557 - * dp_catalog_hw_revision() - retrieve DP hw revision 557 557 + * msm_dp_catalog_hw_revision() - retrieve DP hw revision 558 558 * 559 559 - * @dp_catalog: DP catalog structure 559 559 + * @msm_dp_catalog: DP catalog structure 560 560 * 561 561 * Return: DP controller hw revision 562 562 * 563 563 */ 564 564 - u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog) 564 564 + u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog) 565 565 { 566 566 - const struct dp_catalog_private *catalog = container_of(dp_catalog, 567 567 - struct dp_catalog_private, dp_catalog); 566 566 + const struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 567 567 + struct msm_dp_catalog_private, msm_dp_catalog); 568 568 569 569 - return dp_read_ahb(catalog, REG_DP_HW_VERSION); 569 569 + return msm_dp_read_ahb(catalog, REG_DP_HW_VERSION); 570 570 } 571 571 572 572 /** 573 573 - * dp_catalog_ctrl_reset() - reset DP controller 573 573 + * msm_dp_catalog_ctrl_reset() - reset DP controller 574 574 * 575 575 - * @dp_catalog: DP catalog structure 575 575 + * @msm_dp_catalog: DP catalog structure 576 576 * 577 577 * return: void 578 578 * ··· 581 581 * NOTE: reset DP controller will also clear any pending HPD related interrupts 582 582 * 583 583 */ 584 584 - void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog) 584 584 + void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog) 585 585 { 586 586 u32 sw_reset; 587 587 - struct dp_catalog_private *catalog = container_of(dp_catalog, 588 588 - struct dp_catalog_private, dp_catalog); 587 587 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 588 588 + struct msm_dp_catalog_private, msm_dp_catalog); 589 589 590 590 - sw_reset = dp_read_ahb(catalog, REG_DP_SW_RESET); 590 590 + sw_reset = msm_dp_read_ahb(catalog, REG_DP_SW_RESET); 591 591 592 592 sw_reset |= DP_SW_RESET; 593 593 - dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); 593 593 + msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); 594 594 usleep_range(1000, 1100); /* h/w recommended delay */ 595 595 596 596 sw_reset &= ~DP_SW_RESET; 597 597 - dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); 597 597 + msm_dp_write_ahb(catalog, REG_DP_SW_RESET, sw_reset); 598 598 } 599 599 600 600 - bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) 600 600 + bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog) 601 601 { 602 602 u32 data; 603 603 int ret; 604 604 - struct dp_catalog_private *catalog = container_of(dp_catalog, 605 605 - struct dp_catalog_private, dp_catalog); 604 604 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 605 605 + struct msm_dp_catalog_private, msm_dp_catalog); 606 606 607 607 /* Poll for mainlink ready status */ 608 608 ret = readl_poll_timeout(catalog->io.link.base + ··· 617 617 return true; 618 618 } 619 619 620 620 - void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, 620 620 + void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, 621 621 bool enable) 622 622 { 623 623 - struct dp_catalog_private *catalog = container_of(dp_catalog, 624 624 - struct dp_catalog_private, dp_catalog); 623 623 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 624 624 + struct msm_dp_catalog_private, msm_dp_catalog); 625 625 626 626 if (enable) { 627 627 - dp_write_ahb(catalog, REG_DP_INTR_STATUS, 627 627 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, 628 628 DP_INTERRUPT_STATUS1_MASK); 629 629 - dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 629 629 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 630 630 DP_INTERRUPT_STATUS2_MASK); 631 631 } else { 632 632 - dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00); 633 633 - dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00); 632 632 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS, 0x00); 633 633 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 0x00); 634 634 } 635 635 } 636 636 637 637 - void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, 637 637 + void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, 638 638 u32 intr_mask, bool en) 639 639 { 640 640 - struct dp_catalog_private *catalog = container_of(dp_catalog, 641 641 - struct dp_catalog_private, dp_catalog); 640 640 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 641 641 + struct msm_dp_catalog_private, msm_dp_catalog); 642 642 643 643 - u32 config = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); 643 643 + u32 config = msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); 644 644 645 645 config = (en ? config | intr_mask : config & ~intr_mask); 646 646 647 647 drm_dbg_dp(catalog->drm_dev, "intr_mask=%#x config=%#x\n", 648 648 intr_mask, config); 649 649 - dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, 649 649 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_MASK, 650 650 config & DP_DP_HPD_INT_MASK); 651 651 } 652 652 653 653 - void dp_catalog_ctrl_hpd_enable(struct dp_catalog *dp_catalog) 653 653 + void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog) 654 654 { 655 655 - struct dp_catalog_private *catalog = container_of(dp_catalog, 656 656 - struct dp_catalog_private, dp_catalog); 655 655 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 656 656 + struct msm_dp_catalog_private, msm_dp_catalog); 657 657 658 658 - u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); 658 658 + u32 reftimer = msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); 659 659 660 660 /* Configure REFTIMER and enable it */ 661 661 reftimer |= DP_DP_HPD_REFTIMER_ENABLE; 662 662 - dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); 662 662 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); 663 663 664 664 /* Enable HPD */ 665 665 - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); 665 665 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN); 666 666 } 667 667 668 668 - void dp_catalog_ctrl_hpd_disable(struct dp_catalog *dp_catalog) 668 668 + void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog) 669 669 { 670 670 - struct dp_catalog_private *catalog = container_of(dp_catalog, 671 671 - struct dp_catalog_private, dp_catalog); 670 670 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 671 671 + struct msm_dp_catalog_private, msm_dp_catalog); 672 672 673 673 - u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); 673 673 + u32 reftimer = msm_dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); 674 674 675 675 reftimer &= ~DP_DP_HPD_REFTIMER_ENABLE; 676 676 - dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); 676 676 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_REFTIMER, reftimer); 677 677 678 678 - dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0); 678 678 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, 0); 679 679 } 680 680 681 681 - static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog) 681 681 + static void msm_dp_catalog_enable_sdp(struct msm_dp_catalog_private *catalog) 682 682 { 683 683 /* trigger sdp */ 684 684 - dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); 685 685 - dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0); 684 684 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, UPDATE_SDP); 685 685 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0); 686 686 } 687 687 688 688 - void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog) 688 688 + void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog) 689 689 { 690 690 - struct dp_catalog_private *catalog = container_of(dp_catalog, 691 691 - struct dp_catalog_private, dp_catalog); 690 690 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 691 691 + struct msm_dp_catalog_private, msm_dp_catalog); 692 692 u32 config; 693 693 694 694 /* enable PSR1 function */ 695 695 - config = dp_read_link(catalog, REG_PSR_CONFIG); 695 695 + config = msm_dp_read_link(catalog, REG_PSR_CONFIG); 696 696 config |= PSR1_SUPPORTED; 697 697 - dp_write_link(catalog, REG_PSR_CONFIG, config); 697 697 + msm_dp_write_link(catalog, REG_PSR_CONFIG, config); 698 698 699 699 - dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); 700 700 - dp_catalog_enable_sdp(catalog); 699 699 + msm_dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); 700 700 + msm_dp_catalog_enable_sdp(catalog); 701 701 } 702 702 703 703 - void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter) 703 703 + void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bool enter) 704 704 { 705 705 - struct dp_catalog_private *catalog = container_of(dp_catalog, 706 706 - struct dp_catalog_private, dp_catalog); 705 705 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 706 706 + struct msm_dp_catalog_private, msm_dp_catalog); 707 707 u32 cmd; 708 708 709 709 - cmd = dp_read_link(catalog, REG_PSR_CMD); 709 709 + cmd = msm_dp_read_link(catalog, REG_PSR_CMD); 710 710 711 711 cmd &= ~(PSR_ENTER | PSR_EXIT); 712 712 ··· 715 715 else 716 716 cmd |= PSR_EXIT; 717 717 718 718 - dp_catalog_enable_sdp(catalog); 719 719 - dp_write_link(catalog, REG_PSR_CMD, cmd); 718 718 + msm_dp_catalog_enable_sdp(catalog); 719 719 + msm_dp_write_link(catalog, REG_PSR_CMD, cmd); 720 720 } 721 721 722 722 - u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog) 722 722 + u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog) 723 723 { 724 724 - struct dp_catalog_private *catalog = container_of(dp_catalog, 725 725 - struct dp_catalog_private, dp_catalog); 724 724 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 725 725 + struct msm_dp_catalog_private, msm_dp_catalog); 726 726 u32 status; 727 727 728 728 - status = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); 728 728 + status = msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); 729 729 drm_dbg_dp(catalog->drm_dev, "aux status: %#x\n", status); 730 730 status >>= DP_DP_HPD_STATE_STATUS_BITS_SHIFT; 731 731 status &= DP_DP_HPD_STATE_STATUS_BITS_MASK; ··· 733 733 return status; 734 734 } 735 735 736 736 - u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog) 736 736 + u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catalog) 737 737 { 738 738 - struct dp_catalog_private *catalog = container_of(dp_catalog, 739 739 - struct dp_catalog_private, dp_catalog); 738 738 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 739 739 + struct msm_dp_catalog_private, msm_dp_catalog); 740 740 int isr, mask; 741 741 742 742 - isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); 743 743 - dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, 742 742 + isr = msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS); 743 743 + msm_dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK, 744 744 (isr & DP_DP_HPD_INT_MASK)); 745 745 - mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); 745 745 + mask = msm_dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK); 746 746 747 747 /* 748 748 * We only want to return interrupts that are unmasked to the caller. ··· 754 754 return isr & (mask | ~DP_DP_HPD_INT_MASK); 755 755 } 756 756 757 757 - u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog) 757 757 + u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *msm_dp_catalog) 758 758 { 759 759 - struct dp_catalog_private *catalog = container_of(dp_catalog, 760 760 - struct dp_catalog_private, dp_catalog); 759 759 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 760 760 + struct msm_dp_catalog_private, msm_dp_catalog); 761 761 u32 intr, intr_ack; 762 762 763 763 - intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4); 763 763 + intr = msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS4); 764 764 intr_ack = (intr & DP_INTERRUPT_STATUS4) 765 765 << DP_INTERRUPT_STATUS_ACK_SHIFT; 766 766 - dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack); 766 766 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack); 767 767 768 768 return intr; 769 769 } 770 770 771 771 - int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog) 771 771 + int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalog) 772 772 { 773 773 - struct dp_catalog_private *catalog = container_of(dp_catalog, 774 774 - struct dp_catalog_private, dp_catalog); 773 773 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 774 774 + struct msm_dp_catalog_private, msm_dp_catalog); 775 775 u32 intr, intr_ack; 776 776 777 777 - intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS2); 777 777 + intr = msm_dp_read_ahb(catalog, REG_DP_INTR_STATUS2); 778 778 intr &= ~DP_INTERRUPT_STATUS2_MASK; 779 779 intr_ack = (intr & DP_INTERRUPT_STATUS2) 780 780 << DP_INTERRUPT_STATUS_ACK_SHIFT; 781 781 - dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 781 781 + msm_dp_write_ahb(catalog, REG_DP_INTR_STATUS2, 782 782 intr_ack | DP_INTERRUPT_STATUS2_MASK); 783 783 784 784 return intr; 785 785 } 786 786 787 787 - void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) 787 787 + void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog) 788 788 { 789 789 - struct dp_catalog_private *catalog = container_of(dp_catalog, 790 790 - struct dp_catalog_private, dp_catalog); 789 789 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 790 790 + struct msm_dp_catalog_private, msm_dp_catalog); 791 791 792 792 - dp_write_ahb(catalog, REG_DP_PHY_CTRL, 792 792 + msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, 793 793 DP_PHY_CTRL_SW_RESET | DP_PHY_CTRL_SW_RESET_PLL); 794 794 usleep_range(1000, 1100); /* h/w recommended delay */ 795 795 - dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); 795 795 + msm_dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); 796 796 } 797 797 798 798 - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, 798 798 + void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_catalog, 799 799 u32 pattern) 800 800 { 801 801 - struct dp_catalog_private *catalog = container_of(dp_catalog, 802 802 - struct dp_catalog_private, dp_catalog); 801 801 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 802 802 + struct msm_dp_catalog_private, msm_dp_catalog); 803 803 u32 value = 0x0; 804 804 805 805 /* Make sure to clear the current pattern before starting a new one */ 806 806 - dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); 806 806 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 0x0); 807 807 808 808 drm_dbg_dp(catalog->drm_dev, "pattern: %#x\n", pattern); 809 809 switch (pattern) { 810 810 case DP_PHY_TEST_PATTERN_D10_2: 811 811 - dp_write_link(catalog, REG_DP_STATE_CTRL, 811 811 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 812 812 DP_STATE_CTRL_LINK_TRAINING_PATTERN1); 813 813 break; 814 814 case DP_PHY_TEST_PATTERN_ERROR_COUNT: 815 815 value &= ~(1 << 16); 816 816 - dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 816 816 + msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 817 817 value); 818 818 value |= SCRAMBLER_RESET_COUNT_VALUE; 819 819 - dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 819 819 + msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 820 820 value); 821 821 - dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, 821 821 + msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, 822 822 DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); 823 823 - dp_write_link(catalog, REG_DP_STATE_CTRL, 823 823 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 824 824 DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); 825 825 break; 826 826 case DP_PHY_TEST_PATTERN_PRBS7: 827 827 - dp_write_link(catalog, REG_DP_STATE_CTRL, 827 827 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 828 828 DP_STATE_CTRL_LINK_PRBS7); 829 829 break; 830 830 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 831 831 - dp_write_link(catalog, REG_DP_STATE_CTRL, 831 831 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 832 832 DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); 833 833 /* 00111110000011111000001111100000 */ 834 834 - dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 834 834 + msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, 835 835 0x3E0F83E0); 836 836 /* 00001111100000111110000011111000 */ 837 837 - dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 837 837 + msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, 838 838 0x0F83E0F8); 839 839 /* 1111100000111110 */ 840 840 - dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 840 840 + msm_dp_write_link(catalog, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, 841 841 0x0000F83E); 842 842 break; 843 843 case DP_PHY_TEST_PATTERN_CP2520: 844 844 - value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 844 844 + value = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 845 845 value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; 846 846 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); 846 846 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); 847 847 848 848 value = DP_HBR2_ERM_PATTERN; 849 849 - dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 849 849 + msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 850 850 value); 851 851 value |= SCRAMBLER_RESET_COUNT_VALUE; 852 852 - dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 852 852 + msm_dp_write_link(catalog, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, 853 853 value); 854 854 - dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, 854 854 + msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, 855 855 DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); 856 856 - dp_write_link(catalog, REG_DP_STATE_CTRL, 856 856 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 857 857 DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); 858 858 - value = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 858 858 + value = msm_dp_read_link(catalog, REG_DP_MAINLINK_CTRL); 859 859 value |= DP_MAINLINK_CTRL_ENABLE; 860 860 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); 860 860 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, value); 861 861 break; 862 862 case DP_PHY_TEST_PATTERN_SEL_MASK: 863 863 - dp_write_link(catalog, REG_DP_MAINLINK_CTRL, 863 863 + msm_dp_write_link(catalog, REG_DP_MAINLINK_CTRL, 864 864 DP_MAINLINK_CTRL_ENABLE); 865 865 - dp_write_link(catalog, REG_DP_STATE_CTRL, 865 865 + msm_dp_write_link(catalog, REG_DP_STATE_CTRL, 866 866 DP_STATE_CTRL_LINK_TRAINING_PATTERN4); 867 867 break; 868 868 default: ··· 872 872 } 873 873 } 874 874 875 875 - u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog) 875 875 + u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_catalog) 876 876 { 877 877 - struct dp_catalog_private *catalog = container_of(dp_catalog, 878 878 - struct dp_catalog_private, dp_catalog); 877 877 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 878 878 + struct msm_dp_catalog_private, msm_dp_catalog); 879 879 880 880 - return dp_read_link(catalog, REG_DP_MAINLINK_READY); 880 880 + return msm_dp_read_link(catalog, REG_DP_MAINLINK_READY); 881 881 } 882 882 883 883 /* panel related catalog functions */ 884 884 - int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total, 885 885 - u32 sync_start, u32 width_blanking, u32 dp_active) 884 884 + int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32 total, 885 885 + u32 sync_start, u32 width_blanking, u32 msm_dp_active) 886 886 { 887 887 - struct dp_catalog_private *catalog = container_of(dp_catalog, 888 888 - struct dp_catalog_private, dp_catalog); 887 887 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 888 888 + struct msm_dp_catalog_private, msm_dp_catalog); 889 889 u32 reg; 890 890 891 891 - dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); 892 892 - dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); 893 893 - dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); 894 894 - dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_active); 891 891 + msm_dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total); 892 892 + msm_dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); 893 893 + msm_dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking); 894 894 + msm_dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, msm_dp_active); 895 895 896 896 - reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); 896 896 + reg = msm_dp_read_p0(catalog, MMSS_DP_INTF_CONFIG); 897 897 898 898 - if (dp_catalog->wide_bus_en) 898 898 + if (msm_dp_catalog->wide_bus_en) 899 899 reg |= DP_INTF_CONFIG_DATABUS_WIDEN; 900 900 else 901 901 reg &= ~DP_INTF_CONFIG_DATABUS_WIDEN; 902 902 903 903 904 904 - DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", dp_catalog->wide_bus_en, reg); 904 904 + DRM_DEBUG_DP("wide_bus_en=%d reg=%#x\n", msm_dp_catalog->wide_bus_en, reg); 905 905 906 906 - dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); 906 906 + msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, reg); 907 907 return 0; 908 908 } 909 909 910 910 - static void dp_catalog_panel_send_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) 910 910 + static void msm_dp_catalog_panel_send_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp) 911 911 { 912 912 - struct dp_catalog_private *catalog; 912 912 + struct msm_dp_catalog_private *catalog; 913 913 u32 header[2]; 914 914 u32 val; 915 915 int i; 916 916 917 917 - catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); 917 917 + catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); 918 918 919 919 - dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); 919 919 + msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); 920 920 921 921 - dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); 922 922 - dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); 921 921 + msm_dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); 922 922 + msm_dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); 923 923 924 924 for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { 925 925 val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | 926 926 (vsc_sdp->db[i + 3] << 24)); 927 927 - dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); 927 927 + msm_dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); 928 928 } 929 929 } 930 930 931 931 - static void dp_catalog_panel_update_sdp(struct dp_catalog *dp_catalog) 931 931 + static void msm_dp_catalog_panel_update_sdp(struct msm_dp_catalog *msm_dp_catalog) 932 932 { 933 933 - struct dp_catalog_private *catalog; 933 933 + struct msm_dp_catalog_private *catalog; 934 934 u32 hw_revision; 935 935 936 936 - catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); 936 936 + catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); 937 937 938 938 - hw_revision = dp_catalog_hw_revision(dp_catalog); 938 938 + hw_revision = msm_dp_catalog_hw_revision(msm_dp_catalog); 939 939 if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >= DP_HW_VERSION_1_0) { 940 940 - dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); 941 941 - dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); 940 940 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); 941 941 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); 942 942 } 943 943 } 944 944 945 945 - void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) 945 945 + void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp) 946 946 { 947 947 - struct dp_catalog_private *catalog; 947 947 + struct msm_dp_catalog_private *catalog; 948 948 u32 cfg, cfg2, misc; 949 949 950 950 - catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); 950 950 + catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); 951 951 952 952 - cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); 953 953 - cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); 954 954 - misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); 952 952 + cfg = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); 953 953 + cfg2 = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); 954 954 + misc = msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); 955 955 956 956 cfg |= GEN0_SDP_EN; 957 957 - dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); 957 957 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); 958 958 959 959 cfg2 |= GENERIC0_SDPSIZE_VALID; 960 960 - dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); 960 960 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); 961 961 962 962 - dp_catalog_panel_send_vsc_sdp(dp_catalog, vsc_sdp); 962 962 + msm_dp_catalog_panel_send_vsc_sdp(msm_dp_catalog, vsc_sdp); 963 963 964 964 /* indicates presence of VSC (BIT(6) of MISC1) */ 965 965 misc |= DP_MISC1_VSC_SDP; ··· 967 967 drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=1\n"); 968 968 969 969 pr_debug("misc settings = 0x%x\n", misc); 970 970 - dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); 970 970 + msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); 971 971 972 972 - dp_catalog_panel_update_sdp(dp_catalog); 972 972 + msm_dp_catalog_panel_update_sdp(msm_dp_catalog); 973 973 } 974 974 975 975 - void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog) 975 975 + void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog) 976 976 { 977 977 - struct dp_catalog_private *catalog; 977 977 + struct msm_dp_catalog_private *catalog; 978 978 u32 cfg, cfg2, misc; 979 979 980 980 - catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); 980 980 + catalog = container_of(msm_dp_catalog, struct msm_dp_catalog_private, msm_dp_catalog); 981 981 982 982 - cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); 983 983 - cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); 984 984 - misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); 982 982 + cfg = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); 983 983 + cfg2 = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); 984 984 + misc = msm_dp_read_link(catalog, REG_DP_MISC1_MISC0); 985 985 986 986 cfg &= ~GEN0_SDP_EN; 987 987 - dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); 987 987 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); 988 988 989 989 cfg2 &= ~GENERIC0_SDPSIZE_VALID; 990 990 - dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); 990 990 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); 991 991 992 992 /* switch back to MSA */ 993 993 misc &= ~DP_MISC1_VSC_SDP; ··· 995 995 drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=0\n"); 996 996 997 997 pr_debug("misc settings = 0x%x\n", misc); 998 998 - dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); 998 998 + msm_dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); 999 999 1000 1000 - dp_catalog_panel_update_sdp(dp_catalog); 1000 1000 + msm_dp_catalog_panel_update_sdp(msm_dp_catalog); 1001 1001 } 1002 1002 1003 1003 - void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog, 1003 1003 + void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, 1004 1004 struct drm_display_mode *drm_mode) 1005 1005 { 1006 1006 - struct dp_catalog_private *catalog = container_of(dp_catalog, 1007 1007 - struct dp_catalog_private, dp_catalog); 1006 1006 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 1007 1007 + struct msm_dp_catalog_private, msm_dp_catalog); 1008 1008 u32 hsync_period, vsync_period; 1009 1009 u32 display_v_start, display_v_end; 1010 1010 u32 hsync_start_x, hsync_end_x; ··· 1036 1036 display_hctl = (hsync_end_x << 16) | hsync_start_x; 1037 1037 1038 1038 1039 1039 - dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0); 1040 1040 - dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); 1041 1041 - dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * 1039 1039 + msm_dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0x0); 1040 1040 + msm_dp_write_p0(catalog, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); 1041 1041 + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * 1042 1042 hsync_period); 1043 1043 - dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * 1043 1043 + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * 1044 1044 hsync_period); 1045 1045 - dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); 1046 1046 - dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); 1047 1047 - dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); 1048 1048 - dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); 1049 1049 - dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); 1050 1050 - dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); 1051 1051 - dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); 1052 1052 - dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); 1053 1053 - dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); 1054 1054 - dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); 1055 1055 - dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); 1056 1056 - dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); 1057 1057 - dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); 1045 1045 + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); 1046 1046 + msm_dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); 1047 1047 + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); 1048 1048 + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_HCTL, 0); 1049 1049 + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); 1050 1050 + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); 1051 1051 + msm_dp_write_p0(catalog, MMSS_INTF_DISPLAY_V_START_F1, 0); 1052 1052 + msm_dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); 1053 1053 + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); 1054 1054 + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); 1055 1055 + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); 1056 1056 + msm_dp_write_p0(catalog, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); 1057 1057 + msm_dp_write_p0(catalog, MMSS_DP_INTF_POLARITY_CTL, 0); 1058 1058 1059 1059 - dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 1059 1059 + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 1060 1060 DP_TPG_CHECKERED_RECT_PATTERN); 1061 1061 - dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, 1061 1061 + msm_dp_write_p0(catalog, MMSS_DP_TPG_VIDEO_CONFIG, 1062 1062 DP_TPG_VIDEO_CONFIG_BPP_8BIT | 1063 1063 DP_TPG_VIDEO_CONFIG_RGB); 1064 1064 - dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 1064 1064 + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 1065 1065 DP_BIST_ENABLE_DPBIST_EN); 1066 1066 - dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 1066 1066 + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 1067 1067 DP_TIMING_ENGINE_EN_EN); 1068 1068 drm_dbg_dp(catalog->drm_dev, "%s: enabled tpg\n", __func__); 1069 1069 } 1070 1070 1071 1071 - void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog) 1071 1071 + void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog) 1072 1072 { 1073 1073 - struct dp_catalog_private *catalog = container_of(dp_catalog, 1074 1074 - struct dp_catalog_private, dp_catalog); 1073 1073 + struct msm_dp_catalog_private *catalog = container_of(msm_dp_catalog, 1074 1074 + struct msm_dp_catalog_private, msm_dp_catalog); 1075 1075 1076 1076 - dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); 1077 1077 - dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); 1078 1078 - dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); 1076 1076 + msm_dp_write_p0(catalog, MMSS_DP_TPG_MAIN_CONTROL, 0x0); 1077 1077 + msm_dp_write_p0(catalog, MMSS_DP_BIST_ENABLE, 0x0); 1078 1078 + msm_dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); 1079 1079 } 1080 1080 1081 1081 - static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) 1081 1081 + static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_t *len) 1082 1082 { 1083 1083 struct resource *res; 1084 1084 void __iomem *base; ··· 1090 1090 return base; 1091 1091 } 1092 1092 1093 1093 - static int dp_catalog_get_io(struct dp_catalog_private *catalog) 1093 1093 + static int msm_dp_catalog_get_io(struct msm_dp_catalog_private *catalog) 1094 1094 { 1095 1095 struct platform_device *pdev = to_platform_device(catalog->dev); 1096 1096 struct dss_io_data *dss = &catalog->io; 1097 1097 1098 1098 - dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); 1098 1098 + dss->ahb.base = msm_dp_ioremap(pdev, 0, &dss->ahb.len); 1099 1099 if (IS_ERR(dss->ahb.base)) 1100 1100 return PTR_ERR(dss->ahb.base); 1101 1101 1102 1102 - dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); 1102 1102 + dss->aux.base = msm_dp_ioremap(pdev, 1, &dss->aux.len); 1103 1103 if (IS_ERR(dss->aux.base)) { 1104 1104 /* 1105 1105 * The initial binding had a single reg, but in order to 1106 1106 * support variation in the sub-region sizes this was split. 1107 1107 - * dp_ioremap() will fail with -EINVAL here if only a single 1107 1107 + * msm_dp_ioremap() will fail with -EINVAL here if only a single 1108 1108 * reg is specified, so fill in the sub-region offsets and 1109 1109 * lengths based on this single region. 1110 1110 */ ··· 1126 1126 return PTR_ERR(dss->aux.base); 1127 1127 } 1128 1128 } else { 1129 1129 - dss->link.base = dp_ioremap(pdev, 2, &dss->link.len); 1129 1129 + dss->link.base = msm_dp_ioremap(pdev, 2, &dss->link.len); 1130 1130 if (IS_ERR(dss->link.base)) { 1131 1131 DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); 1132 1132 return PTR_ERR(dss->link.base); 1133 1133 } 1134 1134 1135 1135 - dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len); 1135 1135 + dss->p0.base = msm_dp_ioremap(pdev, 3, &dss->p0.len); 1136 1136 if (IS_ERR(dss->p0.base)) { 1137 1137 DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); 1138 1138 return PTR_ERR(dss->p0.base); ··· 1142 1142 return 0; 1143 1143 } 1144 1144 1145 1145 - struct dp_catalog *dp_catalog_get(struct device *dev) 1145 1145 + struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev) 1146 1146 { 1147 1147 - struct dp_catalog_private *catalog; 1147 1147 + struct msm_dp_catalog_private *catalog; 1148 1148 int ret; 1149 1149 1150 1150 catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL); ··· 1153 1153 1154 1154 catalog->dev = dev; 1155 1155 1156 1156 - ret = dp_catalog_get_io(catalog); 1156 1156 + ret = msm_dp_catalog_get_io(catalog); 1157 1157 if (ret) 1158 1158 return ERR_PTR(ret); 1159 1159 1160 1160 - return &catalog->dp_catalog; 1160 1160 + return &catalog->msm_dp_catalog; 1161 1161 } 1162 1162 1163 1163 - u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog, 1164 1164 - enum dp_catalog_audio_sdp_type sdp, 1165 1165 - enum dp_catalog_audio_header_type header) 1163 1163 + u32 msm_dp_catalog_audio_get_header(struct msm_dp_catalog *msm_dp_catalog, 1164 1164 + enum msm_dp_catalog_audio_sdp_type sdp, 1165 1165 + enum msm_dp_catalog_audio_header_type header) 1166 1166 { 1167 1167 - struct dp_catalog_private *catalog; 1167 1167 + struct msm_dp_catalog_private *catalog; 1168 1168 u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX]; 1169 1169 1170 1170 - catalog = container_of(dp_catalog, 1171 1171 - struct dp_catalog_private, dp_catalog); 1170 1170 + catalog = container_of(msm_dp_catalog, 1171 1171 + struct msm_dp_catalog_private, msm_dp_catalog); 1172 1172 1173 1173 sdp_map = catalog->audio_map; 1174 1174 1175 1175 - return dp_read_link(catalog, sdp_map[sdp][header]); 1175 1175 + return msm_dp_read_link(catalog, sdp_map[sdp][header]); 1176 1176 } 1177 1177 1178 1178 - void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog, 1179 1179 - enum dp_catalog_audio_sdp_type sdp, 1180 1180 - enum dp_catalog_audio_header_type header, 1178 1178 + void msm_dp_catalog_audio_set_header(struct msm_dp_catalog *msm_dp_catalog, 1179 1179 + enum msm_dp_catalog_audio_sdp_type sdp, 1180 1180 + enum msm_dp_catalog_audio_header_type header, 1181 1181 u32 data) 1182 1182 { 1183 1183 - struct dp_catalog_private *catalog; 1183 1183 + struct msm_dp_catalog_private *catalog; 1184 1184 u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX]; 1185 1185 1186 1186 - if (!dp_catalog) 1186 1186 + if (!msm_dp_catalog) 1187 1187 return; 1188 1188 1189 1189 - catalog = container_of(dp_catalog, 1190 1190 - struct dp_catalog_private, dp_catalog); 1189 1189 + catalog = container_of(msm_dp_catalog, 1190 1190 + struct msm_dp_catalog_private, msm_dp_catalog); 1191 1191 1192 1192 sdp_map = catalog->audio_map; 1193 1193 1194 1194 - dp_write_link(catalog, sdp_map[sdp][header], data); 1194 1194 + msm_dp_write_link(catalog, sdp_map[sdp][header], data); 1195 1195 } 1196 1196 1197 1197 - void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog, u32 select) 1197 1197 + void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *msm_dp_catalog, u32 select) 1198 1198 { 1199 1199 - struct dp_catalog_private *catalog; 1199 1199 + struct msm_dp_catalog_private *catalog; 1200 1200 u32 acr_ctrl; 1201 1201 1202 1202 - if (!dp_catalog) 1202 1202 + if (!msm_dp_catalog) 1203 1203 return; 1204 1204 1205 1205 - catalog = container_of(dp_catalog, 1206 1206 - struct dp_catalog_private, dp_catalog); 1205 1205 + catalog = container_of(msm_dp_catalog, 1206 1206 + struct msm_dp_catalog_private, msm_dp_catalog); 1207 1207 1208 1208 acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14); 1209 1209 1210 1210 drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n", 1211 1211 select, acr_ctrl); 1212 1212 1213 1213 - dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); 1213 1213 + msm_dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl); 1214 1214 } 1215 1215 1216 1216 - void dp_catalog_audio_enable(struct dp_catalog *dp_catalog, bool enable) 1216 1216 + void msm_dp_catalog_audio_enable(struct msm_dp_catalog *msm_dp_catalog, bool enable) 1217 1217 { 1218 1218 - struct dp_catalog_private *catalog; 1218 1218 + struct msm_dp_catalog_private *catalog; 1219 1219 u32 audio_ctrl; 1220 1220 1221 1221 - if (!dp_catalog) 1221 1221 + if (!msm_dp_catalog) 1222 1222 return; 1223 1223 1224 1224 - catalog = container_of(dp_catalog, 1225 1225 - struct dp_catalog_private, dp_catalog); 1224 1224 + catalog = container_of(msm_dp_catalog, 1225 1225 + struct msm_dp_catalog_private, msm_dp_catalog); 1226 1226 1227 1227 - audio_ctrl = dp_read_link(catalog, MMSS_DP_AUDIO_CFG); 1227 1227 + audio_ctrl = msm_dp_read_link(catalog, MMSS_DP_AUDIO_CFG); 1228 1228 1229 1229 if (enable) 1230 1230 audio_ctrl |= BIT(0); ··· 1233 1233 1234 1234 drm_dbg_dp(catalog->drm_dev, "dp_audio_cfg = 0x%x\n", audio_ctrl); 1235 1235 1236 1236 - dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); 1236 1236 + msm_dp_write_link(catalog, MMSS_DP_AUDIO_CFG, audio_ctrl); 1237 1237 /* make sure audio engine is disabled */ 1238 1238 wmb(); 1239 1239 } 1240 1240 1241 1241 - void dp_catalog_audio_config_sdp(struct dp_catalog *dp_catalog) 1241 1241 + void msm_dp_catalog_audio_config_sdp(struct msm_dp_catalog *msm_dp_catalog) 1242 1242 { 1243 1243 - struct dp_catalog_private *catalog; 1243 1243 + struct msm_dp_catalog_private *catalog; 1244 1244 u32 sdp_cfg = 0; 1245 1245 u32 sdp_cfg2 = 0; 1246 1246 1247 1247 - if (!dp_catalog) 1247 1247 + if (!msm_dp_catalog) 1248 1248 return; 1249 1249 1250 1250 - catalog = container_of(dp_catalog, 1251 1251 - struct dp_catalog_private, dp_catalog); 1250 1250 + catalog = container_of(msm_dp_catalog, 1251 1251 + struct msm_dp_catalog_private, msm_dp_catalog); 1252 1252 1253 1253 - sdp_cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); 1253 1253 + sdp_cfg = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG); 1254 1254 /* AUDIO_TIMESTAMP_SDP_EN */ 1255 1255 sdp_cfg |= BIT(1); 1256 1256 /* AUDIO_STREAM_SDP_EN */ ··· 1264 1264 1265 1265 drm_dbg_dp(catalog->drm_dev, "sdp_cfg = 0x%x\n", sdp_cfg); 1266 1266 1267 1267 - dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg); 1267 1267 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG, sdp_cfg); 1268 1268 1269 1269 - sdp_cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); 1269 1269 + sdp_cfg2 = msm_dp_read_link(catalog, MMSS_DP_SDP_CFG2); 1270 1270 /* IFRM_REGSRC -> Do not use reg values */ 1271 1271 sdp_cfg2 &= ~BIT(0); 1272 1272 /* AUDIO_STREAM_HB3_REGSRC-> Do not use reg values */ ··· 1274 1274 1275 1275 drm_dbg_dp(catalog->drm_dev, "sdp_cfg2 = 0x%x\n", sdp_cfg2); 1276 1276 1277 1277 - dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); 1277 1277 + msm_dp_write_link(catalog, MMSS_DP_SDP_CFG2, sdp_cfg2); 1278 1278 } 1279 1279 1280 1280 - void dp_catalog_audio_init(struct dp_catalog *dp_catalog) 1280 1280 + void msm_dp_catalog_audio_init(struct msm_dp_catalog *msm_dp_catalog) 1281 1281 { 1282 1282 - struct dp_catalog_private *catalog; 1282 1282 + struct msm_dp_catalog_private *catalog; 1283 1283 1284 1284 static u32 sdp_map[][DP_AUDIO_SDP_HEADER_MAX] = { 1285 1285 { ··· 1309 1309 }, 1310 1310 }; 1311 1311 1312 1312 - if (!dp_catalog) 1312 1312 + if (!msm_dp_catalog) 1313 1313 return; 1314 1314 1315 1315 - catalog = container_of(dp_catalog, 1316 1316 - struct dp_catalog_private, dp_catalog); 1315 1315 + catalog = container_of(msm_dp_catalog, 1316 1316 + struct msm_dp_catalog_private, msm_dp_catalog); 1317 1317 1318 1318 catalog->audio_map = sdp_map; 1319 1319 } 1320 1320 1321 1321 - void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog, u32 safe_to_exit_level) 1321 1321 + void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *msm_dp_catalog, u32 safe_to_exit_level) 1322 1322 { 1323 1323 - struct dp_catalog_private *catalog; 1323 1323 + struct msm_dp_catalog_private *catalog; 1324 1324 u32 mainlink_levels; 1325 1325 1326 1326 - if (!dp_catalog) 1326 1326 + if (!msm_dp_catalog) 1327 1327 return; 1328 1328 1329 1329 - catalog = container_of(dp_catalog, 1330 1330 - struct dp_catalog_private, dp_catalog); 1329 1329 + catalog = container_of(msm_dp_catalog, 1330 1330 + struct msm_dp_catalog_private, msm_dp_catalog); 1331 1331 1332 1332 - mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); 1332 1332 + mainlink_levels = msm_dp_read_link(catalog, REG_DP_MAINLINK_LEVELS); 1333 1333 mainlink_levels &= 0xFE0; 1334 1334 mainlink_levels |= safe_to_exit_level; 1335 1335 ··· 1337 1337 "mainlink_level = 0x%x, safe_to_exit_level = 0x%x\n", 1338 1338 mainlink_levels, safe_to_exit_level); 1339 1339 1340 1340 - dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); 1340 1340 + msm_dp_write_link(catalog, REG_DP_MAINLINK_LEVELS, mainlink_levels); 1341 1341 }

+59 -59

drivers/gpu/drm/msm/dp/dp_catalog.h

reviewed

··· 31 31 #define DP_HW_VERSION_1_0 0x10000000 32 32 #define DP_HW_VERSION_1_2 0x10020000 33 33 34 34 - enum dp_catalog_audio_sdp_type { 34 34 + enum msm_dp_catalog_audio_sdp_type { 35 35 DP_AUDIO_SDP_STREAM, 36 36 DP_AUDIO_SDP_TIMESTAMP, 37 37 DP_AUDIO_SDP_INFOFRAME, ··· 40 40 DP_AUDIO_SDP_MAX, 41 41 }; 42 42 43 43 - enum dp_catalog_audio_header_type { 43 43 + enum msm_dp_catalog_audio_header_type { 44 44 DP_AUDIO_SDP_HEADER_1, 45 45 DP_AUDIO_SDP_HEADER_2, 46 46 DP_AUDIO_SDP_HEADER_3, 47 47 DP_AUDIO_SDP_HEADER_MAX, 48 48 }; 49 49 50 50 - struct dp_catalog { 50 50 + struct msm_dp_catalog { 51 51 bool wide_bus_en; 52 52 }; 53 53 54 54 /* Debug module */ 55 55 - void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state); 55 55 + void msm_dp_catalog_snapshot(struct msm_dp_catalog *msm_dp_catalog, struct msm_disp_state *disp_state); 56 56 57 57 /* AUX APIs */ 58 58 - u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog); 59 59 - int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data); 60 60 - int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data); 61 61 - int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read); 62 62 - int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog); 63 63 - void dp_catalog_aux_reset(struct dp_catalog *dp_catalog); 64 64 - void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable); 65 65 - int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog, 58 58 + u32 msm_dp_catalog_aux_read_data(struct msm_dp_catalog *msm_dp_catalog); 59 59 + int msm_dp_catalog_aux_write_data(struct msm_dp_catalog *msm_dp_catalog, u32 data); 60 60 + int msm_dp_catalog_aux_write_trans(struct msm_dp_catalog *msm_dp_catalog, u32 data); 61 61 + int msm_dp_catalog_aux_clear_trans(struct msm_dp_catalog *msm_dp_catalog, bool read); 62 62 + int msm_dp_catalog_aux_clear_hw_interrupts(struct msm_dp_catalog *msm_dp_catalog); 63 63 + void msm_dp_catalog_aux_reset(struct msm_dp_catalog *msm_dp_catalog); 64 64 + void msm_dp_catalog_aux_enable(struct msm_dp_catalog *msm_dp_catalog, bool enable); 65 65 + int msm_dp_catalog_aux_wait_for_hpd_connect_state(struct msm_dp_catalog *msm_dp_catalog, 66 66 unsigned long wait_us); 67 67 - u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); 67 67 + u32 msm_dp_catalog_aux_get_irq(struct msm_dp_catalog *msm_dp_catalog); 68 68 69 69 /* DP Controller APIs */ 70 70 - void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state); 71 71 - void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); 72 72 - void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); 73 73 - void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); 74 74 - void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable); 75 75 - void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog); 76 76 - void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); 77 77 - void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, 70 70 + void msm_dp_catalog_ctrl_state_ctrl(struct msm_dp_catalog *msm_dp_catalog, u32 state); 71 71 + void msm_dp_catalog_ctrl_config_ctrl(struct msm_dp_catalog *msm_dp_catalog, u32 config); 72 72 + void msm_dp_catalog_ctrl_lane_mapping(struct msm_dp_catalog *msm_dp_catalog); 73 73 + void msm_dp_catalog_ctrl_mainlink_ctrl(struct msm_dp_catalog *msm_dp_catalog, bool enable); 74 74 + void msm_dp_catalog_ctrl_psr_mainlink_enable(struct msm_dp_catalog *msm_dp_catalog, bool enable); 75 75 + void msm_dp_catalog_setup_peripheral_flush(struct msm_dp_catalog *msm_dp_catalog); 76 76 + void msm_dp_catalog_ctrl_config_misc(struct msm_dp_catalog *msm_dp_catalog, u32 cc, u32 tb); 77 77 + void msm_dp_catalog_ctrl_config_msa(struct msm_dp_catalog *msm_dp_catalog, u32 rate, 78 78 u32 stream_rate_khz, bool is_ycbcr_420); 79 79 - int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern); 80 80 - u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog); 81 81 - void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); 82 82 - bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); 83 83 - void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); 84 84 - void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog, 79 79 + int msm_dp_catalog_ctrl_set_pattern_state_bit(struct msm_dp_catalog *msm_dp_catalog, u32 pattern); 80 80 + u32 msm_dp_catalog_hw_revision(const struct msm_dp_catalog *msm_dp_catalog); 81 81 + void msm_dp_catalog_ctrl_reset(struct msm_dp_catalog *msm_dp_catalog); 82 82 + bool msm_dp_catalog_ctrl_mainlink_ready(struct msm_dp_catalog *msm_dp_catalog); 83 83 + void msm_dp_catalog_ctrl_enable_irq(struct msm_dp_catalog *msm_dp_catalog, bool enable); 84 84 + void msm_dp_catalog_hpd_config_intr(struct msm_dp_catalog *msm_dp_catalog, 85 85 u32 intr_mask, bool en); 86 86 - void dp_catalog_ctrl_hpd_enable(struct dp_catalog *dp_catalog); 87 87 - void dp_catalog_ctrl_hpd_disable(struct dp_catalog *dp_catalog); 88 88 - void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog); 89 89 - void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter); 90 90 - u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog); 91 91 - u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); 92 92 - void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); 93 93 - int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); 94 94 - u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog); 95 95 - void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog, 96 96 - u32 dp_tu, u32 valid_boundary, 86 86 + void msm_dp_catalog_ctrl_hpd_enable(struct msm_dp_catalog *msm_dp_catalog); 87 87 + void msm_dp_catalog_ctrl_hpd_disable(struct msm_dp_catalog *msm_dp_catalog); 88 88 + void msm_dp_catalog_ctrl_config_psr(struct msm_dp_catalog *msm_dp_catalog); 89 89 + void msm_dp_catalog_ctrl_set_psr(struct msm_dp_catalog *msm_dp_catalog, bool enter); 90 90 + u32 msm_dp_catalog_link_is_connected(struct msm_dp_catalog *msm_dp_catalog); 91 91 + u32 msm_dp_catalog_hpd_get_intr_status(struct msm_dp_catalog *msm_dp_catalog); 92 92 + void msm_dp_catalog_ctrl_phy_reset(struct msm_dp_catalog *msm_dp_catalog); 93 93 + int msm_dp_catalog_ctrl_get_interrupt(struct msm_dp_catalog *msm_dp_catalog); 94 94 + u32 msm_dp_catalog_ctrl_read_psr_interrupt_status(struct msm_dp_catalog *msm_dp_catalog); 95 95 + void msm_dp_catalog_ctrl_update_transfer_unit(struct msm_dp_catalog *msm_dp_catalog, 96 96 + u32 msm_dp_tu, u32 valid_boundary, 97 97 u32 valid_boundary2); 98 98 - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, 98 98 + void msm_dp_catalog_ctrl_send_phy_pattern(struct msm_dp_catalog *msm_dp_catalog, 99 99 u32 pattern); 100 100 - u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog); 100 100 + u32 msm_dp_catalog_ctrl_read_phy_pattern(struct msm_dp_catalog *msm_dp_catalog); 101 101 102 102 /* DP Panel APIs */ 103 103 - int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total, 104 104 - u32 sync_start, u32 width_blanking, u32 dp_active); 105 105 - void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp); 106 106 - void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog); 107 107 - void dp_catalog_dump_regs(struct dp_catalog *dp_catalog); 108 108 - void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog, 103 103 + int msm_dp_catalog_panel_timing_cfg(struct msm_dp_catalog *msm_dp_catalog, u32 total, 104 104 + u32 sync_start, u32 width_blanking, u32 msm_dp_active); 105 105 + void msm_dp_catalog_panel_enable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog, struct dp_sdp *vsc_sdp); 106 106 + void msm_dp_catalog_panel_disable_vsc_sdp(struct msm_dp_catalog *msm_dp_catalog); 107 107 + void msm_dp_catalog_dump_regs(struct msm_dp_catalog *msm_dp_catalog); 108 108 + void msm_dp_catalog_panel_tpg_enable(struct msm_dp_catalog *msm_dp_catalog, 109 109 struct drm_display_mode *drm_mode); 110 110 - void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog); 110 110 + void msm_dp_catalog_panel_tpg_disable(struct msm_dp_catalog *msm_dp_catalog); 111 111 112 112 - struct dp_catalog *dp_catalog_get(struct device *dev); 112 112 + struct msm_dp_catalog *msm_dp_catalog_get(struct device *dev); 113 113 114 114 /* DP Audio APIs */ 115 115 - u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog, 116 116 - enum dp_catalog_audio_sdp_type sdp, 117 117 - enum dp_catalog_audio_header_type header); 118 118 - void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog, 119 119 - enum dp_catalog_audio_sdp_type sdp, 120 120 - enum dp_catalog_audio_header_type header, 115 115 + u32 msm_dp_catalog_audio_get_header(struct msm_dp_catalog *msm_dp_catalog, 116 116 + enum msm_dp_catalog_audio_sdp_type sdp, 117 117 + enum msm_dp_catalog_audio_header_type header); 118 118 + void msm_dp_catalog_audio_set_header(struct msm_dp_catalog *msm_dp_catalog, 119 119 + enum msm_dp_catalog_audio_sdp_type sdp, 120 120 + enum msm_dp_catalog_audio_header_type header, 121 121 u32 data); 122 122 - void dp_catalog_audio_config_acr(struct dp_catalog *catalog, u32 select); 123 123 - void dp_catalog_audio_enable(struct dp_catalog *catalog, bool enable); 124 124 - void dp_catalog_audio_config_sdp(struct dp_catalog *catalog); 125 125 - void dp_catalog_audio_init(struct dp_catalog *catalog); 126 126 - void dp_catalog_audio_sfe_level(struct dp_catalog *catalog, u32 safe_to_exit_level); 122 122 + void msm_dp_catalog_audio_config_acr(struct msm_dp_catalog *catalog, u32 select); 123 123 + void msm_dp_catalog_audio_enable(struct msm_dp_catalog *catalog, bool enable); 124 124 + void msm_dp_catalog_audio_config_sdp(struct msm_dp_catalog *catalog); 125 125 + void msm_dp_catalog_audio_init(struct msm_dp_catalog *catalog); 126 126 + void msm_dp_catalog_audio_sfe_level(struct msm_dp_catalog *catalog, u32 safe_to_exit_level); 127 127 128 128 #endif /* _DP_CATALOG_H_ */

+241 -241

drivers/gpu/drm/msm/dp/dp_ctrl.c

reviewed

··· 40 40 DP_TRAINING_2, 41 41 }; 42 42 43 43 - struct dp_tu_calc_input { 43 43 + struct msm_dp_tu_calc_input { 44 44 u64 lclk; /* 162, 270, 540 and 810 */ 45 45 u64 pclk_khz; /* in KHz */ 46 46 u64 hactive; /* active h-width */ ··· 55 55 int num_of_dsc_slices; /* number of slices per line */ 56 56 }; 57 57 58 58 - struct dp_vc_tu_mapping_table { 58 58 + struct msm_dp_vc_tu_mapping_table { 59 59 u32 vic; 60 60 u8 lanes; 61 61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ ··· 69 69 u8 tu_size_minus1; 70 70 }; 71 71 72 72 - struct dp_ctrl_private { 73 73 - struct dp_ctrl dp_ctrl; 72 72 + struct msm_dp_ctrl_private { 73 73 + struct msm_dp_ctrl msm_dp_ctrl; 74 74 struct drm_device *drm_dev; 75 75 struct device *dev; 76 76 struct drm_dp_aux *aux; 77 77 - struct dp_panel *panel; 78 78 - struct dp_link *link; 79 79 - struct dp_catalog *catalog; 77 77 + struct msm_dp_panel *panel; 78 78 + struct msm_dp_link *link; 79 79 + struct msm_dp_catalog *catalog; 80 80 81 81 struct phy *phy; 82 82 ··· 99 99 bool stream_clks_on; 100 100 }; 101 101 102 102 - static int dp_aux_link_configure(struct drm_dp_aux *aux, 103 103 - struct dp_link_info *link) 102 102 + static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, 103 103 + struct msm_dp_link_info *link) 104 104 { 105 105 u8 values[2]; 106 106 int err; ··· 118 118 return 0; 119 119 } 120 120 121 121 - void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) 121 121 + void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) 122 122 { 123 123 - struct dp_ctrl_private *ctrl; 123 123 + struct msm_dp_ctrl_private *ctrl; 124 124 125 125 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 125 125 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 126 126 127 127 reinit_completion(&ctrl->idle_comp); 128 128 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 128 128 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); 129 129 130 130 if (!wait_for_completion_timeout(&ctrl->idle_comp, 131 131 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) ··· 134 134 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); 135 135 } 136 136 137 137 - static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) 137 137 + static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) 138 138 { 139 139 u32 config = 0, tbd; 140 140 const u8 *dpcd = ctrl->panel->dpcd; ··· 142 142 /* Default-> LSCLK DIV: 1/4 LCLK */ 143 143 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); 144 144 145 145 - if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) 145 145 + if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 146 146 config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ 147 147 148 148 /* Scrambler reset enable */ 149 149 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) 150 150 config |= DP_CONFIGURATION_CTRL_ASSR; 151 151 152 152 - tbd = dp_link_get_test_bits_depth(ctrl->link, 153 153 - ctrl->panel->dp_mode.bpp); 152 152 + tbd = msm_dp_link_get_test_bits_depth(ctrl->link, 153 153 + ctrl->panel->msm_dp_mode.bpp); 154 154 155 155 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; 156 156 ··· 170 170 if (ctrl->panel->psr_cap.version) 171 171 config |= DP_CONFIGURATION_CTRL_SEND_VSC; 172 172 173 173 - dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 173 173 + msm_dp_catalog_ctrl_config_ctrl(ctrl->catalog, config); 174 174 } 175 175 176 176 - static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) 176 176 + static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) 177 177 { 178 178 u32 cc, tb; 179 179 180 180 - dp_catalog_ctrl_lane_mapping(ctrl->catalog); 181 181 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 182 182 - dp_catalog_setup_peripheral_flush(ctrl->catalog); 180 180 + msm_dp_catalog_ctrl_lane_mapping(ctrl->catalog); 181 181 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 182 182 + msm_dp_catalog_setup_peripheral_flush(ctrl->catalog); 183 183 184 184 - dp_ctrl_config_ctrl(ctrl); 184 184 + msm_dp_ctrl_config_ctrl(ctrl); 185 185 186 186 - tb = dp_link_get_test_bits_depth(ctrl->link, 187 187 - ctrl->panel->dp_mode.bpp); 188 188 - cc = dp_link_get_colorimetry_config(ctrl->link); 189 189 - dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 190 190 - dp_panel_timing_cfg(ctrl->panel); 186 186 + tb = msm_dp_link_get_test_bits_depth(ctrl->link, 187 187 + ctrl->panel->msm_dp_mode.bpp); 188 188 + cc = msm_dp_link_get_colorimetry_config(ctrl->link); 189 189 + msm_dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb); 190 190 + msm_dp_panel_timing_cfg(ctrl->panel); 191 191 } 192 192 193 193 /* ··· 310 310 } 311 311 } 312 312 313 313 - static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, 313 313 + static void msm_dp_panel_update_tu_timings(struct msm_dp_tu_calc_input *in, 314 314 struct tu_algo_data *tu) 315 315 { 316 316 int nlanes = in->nlanes; ··· 622 622 } 623 623 } 624 624 625 625 - static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl, 626 626 - struct dp_tu_calc_input *in, 627 627 - struct dp_vc_tu_mapping_table *tu_table) 625 625 + static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl, 626 626 + struct msm_dp_tu_calc_input *in, 627 627 + struct msm_dp_vc_tu_mapping_table *tu_table) 628 628 { 629 629 struct tu_algo_data *tu; 630 630 int compare_result_1, compare_result_2; ··· 645 645 if (!tu) 646 646 return; 647 647 648 648 - dp_panel_update_tu_timings(in, tu); 648 648 + msm_dp_panel_update_tu_timings(in, tu); 649 649 650 650 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */ 651 651 ··· 956 956 kfree(tu); 957 957 } 958 958 959 959 - static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, 960 960 - struct dp_vc_tu_mapping_table *tu_table) 959 959 + static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl, 960 960 + struct msm_dp_vc_tu_mapping_table *tu_table) 961 961 { 962 962 - struct dp_tu_calc_input in; 962 962 + struct msm_dp_tu_calc_input in; 963 963 struct drm_display_mode *drm_mode; 964 964 965 965 - drm_mode = &ctrl->panel->dp_mode.drm_mode; 965 965 + drm_mode = &ctrl->panel->msm_dp_mode.drm_mode; 966 966 967 967 in.lclk = ctrl->link->link_params.rate / 1000; 968 968 in.pclk_khz = drm_mode->clock; 969 969 in.hactive = drm_mode->hdisplay; 970 970 in.hporch = drm_mode->htotal - drm_mode->hdisplay; 971 971 in.nlanes = ctrl->link->link_params.num_lanes; 972 972 - in.bpp = ctrl->panel->dp_mode.bpp; 973 973 - in.pixel_enc = ctrl->panel->dp_mode.out_fmt_is_yuv_420 ? 420 : 444; 972 972 + in.bpp = ctrl->panel->msm_dp_mode.bpp; 973 973 + in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; 974 974 in.dsc_en = 0; 975 975 in.async_en = 0; 976 976 in.fec_en = 0; ··· 980 980 _dp_ctrl_calc_tu(ctrl, &in, tu_table); 981 981 } 982 982 983 983 - static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) 983 983 + static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) 984 984 { 985 985 - u32 dp_tu = 0x0; 985 985 + u32 msm_dp_tu = 0x0; 986 986 u32 valid_boundary = 0x0; 987 987 u32 valid_boundary2 = 0x0; 988 988 - struct dp_vc_tu_mapping_table tu_calc_table; 988 988 + struct msm_dp_vc_tu_mapping_table tu_calc_table; 989 989 990 990 - dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 990 990 + msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); 991 991 992 992 - dp_tu |= tu_calc_table.tu_size_minus1; 992 992 + msm_dp_tu |= tu_calc_table.tu_size_minus1; 993 993 valid_boundary |= tu_calc_table.valid_boundary_link; 994 994 valid_boundary |= (tu_calc_table.delay_start_link << 16); 995 995 ··· 1001 1001 valid_boundary2 |= BIT(0); 1002 1002 1003 1003 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", 1004 1004 - dp_tu, valid_boundary, valid_boundary2); 1004 1004 + msm_dp_tu, valid_boundary, valid_boundary2); 1005 1005 1006 1006 - dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 1007 1007 - dp_tu, valid_boundary, valid_boundary2); 1006 1006 + msm_dp_catalog_ctrl_update_transfer_unit(ctrl->catalog, 1007 1007 + msm_dp_tu, valid_boundary, valid_boundary2); 1008 1008 } 1009 1009 1010 1010 - static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) 1010 1010 + static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) 1011 1011 { 1012 1012 int ret = 0; 1013 1013 ··· 1019 1019 return ret; 1020 1020 } 1021 1021 1022 1022 - static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, 1022 1022 + static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl, 1023 1023 u8 v_level, u8 p_level) 1024 1024 { 1025 1025 union phy_configure_opts *phy_opts = &ctrl->phy_opts; ··· 1034 1034 return 0; 1035 1035 } 1036 1036 1037 1037 - static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) 1037 1037 + static int msm_dp_ctrl_update_vx_px(struct msm_dp_ctrl_private *ctrl) 1038 1038 { 1039 1039 - struct dp_link *link = ctrl->link; 1039 1039 + struct msm_dp_link *link = ctrl->link; 1040 1040 int ret = 0, lane, lane_cnt; 1041 1041 u8 buf[4]; 1042 1042 u32 max_level_reached = 0; ··· 1046 1046 drm_dbg_dp(ctrl->drm_dev, 1047 1047 "voltage level: %d emphasis level: %d\n", 1048 1048 voltage_swing_level, pre_emphasis_level); 1049 1049 - ret = dp_ctrl_set_vx_px(ctrl, 1049 1049 + ret = msm_dp_ctrl_set_vx_px(ctrl, 1050 1050 voltage_swing_level, pre_emphasis_level); 1051 1051 1052 1052 if (ret) ··· 1083 1083 return ret; 1084 1084 } 1085 1085 1086 1086 - static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 1086 1086 + static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl, 1087 1087 u8 pattern) 1088 1088 { 1089 1089 u8 buf; ··· 1100 1100 return ret == 1; 1101 1101 } 1102 1102 1103 1103 - static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 1103 1103 + static int msm_dp_ctrl_read_link_status(struct msm_dp_ctrl_private *ctrl, 1104 1104 u8 *link_status) 1105 1105 { 1106 1106 int ret = 0, len; ··· 1114 1114 return ret; 1115 1115 } 1116 1116 1117 1117 - static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 1117 1117 + static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, 1118 1118 int *training_step) 1119 1119 { 1120 1120 int tries, old_v_level, ret = 0; 1121 1121 u8 link_status[DP_LINK_STATUS_SIZE]; 1122 1122 int const maximum_retries = 4; 1123 1123 1124 1124 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1124 1124 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1125 1125 1126 1126 *training_step = DP_TRAINING_1; 1127 1127 1128 1128 - ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1128 1128 + ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1); 1129 1129 if (ret) 1130 1130 return ret; 1131 1131 - dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1131 1131 + msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | 1132 1132 DP_LINK_SCRAMBLING_DISABLE); 1133 1133 1134 1134 - ret = dp_ctrl_update_vx_px(ctrl); 1134 1134 + ret = msm_dp_ctrl_update_vx_px(ctrl); 1135 1135 if (ret) 1136 1136 return ret; 1137 1137 ··· 1140 1140 for (tries = 0; tries < maximum_retries; tries++) { 1141 1141 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); 1142 1142 1143 1143 - ret = dp_ctrl_read_link_status(ctrl, link_status); 1143 1143 + ret = msm_dp_ctrl_read_link_status(ctrl, link_status); 1144 1144 if (ret) 1145 1145 return ret; 1146 1146 ··· 1160 1160 old_v_level = ctrl->link->phy_params.v_level; 1161 1161 } 1162 1162 1163 1163 - dp_link_adjust_levels(ctrl->link, link_status); 1164 1164 - ret = dp_ctrl_update_vx_px(ctrl); 1163 1163 + msm_dp_link_adjust_levels(ctrl->link, link_status); 1164 1164 + ret = msm_dp_ctrl_update_vx_px(ctrl); 1165 1165 if (ret) 1166 1166 return ret; 1167 1167 } ··· 1170 1170 return -ETIMEDOUT; 1171 1171 } 1172 1172 1173 1173 - static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) 1173 1173 + static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl) 1174 1174 { 1175 1175 int ret = 0; 1176 1176 ··· 1198 1198 return ret; 1199 1199 } 1200 1200 1201 1201 - static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) 1201 1201 + static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl) 1202 1202 { 1203 1203 1204 1204 if (ctrl->link->link_params.num_lanes == 1) ··· 1213 1213 return 0; 1214 1214 } 1215 1215 1216 1216 - static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 1216 1216 + static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl) 1217 1217 { 1218 1218 - dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1218 1218 + msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); 1219 1219 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1220 1220 } 1221 1221 1222 1222 - static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 1222 1222 + static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, 1223 1223 int *training_step) 1224 1224 { 1225 1225 int tries = 0, ret = 0; ··· 1228 1228 int const maximum_retries = 5; 1229 1229 u8 link_status[DP_LINK_STATUS_SIZE]; 1230 1230 1231 1231 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1231 1231 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1232 1232 1233 1233 *training_step = DP_TRAINING_2; 1234 1234 ··· 1243 1243 state_ctrl_bit = 2; 1244 1244 } 1245 1245 1246 1246 - ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1246 1246 + ret = msm_dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); 1247 1247 if (ret) 1248 1248 return ret; 1249 1249 1250 1250 - dp_ctrl_train_pattern_set(ctrl, pattern); 1250 1250 + msm_dp_ctrl_train_pattern_set(ctrl, pattern); 1251 1251 1252 1252 for (tries = 0; tries <= maximum_retries; tries++) { 1253 1253 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); 1254 1254 1255 1255 - ret = dp_ctrl_read_link_status(ctrl, link_status); 1255 1255 + ret = msm_dp_ctrl_read_link_status(ctrl, link_status); 1256 1256 if (ret) 1257 1257 return ret; 1258 1258 ··· 1261 1261 return 0; 1262 1262 } 1263 1263 1264 1264 - dp_link_adjust_levels(ctrl->link, link_status); 1265 1265 - ret = dp_ctrl_update_vx_px(ctrl); 1264 1264 + msm_dp_link_adjust_levels(ctrl->link, link_status); 1265 1265 + ret = msm_dp_ctrl_update_vx_px(ctrl); 1266 1266 if (ret) 1267 1267 return ret; 1268 1268 ··· 1271 1271 return -ETIMEDOUT; 1272 1272 } 1273 1273 1274 1274 - static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 1274 1274 + static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, 1275 1275 int *training_step) 1276 1276 { 1277 1277 int ret = 0; 1278 1278 const u8 *dpcd = ctrl->panel->dpcd; 1279 1279 u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; 1280 1280 u8 assr; 1281 1281 - struct dp_link_info link_info = {0}; 1281 1281 + struct msm_dp_link_info link_info = {0}; 1282 1282 1283 1283 - dp_ctrl_config_ctrl(ctrl); 1283 1283 + msm_dp_ctrl_config_ctrl(ctrl); 1284 1284 1285 1285 link_info.num_lanes = ctrl->link->link_params.num_lanes; 1286 1286 link_info.rate = ctrl->link->link_params.rate; 1287 1287 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; 1288 1288 1289 1289 - dp_link_reset_phy_params_vx_px(ctrl->link); 1289 1289 + msm_dp_link_reset_phy_params_vx_px(ctrl->link); 1290 1290 1291 1291 - dp_aux_link_configure(ctrl->aux, &link_info); 1291 1291 + msm_dp_aux_link_configure(ctrl->aux, &link_info); 1292 1292 1293 1293 if (drm_dp_max_downspread(dpcd)) 1294 1294 encoding[0] |= DP_SPREAD_AMP_0_5; ··· 1302 1302 &assr, 1); 1303 1303 } 1304 1304 1305 1305 - ret = dp_ctrl_link_train_1(ctrl, training_step); 1305 1305 + ret = msm_dp_ctrl_link_train_1(ctrl, training_step); 1306 1306 if (ret) { 1307 1307 DRM_ERROR("link training #1 failed. ret=%d\n", ret); 1308 1308 goto end; ··· 1311 1311 /* print success info as this is a result of user initiated action */ 1312 1312 drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n"); 1313 1313 1314 1314 - ret = dp_ctrl_link_train_2(ctrl, training_step); 1314 1314 + ret = msm_dp_ctrl_link_train_2(ctrl, training_step); 1315 1315 if (ret) { 1316 1316 DRM_ERROR("link training #2 failed. ret=%d\n", ret); 1317 1317 goto end; ··· 1321 1321 drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n"); 1322 1322 1323 1323 end: 1324 1324 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1324 1324 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1325 1325 1326 1326 return ret; 1327 1327 } 1328 1328 1329 1329 - static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 1329 1329 + static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, 1330 1330 int *training_step) 1331 1331 { 1332 1332 int ret = 0; 1333 1333 1334 1334 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1334 1334 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); 1335 1335 1336 1336 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) 1337 1337 return ret; ··· 1342 1342 * a link training pattern, we have to first do soft reset. 1343 1343 */ 1344 1344 1345 1345 - ret = dp_ctrl_link_train(ctrl, training_step); 1345 1345 + ret = msm_dp_ctrl_link_train(ctrl, training_step); 1346 1346 1347 1347 return ret; 1348 1348 } 1349 1349 1350 1350 - int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl) 1350 1350 + int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1351 1351 { 1352 1352 - struct dp_ctrl_private *ctrl; 1352 1352 + struct msm_dp_ctrl_private *ctrl; 1353 1353 int ret = 0; 1354 1354 1355 1355 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1355 1355 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1356 1356 1357 1357 if (ctrl->core_clks_on) { 1358 1358 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); ··· 1374 1374 return 0; 1375 1375 } 1376 1376 1377 1377 - void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl) 1377 1377 + void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1378 1378 { 1379 1379 - struct dp_ctrl_private *ctrl; 1379 1379 + struct msm_dp_ctrl_private *ctrl; 1380 1380 1381 1381 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1381 1381 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1382 1382 1383 1383 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); 1384 1384 ··· 1391 1391 ctrl->core_clks_on ? "on" : "off"); 1392 1392 } 1393 1393 1394 1394 - static int dp_ctrl_link_clk_enable(struct dp_ctrl *dp_ctrl) 1394 1394 + static int msm_dp_ctrl_link_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl) 1395 1395 { 1396 1396 - struct dp_ctrl_private *ctrl; 1396 1396 + struct msm_dp_ctrl_private *ctrl; 1397 1397 int ret = 0; 1398 1398 1399 1399 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1399 1399 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1400 1400 1401 1401 if (ctrl->link_clks_on) { 1402 1402 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); ··· 1406 1406 if (!ctrl->core_clks_on) { 1407 1407 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); 1408 1408 1409 1409 - dp_ctrl_core_clk_enable(dp_ctrl); 1409 1409 + msm_dp_ctrl_core_clk_enable(msm_dp_ctrl); 1410 1410 } 1411 1411 1412 1412 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); ··· 1424 1424 return 0; 1425 1425 } 1426 1426 1427 1427 - static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl) 1427 1427 + static void msm_dp_ctrl_link_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl) 1428 1428 { 1429 1429 - struct dp_ctrl_private *ctrl; 1429 1429 + struct msm_dp_ctrl_private *ctrl; 1430 1430 1431 1431 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1431 1431 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1432 1432 1433 1433 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); 1434 1434 ··· 1441 1441 ctrl->core_clks_on ? "on" : "off"); 1442 1442 } 1443 1443 1444 1444 - static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 1444 1444 + static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) 1445 1445 { 1446 1446 int ret = 0; 1447 1447 struct phy *phy = ctrl->phy; ··· 1455 1455 phy_power_on(phy); 1456 1456 1457 1457 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); 1458 1458 - ret = dp_ctrl_link_clk_enable(&ctrl->dp_ctrl); 1458 1458 + ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); 1459 1459 if (ret) 1460 1460 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); 1461 1461 ··· 1464 1464 return ret; 1465 1465 } 1466 1466 1467 1467 - void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) 1467 1467 + void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enable) 1468 1468 { 1469 1469 - struct dp_ctrl_private *ctrl; 1469 1469 + struct msm_dp_ctrl_private *ctrl; 1470 1470 1471 1471 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1471 1471 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1472 1472 1473 1473 - dp_catalog_ctrl_reset(ctrl->catalog); 1473 1473 + msm_dp_catalog_ctrl_reset(ctrl->catalog); 1474 1474 1475 1475 /* 1476 1476 * all dp controller programmable registers will not ··· 1478 1478 * therefore interrupt mask bits have to be updated 1479 1479 * to enable/disable interrupts 1480 1480 */ 1481 1481 - dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1481 1481 + msm_dp_catalog_ctrl_enable_irq(ctrl->catalog, enable); 1482 1482 } 1483 1483 1484 1484 - void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl) 1484 1484 + void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) 1485 1485 { 1486 1486 u8 cfg; 1487 1487 - struct dp_ctrl_private *ctrl = container_of(dp_ctrl, 1488 1488 - struct dp_ctrl_private, dp_ctrl); 1487 1487 + struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1488 1488 + struct msm_dp_ctrl_private, msm_dp_ctrl); 1489 1489 1490 1490 if (!ctrl->panel->psr_cap.version) 1491 1491 return; 1492 1492 1493 1493 - dp_catalog_ctrl_config_psr(ctrl->catalog); 1493 1493 + msm_dp_catalog_ctrl_config_psr(ctrl->catalog); 1494 1494 1495 1495 cfg = DP_PSR_ENABLE; 1496 1496 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); 1497 1497 } 1498 1498 1499 1499 - void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter) 1499 1499 + void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) 1500 1500 { 1501 1501 - struct dp_ctrl_private *ctrl = container_of(dp_ctrl, 1502 1502 - struct dp_ctrl_private, dp_ctrl); 1501 1501 + struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, 1502 1502 + struct msm_dp_ctrl_private, msm_dp_ctrl); 1503 1503 1504 1504 if (!ctrl->panel->psr_cap.version) 1505 1505 return; ··· 1516 1516 */ 1517 1517 if (enter) { 1518 1518 reinit_completion(&ctrl->psr_op_comp); 1519 1519 - dp_catalog_ctrl_set_psr(ctrl->catalog, true); 1519 1519 + msm_dp_catalog_ctrl_set_psr(ctrl->catalog, true); 1520 1520 1521 1521 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, 1522 1522 PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { 1523 1523 DRM_ERROR("PSR_ENTRY timedout\n"); 1524 1524 - dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1524 1524 + msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1525 1525 return; 1526 1526 } 1527 1527 1528 1528 - dp_ctrl_push_idle(dp_ctrl); 1529 1529 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1528 1528 + msm_dp_ctrl_push_idle(msm_dp_ctrl); 1529 1529 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1530 1530 1531 1531 - dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); 1531 1531 + msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false); 1532 1532 } else { 1533 1533 - dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); 1533 1533 + msm_dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true); 1534 1534 1535 1535 - dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1536 1536 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1537 1537 - dp_ctrl_wait4video_ready(ctrl); 1538 1538 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1535 1535 + msm_dp_catalog_ctrl_set_psr(ctrl->catalog, false); 1536 1536 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1537 1537 + msm_dp_ctrl_wait4video_ready(ctrl); 1538 1538 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); 1539 1539 } 1540 1540 } 1541 1541 1542 1542 - void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) 1542 1542 + void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl) 1543 1543 { 1544 1544 - struct dp_ctrl_private *ctrl; 1544 1544 + struct msm_dp_ctrl_private *ctrl; 1545 1545 struct phy *phy; 1546 1546 1547 1547 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1547 1547 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1548 1548 phy = ctrl->phy; 1549 1549 1550 1550 - dp_catalog_ctrl_phy_reset(ctrl->catalog); 1550 1550 + msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); 1551 1551 phy_init(phy); 1552 1552 1553 1553 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1554 1554 phy, phy->init_count, phy->power_count); 1555 1555 } 1556 1556 1557 1557 - void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) 1557 1557 + void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl) 1558 1558 { 1559 1559 - struct dp_ctrl_private *ctrl; 1559 1559 + struct msm_dp_ctrl_private *ctrl; 1560 1560 struct phy *phy; 1561 1561 1562 1562 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1562 1562 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1563 1563 phy = ctrl->phy; 1564 1564 1565 1565 - dp_catalog_ctrl_phy_reset(ctrl->catalog); 1565 1565 + msm_dp_catalog_ctrl_phy_reset(ctrl->catalog); 1566 1566 phy_exit(phy); 1567 1567 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 1568 1568 phy, phy->init_count, phy->power_count); 1569 1569 } 1570 1570 1571 1571 - static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 1571 1571 + static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) 1572 1572 { 1573 1573 struct phy *phy = ctrl->phy; 1574 1574 int ret = 0; 1575 1575 1576 1576 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1576 1576 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1577 1577 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1578 1578 phy_configure(phy, &ctrl->phy_opts); 1579 1579 /* ··· 1583 1583 */ 1584 1584 dev_pm_opp_set_rate(ctrl->dev, 0); 1585 1585 1586 1586 - dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 1586 1586 + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 1587 1587 1588 1588 phy_power_off(phy); 1589 1589 /* hw recommended delay before re-enabling clocks */ 1590 1590 msleep(20); 1591 1591 1592 1592 - ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1592 1592 + ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 1593 1593 if (ret) { 1594 1594 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret); 1595 1595 return ret; ··· 1598 1598 return ret; 1599 1599 } 1600 1600 1601 1601 - static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 1601 1601 + static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) 1602 1602 { 1603 1603 struct phy *phy; 1604 1604 1605 1605 phy = ctrl->phy; 1606 1606 1607 1607 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1607 1607 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 1608 1608 1609 1609 - dp_catalog_ctrl_reset(ctrl->catalog); 1609 1609 + msm_dp_catalog_ctrl_reset(ctrl->catalog); 1610 1610 1611 1611 dev_pm_opp_set_rate(ctrl->dev, 0); 1612 1612 - dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 1612 1612 + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 1613 1613 1614 1614 phy_power_off(phy); 1615 1615 ··· 1622 1622 return 0; 1623 1623 } 1624 1624 1625 1625 - static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) 1625 1625 + static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) 1626 1626 { 1627 1627 int ret = 0; 1628 1628 int training_step = DP_TRAINING_NONE; 1629 1629 1630 1630 - dp_ctrl_push_idle(&ctrl->dp_ctrl); 1630 1630 + msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); 1631 1631 1632 1632 ctrl->link->phy_params.p_level = 0; 1633 1633 ctrl->link->phy_params.v_level = 0; 1634 1634 1635 1635 - ret = dp_ctrl_setup_main_link(ctrl, &training_step); 1635 1635 + ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1636 1636 if (ret) 1637 1637 goto end; 1638 1638 1639 1639 - dp_ctrl_clear_training_pattern(ctrl); 1639 1639 + msm_dp_ctrl_clear_training_pattern(ctrl); 1640 1640 1641 1641 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1641 1641 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 1642 1642 1643 1643 - ret = dp_ctrl_wait4video_ready(ctrl); 1643 1643 + ret = msm_dp_ctrl_wait4video_ready(ctrl); 1644 1644 end: 1645 1645 return ret; 1646 1646 } 1647 1647 1648 1648 - static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) 1648 1648 + static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) 1649 1649 { 1650 1650 bool success = false; 1651 1651 u32 pattern_sent = 0x0; ··· 1653 1653 1654 1654 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); 1655 1655 1656 1656 - if (dp_ctrl_set_vx_px(ctrl, 1656 1656 + if (msm_dp_ctrl_set_vx_px(ctrl, 1657 1657 ctrl->link->phy_params.v_level, 1658 1658 ctrl->link->phy_params.p_level)) { 1659 1659 DRM_ERROR("Failed to set v/p levels\n"); 1660 1660 return false; 1661 1661 } 1662 1662 - dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1663 1663 - dp_ctrl_update_vx_px(ctrl); 1664 1664 - dp_link_send_test_response(ctrl->link); 1662 1662 + msm_dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested); 1663 1663 + msm_dp_ctrl_update_vx_px(ctrl); 1664 1664 + msm_dp_link_send_test_response(ctrl->link); 1665 1665 1666 1666 - pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1666 1666 + pattern_sent = msm_dp_catalog_ctrl_read_phy_pattern(ctrl->catalog); 1667 1667 1668 1668 switch (pattern_sent) { 1669 1669 case MR_LINK_TRAINING1: ··· 1697 1697 return success; 1698 1698 } 1699 1699 1700 1700 - static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) 1700 1700 + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl) 1701 1701 { 1702 1702 int ret; 1703 1703 unsigned long pixel_rate; ··· 1713 1713 * running. Add the global reset just before disabling the 1714 1714 * link clocks and core clocks. 1715 1715 */ 1716 1716 - dp_ctrl_off(&ctrl->dp_ctrl); 1716 1716 + msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); 1717 1717 1718 1718 - ret = dp_ctrl_on_link(&ctrl->dp_ctrl); 1718 1718 + ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); 1719 1719 if (ret) { 1720 1720 DRM_ERROR("failed to enable DP link controller\n"); 1721 1721 return ret; 1722 1722 } 1723 1723 1724 1724 - pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1724 1724 + pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; 1725 1725 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); 1726 1726 if (ret) { 1727 1727 DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); ··· 1739 1739 ctrl->stream_clks_on = true; 1740 1740 } 1741 1741 1742 1742 - dp_ctrl_send_phy_test_pattern(ctrl); 1742 1742 + msm_dp_ctrl_send_phy_test_pattern(ctrl); 1743 1743 1744 1744 return 0; 1745 1745 } 1746 1746 1747 1747 - void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 1747 1747 + void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl) 1748 1748 { 1749 1749 - struct dp_ctrl_private *ctrl; 1749 1749 + struct msm_dp_ctrl_private *ctrl; 1750 1750 u32 sink_request = 0x0; 1751 1751 1752 1752 - if (!dp_ctrl) { 1752 1752 + if (!msm_dp_ctrl) { 1753 1753 DRM_ERROR("invalid input\n"); 1754 1754 return; 1755 1755 } 1756 1756 1757 1757 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1757 1757 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1758 1758 sink_request = ctrl->link->sink_request; 1759 1759 1760 1760 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1761 1761 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); 1762 1762 - if (dp_ctrl_process_phy_test_request(ctrl)) { 1762 1762 + if (msm_dp_ctrl_process_phy_test_request(ctrl)) { 1763 1763 DRM_ERROR("process phy_test_req failed\n"); 1764 1764 return; 1765 1765 } 1766 1766 } 1767 1767 1768 1768 if (sink_request & DP_LINK_STATUS_UPDATED) { 1769 1769 - if (dp_ctrl_link_maintenance(ctrl)) { 1769 1769 + if (msm_dp_ctrl_link_maintenance(ctrl)) { 1770 1770 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1771 1771 return; 1772 1772 } 1773 1773 } 1774 1774 1775 1775 if (sink_request & DP_TEST_LINK_TRAINING) { 1776 1776 - dp_link_send_test_response(ctrl->link); 1777 1777 - if (dp_ctrl_link_maintenance(ctrl)) { 1776 1776 + msm_dp_link_send_test_response(ctrl->link); 1777 1777 + if (msm_dp_ctrl_link_maintenance(ctrl)) { 1778 1778 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n"); 1779 1779 return; 1780 1780 } 1781 1781 } 1782 1782 } 1783 1783 1784 1784 - static bool dp_ctrl_clock_recovery_any_ok( 1784 1784 + static bool msm_dp_ctrl_clock_recovery_any_ok( 1785 1785 const u8 link_status[DP_LINK_STATUS_SIZE], 1786 1786 int lane_count) 1787 1787 { ··· 1800 1800 return drm_dp_clock_recovery_ok(link_status, reduced_cnt); 1801 1801 } 1802 1802 1803 1803 - static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl) 1803 1803 + static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) 1804 1804 { 1805 1805 u8 link_status[DP_LINK_STATUS_SIZE]; 1806 1806 int num_lanes = ctrl->link->link_params.num_lanes; 1807 1807 1808 1808 - dp_ctrl_read_link_status(ctrl, link_status); 1808 1808 + msm_dp_ctrl_read_link_status(ctrl, link_status); 1809 1809 1810 1810 return drm_dp_channel_eq_ok(link_status, num_lanes); 1811 1811 } 1812 1812 1813 1813 - int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 1813 1813 + int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) 1814 1814 { 1815 1815 int rc = 0; 1816 1816 - struct dp_ctrl_private *ctrl; 1816 1816 + struct msm_dp_ctrl_private *ctrl; 1817 1817 u32 rate; 1818 1818 int link_train_max_retries = 5; 1819 1819 u32 const phy_cts_pixel_clk_khz = 148500; ··· 1821 1821 unsigned int training_step; 1822 1822 unsigned long pixel_rate; 1823 1823 1824 1824 - if (!dp_ctrl) 1824 1824 + if (!msm_dp_ctrl) 1825 1825 return -EINVAL; 1826 1826 1827 1827 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1827 1827 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1828 1828 1829 1829 rate = ctrl->panel->link_info.rate; 1830 1830 - pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; 1830 1830 + pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; 1831 1831 1832 1832 - dp_ctrl_core_clk_enable(&ctrl->dp_ctrl); 1832 1832 + msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); 1833 1833 1834 1834 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { 1835 1835 drm_dbg_dp(ctrl->drm_dev, ··· 1840 1840 ctrl->link->link_params.rate = rate; 1841 1841 ctrl->link->link_params.num_lanes = 1842 1842 ctrl->panel->link_info.num_lanes; 1843 1843 - if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) 1843 1843 + if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 1844 1844 pixel_rate >>= 1; 1845 1845 } 1846 1846 ··· 1848 1848 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, 1849 1849 pixel_rate); 1850 1850 1851 1851 - rc = dp_ctrl_enable_mainlink_clocks(ctrl); 1851 1851 + rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 1852 1852 if (rc) 1853 1853 return rc; 1854 1854 1855 1855 while (--link_train_max_retries) { 1856 1856 training_step = DP_TRAINING_NONE; 1857 1857 - rc = dp_ctrl_setup_main_link(ctrl, &training_step); 1857 1857 + rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1858 1858 if (rc == 0) { 1859 1859 /* training completed successfully */ 1860 1860 break; 1861 1861 } else if (training_step == DP_TRAINING_1) { 1862 1862 /* link train_1 failed */ 1863 1863 - if (!dp_catalog_link_is_connected(ctrl->catalog)) 1863 1863 + if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) 1864 1864 break; 1865 1865 1866 1866 - dp_ctrl_read_link_status(ctrl, link_status); 1866 1866 + msm_dp_ctrl_read_link_status(ctrl, link_status); 1867 1867 1868 1868 - rc = dp_ctrl_link_rate_down_shift(ctrl); 1868 1868 + rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 1869 1869 if (rc < 0) { /* already in RBR = 1.6G */ 1870 1870 - if (dp_ctrl_clock_recovery_any_ok(link_status, 1870 1870 + if (msm_dp_ctrl_clock_recovery_any_ok(link_status, 1871 1871 ctrl->link->link_params.num_lanes)) { 1872 1872 /* 1873 1873 * some lanes are ready, 1874 1874 * reduce lane number 1875 1875 */ 1876 1876 - rc = dp_ctrl_link_lane_down_shift(ctrl); 1876 1876 + rc = msm_dp_ctrl_link_lane_down_shift(ctrl); 1877 1877 if (rc < 0) { /* lane == 1 already */ 1878 1878 /* end with failure */ 1879 1879 break; ··· 1885 1885 } 1886 1886 } else if (training_step == DP_TRAINING_2) { 1887 1887 /* link train_2 failed */ 1888 1888 - if (!dp_catalog_link_is_connected(ctrl->catalog)) 1888 1888 + if (!msm_dp_catalog_link_is_connected(ctrl->catalog)) 1889 1889 break; 1890 1890 1891 1891 - dp_ctrl_read_link_status(ctrl, link_status); 1891 1891 + msm_dp_ctrl_read_link_status(ctrl, link_status); 1892 1892 1893 1893 if (!drm_dp_clock_recovery_ok(link_status, 1894 1894 ctrl->link->link_params.num_lanes)) 1895 1895 - rc = dp_ctrl_link_rate_down_shift(ctrl); 1895 1895 + rc = msm_dp_ctrl_link_rate_down_shift(ctrl); 1896 1896 else 1897 1897 - rc = dp_ctrl_link_lane_down_shift(ctrl); 1897 1897 + rc = msm_dp_ctrl_link_lane_down_shift(ctrl); 1898 1898 1899 1899 if (rc < 0) { 1900 1900 /* end with failure */ ··· 1902 1902 } 1903 1903 1904 1904 /* stop link training before start re training */ 1905 1905 - dp_ctrl_clear_training_pattern(ctrl); 1905 1905 + msm_dp_ctrl_clear_training_pattern(ctrl); 1906 1906 } 1907 1907 1908 1908 - rc = dp_ctrl_reinitialize_mainlink(ctrl); 1908 1908 + rc = msm_dp_ctrl_reinitialize_mainlink(ctrl); 1909 1909 if (rc) { 1910 1910 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); 1911 1911 break; ··· 1926 1926 * link training failed 1927 1927 * end txing train pattern here 1928 1928 */ 1929 1929 - dp_ctrl_clear_training_pattern(ctrl); 1929 1929 + msm_dp_ctrl_clear_training_pattern(ctrl); 1930 1930 1931 1931 - dp_ctrl_deinitialize_mainlink(ctrl); 1931 1931 + msm_dp_ctrl_deinitialize_mainlink(ctrl); 1932 1932 rc = -ECONNRESET; 1933 1933 } 1934 1934 1935 1935 return rc; 1936 1936 } 1937 1937 1938 1938 - static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) 1938 1938 + static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) 1939 1939 { 1940 1940 int training_step = DP_TRAINING_NONE; 1941 1941 1942 1942 - return dp_ctrl_setup_main_link(ctrl, &training_step); 1942 1942 + return msm_dp_ctrl_setup_main_link(ctrl, &training_step); 1943 1943 } 1944 1944 1945 1945 - int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) 1945 1945 + int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train) 1946 1946 { 1947 1947 int ret = 0; 1948 1948 bool mainlink_ready = false; 1949 1949 - struct dp_ctrl_private *ctrl; 1949 1949 + struct msm_dp_ctrl_private *ctrl; 1950 1950 unsigned long pixel_rate; 1951 1951 unsigned long pixel_rate_orig; 1952 1952 1953 1953 - if (!dp_ctrl) 1953 1953 + if (!msm_dp_ctrl) 1954 1954 return -EINVAL; 1955 1955 1956 1956 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 1956 1956 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 1957 1957 1958 1958 - pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; 1958 1958 + pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; 1959 1959 1960 1960 - if (dp_ctrl->wide_bus_en || ctrl->panel->dp_mode.out_fmt_is_yuv_420) 1960 1960 + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) 1961 1961 pixel_rate >>= 1; 1962 1962 1963 1963 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", ··· 1969 1969 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); 1970 1970 1971 1971 if (!ctrl->link_clks_on) { /* link clk is off */ 1972 1972 - ret = dp_ctrl_enable_mainlink_clocks(ctrl); 1972 1972 + ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); 1973 1973 if (ret) { 1974 1974 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); 1975 1975 goto end; ··· 1993 1993 ctrl->stream_clks_on = true; 1994 1994 } 1995 1995 1996 1996 - if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) 1997 1997 - dp_ctrl_link_retrain(ctrl); 1996 1996 + if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) 1997 1997 + msm_dp_ctrl_link_retrain(ctrl); 1998 1998 1999 1999 /* stop txing train pattern to end link training */ 2000 2000 - dp_ctrl_clear_training_pattern(ctrl); 2000 2000 + msm_dp_ctrl_clear_training_pattern(ctrl); 2001 2001 2002 2002 /* 2003 2003 * Set up transfer unit values and set controller state to send ··· 2005 2005 */ 2006 2006 reinit_completion(&ctrl->video_comp); 2007 2007 2008 2008 - dp_ctrl_configure_source_params(ctrl); 2008 2008 + msm_dp_ctrl_configure_source_params(ctrl); 2009 2009 2010 2010 - dp_catalog_ctrl_config_msa(ctrl->catalog, 2010 2010 + msm_dp_catalog_ctrl_config_msa(ctrl->catalog, 2011 2011 ctrl->link->link_params.rate, 2012 2012 pixel_rate_orig, 2013 2013 - ctrl->panel->dp_mode.out_fmt_is_yuv_420); 2013 2013 + ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); 2014 2014 2015 2015 - dp_ctrl_setup_tr_unit(ctrl); 2015 2015 + msm_dp_ctrl_setup_tr_unit(ctrl); 2016 2016 2017 2017 - dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 2017 2017 + msm_dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); 2018 2018 2019 2019 - ret = dp_ctrl_wait4video_ready(ctrl); 2019 2019 + ret = msm_dp_ctrl_wait4video_ready(ctrl); 2020 2020 if (ret) 2021 2021 return ret; 2022 2022 2023 2023 - mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 2023 2023 + mainlink_ready = msm_dp_catalog_ctrl_mainlink_ready(ctrl->catalog); 2024 2024 drm_dbg_dp(ctrl->drm_dev, 2025 2025 "mainlink %s\n", mainlink_ready ? "READY" : "NOT READY"); 2026 2026 ··· 2028 2028 return ret; 2029 2029 } 2030 2030 2031 2031 - void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 2031 2031 + void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) 2032 2032 { 2033 2033 - struct dp_ctrl_private *ctrl; 2033 2033 + struct msm_dp_ctrl_private *ctrl; 2034 2034 struct phy *phy; 2035 2035 2036 2036 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2036 2036 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2037 2037 phy = ctrl->phy; 2038 2038 2039 2039 - dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2039 2039 + msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2040 2040 2041 2041 /* set dongle to D3 (power off) mode */ 2042 2042 - dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 2042 2042 + msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); 2043 2043 2044 2044 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2044 2044 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2045 2045 2046 2046 if (ctrl->stream_clks_on) { 2047 2047 clk_disable_unprepare(ctrl->pixel_clk); ··· 2049 2049 } 2050 2050 2051 2051 dev_pm_opp_set_rate(ctrl->dev, 0); 2052 2052 - dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2052 2052 + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2053 2053 2054 2054 phy_power_off(phy); 2055 2055 ··· 2061 2061 phy, phy->init_count, phy->power_count); 2062 2062 } 2063 2063 2064 2064 - void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) 2064 2064 + void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) 2065 2065 { 2066 2066 - struct dp_ctrl_private *ctrl; 2066 2066 + struct msm_dp_ctrl_private *ctrl; 2067 2067 struct phy *phy; 2068 2068 2069 2069 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2069 2069 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2070 2070 phy = ctrl->phy; 2071 2071 2072 2072 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2072 2072 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2073 2073 2074 2074 - dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2074 2074 + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2075 2075 2076 2076 DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", 2077 2077 phy, phy->init_count, phy->power_count); ··· 2082 2082 phy, phy->init_count, phy->power_count); 2083 2083 } 2084 2084 2085 2085 - void dp_ctrl_off(struct dp_ctrl *dp_ctrl) 2085 2085 + void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) 2086 2086 { 2087 2087 - struct dp_ctrl_private *ctrl; 2087 2087 + struct msm_dp_ctrl_private *ctrl; 2088 2088 struct phy *phy; 2089 2089 2090 2090 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2090 2090 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2091 2091 phy = ctrl->phy; 2092 2092 2093 2093 - dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2093 2093 + msm_dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); 2094 2094 2095 2095 - dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2095 2095 + msm_dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); 2096 2096 2097 2097 - dp_catalog_ctrl_reset(ctrl->catalog); 2097 2097 + msm_dp_catalog_ctrl_reset(ctrl->catalog); 2098 2098 2099 2099 if (ctrl->stream_clks_on) { 2100 2100 clk_disable_unprepare(ctrl->pixel_clk); ··· 2102 2102 } 2103 2103 2104 2104 dev_pm_opp_set_rate(ctrl->dev, 0); 2105 2105 - dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); 2105 2105 + msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); 2106 2106 2107 2107 phy_power_off(phy); 2108 2108 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", 2109 2109 phy, phy->init_count, phy->power_count); 2110 2110 } 2111 2111 2112 2112 - irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl) 2112 2112 + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) 2113 2113 { 2114 2114 - struct dp_ctrl_private *ctrl; 2114 2114 + struct msm_dp_ctrl_private *ctrl; 2115 2115 u32 isr; 2116 2116 irqreturn_t ret = IRQ_NONE; 2117 2117 2118 2118 - if (!dp_ctrl) 2118 2118 + if (!msm_dp_ctrl) 2119 2119 return IRQ_NONE; 2120 2120 2121 2121 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2121 2121 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2122 2122 2123 2123 if (ctrl->panel->psr_cap.version) { 2124 2124 - isr = dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); 2124 2124 + isr = msm_dp_catalog_ctrl_read_psr_interrupt_status(ctrl->catalog); 2125 2125 2126 2126 if (isr) 2127 2127 complete(&ctrl->psr_op_comp); ··· 2136 2136 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); 2137 2137 } 2138 2138 2139 2139 - isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog); 2139 2139 + isr = msm_dp_catalog_ctrl_get_interrupt(ctrl->catalog); 2140 2140 2141 2141 2142 2142 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { ··· 2164 2164 "ctrl_link_iface", 2165 2165 }; 2166 2166 2167 2167 - static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl) 2167 2167 + static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) 2168 2168 { 2169 2169 - struct dp_ctrl_private *ctrl; 2169 2169 + struct msm_dp_ctrl_private *ctrl; 2170 2170 struct device *dev; 2171 2171 int i, rc; 2172 2172 2173 2173 - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); 2173 2173 + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); 2174 2174 dev = ctrl->dev; 2175 2175 2176 2176 ctrl->num_core_clks = ARRAY_SIZE(core_clks); ··· 2204 2204 return 0; 2205 2205 } 2206 2206 2207 2207 - struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 2208 2208 - struct dp_panel *panel, struct drm_dp_aux *aux, 2209 2209 - struct dp_catalog *catalog, 2207 2207 + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, 2208 2208 + struct msm_dp_panel *panel, struct drm_dp_aux *aux, 2209 2209 + struct msm_dp_catalog *catalog, 2210 2210 struct phy *phy) 2211 2211 { 2212 2212 - struct dp_ctrl_private *ctrl; 2212 2212 + struct msm_dp_ctrl_private *ctrl; 2213 2213 int ret; 2214 2214 2215 2215 if (!dev || !panel || !aux || ··· 2228 2228 if (ret) { 2229 2229 dev_err(dev, "invalid DP OPP table in device tree\n"); 2230 2230 /* caller do PTR_ERR(opp_table) */ 2231 2231 - return (struct dp_ctrl *)ERR_PTR(ret); 2231 2231 + return (struct msm_dp_ctrl *)ERR_PTR(ret); 2232 2232 } 2233 2233 2234 2234 /* OPP table is optional */ ··· 2248 2248 ctrl->dev = dev; 2249 2249 ctrl->phy = phy; 2250 2250 2251 2251 - ret = dp_ctrl_clk_init(&ctrl->dp_ctrl); 2251 2251 + ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); 2252 2252 if (ret) { 2253 2253 dev_err(dev, "failed to init clocks\n"); 2254 2254 return ERR_PTR(ret); 2255 2255 } 2256 2256 2257 2257 - return &ctrl->dp_ctrl; 2257 2257 + return &ctrl->msm_dp_ctrl; 2258 2258 }

+20 -20

drivers/gpu/drm/msm/dp/dp_ctrl.h

reviewed

··· 11 11 #include "dp_link.h" 12 12 #include "dp_catalog.h" 13 13 14 14 - struct dp_ctrl { 14 14 + struct msm_dp_ctrl { 15 15 bool wide_bus_en; 16 16 }; 17 17 18 18 struct phy; 19 19 20 20 - int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); 21 21 - int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train); 22 22 - void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl); 23 23 - void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl); 24 24 - void dp_ctrl_off(struct dp_ctrl *dp_ctrl); 25 25 - void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl); 26 26 - irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl); 27 27 - void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl); 28 28 - struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, 29 29 - struct dp_panel *panel, struct drm_dp_aux *aux, 30 30 - struct dp_catalog *catalog, 20 20 + int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); 21 21 + int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link_train); 22 22 + void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); 23 23 + void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); 24 24 + void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); 25 25 + void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); 26 26 + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); 27 27 + void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); 28 28 + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, 29 29 + struct msm_dp_panel *panel, struct drm_dp_aux *aux, 30 30 + struct msm_dp_catalog *catalog, 31 31 struct phy *phy); 32 32 33 33 - void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable); 34 34 - void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl); 35 35 - void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl); 36 36 - void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl); 33 33 + void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enable); 34 34 + void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); 35 35 + void msm_dp_ctrl_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); 36 36 + void msm_dp_ctrl_irq_phy_exit(struct msm_dp_ctrl *msm_dp_ctrl); 37 37 38 38 - void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable); 39 39 - void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl); 38 38 + void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enable); 39 39 + void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl); 40 40 41 41 - int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl); 42 42 - void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl); 41 41 + int msm_dp_ctrl_core_clk_enable(struct msm_dp_ctrl *msm_dp_ctrl); 42 42 + void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm_dp_ctrl); 43 43 44 44 #endif /* _DP_CTRL_H_ */

+34 -34

drivers/gpu/drm/msm/dp/dp_debug.c

reviewed

··· 17 17 18 18 #define DEBUG_NAME "msm_dp" 19 19 20 20 - struct dp_debug_private { 21 21 - struct dp_link *link; 22 22 - struct dp_panel *panel; 20 20 + struct msm_dp_debug_private { 21 21 + struct msm_dp_link *link; 22 22 + struct msm_dp_panel *panel; 23 23 struct drm_connector *connector; 24 24 }; 25 25 26 26 - static int dp_debug_show(struct seq_file *seq, void *p) 26 26 + static int msm_dp_debug_show(struct seq_file *seq, void *p) 27 27 { 28 28 - struct dp_debug_private *debug = seq->private; 28 28 + struct msm_dp_debug_private *debug = seq->private; 29 29 u64 lclk = 0; 30 30 u32 link_params_rate; 31 31 const struct drm_display_mode *drm_mode; ··· 33 33 if (!debug) 34 34 return -ENODEV; 35 35 36 36 - drm_mode = &debug->panel->dp_mode.drm_mode; 36 36 + drm_mode = &debug->panel->msm_dp_mode.drm_mode; 37 37 38 38 seq_printf(seq, "\tname = %s\n", DEBUG_NAME); 39 39 seq_printf(seq, "\tdrm_dp_link\n\t\trate = %u\n", ··· 55 55 drm_mode->hsync_end - drm_mode->hsync_start, 56 56 drm_mode->vsync_end - drm_mode->vsync_start); 57 57 seq_printf(seq, "\t\tactive_low = %dx%d\n", 58 58 - debug->panel->dp_mode.h_active_low, 59 59 - debug->panel->dp_mode.v_active_low); 58 58 + debug->panel->msm_dp_mode.h_active_low, 59 59 + debug->panel->msm_dp_mode.v_active_low); 60 60 seq_printf(seq, "\t\th_skew = %d\n", 61 61 drm_mode->hskew); 62 62 seq_printf(seq, "\t\trefresh rate = %d\n", ··· 64 64 seq_printf(seq, "\t\tpixel clock khz = %d\n", 65 65 drm_mode->clock); 66 66 seq_printf(seq, "\t\tbpp = %d\n", 67 67 - debug->panel->dp_mode.bpp); 67 67 + debug->panel->msm_dp_mode.bpp); 68 68 69 69 /* Link Information */ 70 70 seq_printf(seq, "\tdp_link:\n\t\ttest_requested = %d\n", ··· 83 83 84 84 return 0; 85 85 } 86 86 - DEFINE_SHOW_ATTRIBUTE(dp_debug); 86 86 + DEFINE_SHOW_ATTRIBUTE(msm_dp_debug); 87 87 88 88 - static int dp_test_data_show(struct seq_file *m, void *data) 88 88 + static int msm_dp_test_data_show(struct seq_file *m, void *data) 89 89 { 90 90 - const struct dp_debug_private *debug = m->private; 90 90 + const struct msm_dp_debug_private *debug = m->private; 91 91 const struct drm_connector *connector = debug->connector; 92 92 u32 bpc; 93 93 ··· 98 98 seq_printf(m, "vdisplay: %d\n", 99 99 debug->link->test_video.test_v_height); 100 100 seq_printf(m, "bpc: %u\n", 101 101 - dp_link_bit_depth_to_bpp(bpc) / 3); 101 101 + msm_dp_link_bit_depth_to_bpp(bpc) / 3); 102 102 } else { 103 103 seq_puts(m, "0"); 104 104 } 105 105 106 106 return 0; 107 107 } 108 108 - DEFINE_SHOW_ATTRIBUTE(dp_test_data); 108 108 + DEFINE_SHOW_ATTRIBUTE(msm_dp_test_data); 109 109 110 110 - static int dp_test_type_show(struct seq_file *m, void *data) 110 110 + static int msm_dp_test_type_show(struct seq_file *m, void *data) 111 111 { 112 112 - const struct dp_debug_private *debug = m->private; 112 112 + const struct msm_dp_debug_private *debug = m->private; 113 113 const struct drm_connector *connector = debug->connector; 114 114 115 115 if (connector->status == connector_status_connected) ··· 119 119 120 120 return 0; 121 121 } 122 122 - DEFINE_SHOW_ATTRIBUTE(dp_test_type); 122 122 + DEFINE_SHOW_ATTRIBUTE(msm_dp_test_type); 123 123 124 124 - static ssize_t dp_test_active_write(struct file *file, 124 124 + static ssize_t msm_dp_test_active_write(struct file *file, 125 125 const char __user *ubuf, 126 126 size_t len, loff_t *offp) 127 127 { 128 128 char *input_buffer; 129 129 int status = 0; 130 130 - const struct dp_debug_private *debug; 130 130 + const struct msm_dp_debug_private *debug; 131 131 const struct drm_connector *connector; 132 132 int val = 0; 133 133 ··· 164 164 return len; 165 165 } 166 166 167 167 - static int dp_test_active_show(struct seq_file *m, void *data) 167 167 + static int msm_dp_test_active_show(struct seq_file *m, void *data) 168 168 { 169 169 - struct dp_debug_private *debug = m->private; 169 169 + struct msm_dp_debug_private *debug = m->private; 170 170 struct drm_connector *connector = debug->connector; 171 171 172 172 if (connector->status == connector_status_connected) { ··· 181 181 return 0; 182 182 } 183 183 184 184 - static int dp_test_active_open(struct inode *inode, 184 184 + static int msm_dp_test_active_open(struct inode *inode, 185 185 struct file *file) 186 186 { 187 187 - return single_open(file, dp_test_active_show, 187 187 + return single_open(file, msm_dp_test_active_show, 188 188 inode->i_private); 189 189 } 190 190 191 191 static const struct file_operations test_active_fops = { 192 192 .owner = THIS_MODULE, 193 193 - .open = dp_test_active_open, 193 193 + .open = msm_dp_test_active_open, 194 194 .read = seq_read, 195 195 .llseek = seq_lseek, 196 196 .release = single_release, 197 197 - .write = dp_test_active_write 197 197 + .write = msm_dp_test_active_write 198 198 }; 199 199 200 200 - int dp_debug_init(struct device *dev, struct dp_panel *panel, 201 201 - struct dp_link *link, 200 200 + int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, 201 201 + struct msm_dp_link *link, 202 202 struct drm_connector *connector, 203 203 struct dentry *root, bool is_edp) 204 204 { 205 205 - struct dp_debug_private *debug; 205 205 + struct msm_dp_debug_private *debug; 206 206 207 207 if (!dev || !panel || !link) { 208 208 DRM_ERROR("invalid input\n"); ··· 217 217 debug->panel = panel; 218 218 219 219 debugfs_create_file("dp_debug", 0444, root, 220 220 - debug, &dp_debug_fops); 220 220 + debug, &msm_dp_debug_fops); 221 221 222 222 if (!is_edp) { 223 223 - debugfs_create_file("msm_dp_test_active", 0444, 223 223 + debugfs_create_file("dp_test_active", 0444, 224 224 root, 225 225 debug, &test_active_fops); 226 226 227 227 - debugfs_create_file("msm_dp_test_data", 0444, 227 227 + debugfs_create_file("dp_test_data", 0444, 228 228 root, 229 229 - debug, &dp_test_data_fops); 229 229 + debug, &msm_dp_test_data_fops); 230 230 231 231 - debugfs_create_file("msm_dp_test_type", 0444, 231 231 + debugfs_create_file("dp_test_type", 0444, 232 232 root, 233 233 - debug, &dp_test_type_fops); 233 233 + debug, &msm_dp_test_type_fops); 234 234 } 235 235 236 236 return 0;

+5 -5

drivers/gpu/drm/msm/dp/dp_debug.h

reviewed

··· 12 12 #if defined(CONFIG_DEBUG_FS) 13 13 14 14 /** 15 15 - * dp_debug_get() - configure and get the DisplayPlot debug module data 15 15 + * msm_dp_debug_get() - configure and get the DisplayPlot debug module data 16 16 * 17 17 * @dev: device instance of the caller 18 18 * @panel: instance of panel module ··· 25 25 * This function sets up the debug module and provides a way 26 26 * for debugfs input to be communicated with existing modules 27 27 */ 28 28 - int dp_debug_init(struct device *dev, struct dp_panel *panel, 29 29 - struct dp_link *link, 28 28 + int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, 29 29 + struct msm_dp_link *link, 30 30 struct drm_connector *connector, 31 31 struct dentry *root, 32 32 bool is_edp); ··· 34 34 #else 35 35 36 36 static inline 37 37 - int dp_debug_init(struct device *dev, struct dp_panel *panel, 38 38 - struct dp_link *link, 37 37 + int msm_dp_debug_init(struct device *dev, struct msm_dp_panel *panel, 38 38 + struct msm_dp_link *link, 39 39 struct drm_connector *connector, 40 40 struct dentry *root, 41 41 bool is_edp)

+452 -452

drivers/gpu/drm/msm/dp/dp_display.c

reviewed

··· 67 67 68 68 #define WAIT_FOR_RESUME_TIMEOUT_JIFFIES (HZ / 2) 69 69 70 70 - struct dp_event { 70 70 + struct msm_dp_event { 71 71 u32 event_id; 72 72 u32 data; 73 73 u32 delay; 74 74 }; 75 75 76 76 - struct dp_display_private { 76 76 + struct msm_dp_display_private { 77 77 int irq; 78 78 79 79 unsigned int id; ··· 85 85 86 86 struct drm_device *drm_dev; 87 87 88 88 - struct dp_catalog *catalog; 88 88 + struct msm_dp_catalog *catalog; 89 89 struct drm_dp_aux *aux; 90 90 - struct dp_link *link; 91 91 - struct dp_panel *panel; 92 92 - struct dp_ctrl *ctrl; 90 90 + struct msm_dp_link *link; 91 91 + struct msm_dp_panel *panel; 92 92 + struct msm_dp_ctrl *ctrl; 93 93 94 94 - struct dp_display_mode dp_mode; 95 95 - struct msm_dp dp_display; 94 94 + struct msm_dp_display_mode msm_dp_mode; 95 95 + struct msm_dp msm_dp_display; 96 96 97 97 /* wait for audio signaling */ 98 98 struct completion audio_comp; ··· 104 104 u32 event_pndx; 105 105 u32 event_gndx; 106 106 struct task_struct *ev_tsk; 107 107 - struct dp_event event_list[DP_EVENT_Q_MAX]; 107 107 + struct msm_dp_event event_list[DP_EVENT_Q_MAX]; 108 108 spinlock_t event_lock; 109 109 110 110 bool wide_bus_supported; 111 111 112 112 - struct dp_audio *audio; 112 112 + struct msm_dp_audio *audio; 113 113 }; 114 114 115 115 struct msm_dp_desc { ··· 118 118 bool wide_bus_supported; 119 119 }; 120 120 121 121 - static const struct msm_dp_desc sa8775p_dp_descs[] = { 121 121 + static const struct msm_dp_desc msm_dp_desc_sa8775p[] = { 122 122 { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 123 123 { .io_start = 0x0af5c000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, 124 124 { .io_start = 0x22154000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, ··· 126 126 {} 127 127 }; 128 128 129 129 - static const struct msm_dp_desc sc7180_dp_descs[] = { 129 129 + static const struct msm_dp_desc msm_dp_desc_sc7180[] = { 130 130 { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 131 131 {} 132 132 }; 133 133 134 134 - static const struct msm_dp_desc sc7280_dp_descs[] = { 134 134 + static const struct msm_dp_desc msm_dp_desc_sc7280[] = { 135 135 { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 136 136 { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, 137 137 {} 138 138 }; 139 139 140 140 - static const struct msm_dp_desc sc8180x_dp_descs[] = { 140 140 + static const struct msm_dp_desc msm_dp_desc_sc8180x[] = { 141 141 { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 142 142 { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, 143 143 { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, 144 144 {} 145 145 }; 146 146 147 147 - static const struct msm_dp_desc sc8280xp_dp_descs[] = { 147 147 + static const struct msm_dp_desc msm_dp_desc_sc8280xp[] = { 148 148 { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 149 149 { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, 150 150 { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, ··· 156 156 {} 157 157 }; 158 158 159 159 - static const struct msm_dp_desc sm8650_dp_descs[] = { 159 159 + static const struct msm_dp_desc msm_dp_desc_sm8650[] = { 160 160 { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 161 161 {} 162 162 }; 163 163 164 164 - static const struct msm_dp_desc x1e80100_dp_descs[] = { 164 164 + static const struct msm_dp_desc msm_dp_desc_x1e80100[] = { 165 165 { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true }, 166 166 { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true }, 167 167 { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true }, ··· 169 169 {} 170 170 }; 171 171 172 172 - static const struct of_device_id dp_dt_match[] = { 173 173 - { .compatible = "qcom,sa8775p-dp", .data = &sa8775p_dp_descs }, 174 174 - { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_descs }, 175 175 - { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_descs }, 176 176 - { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs }, 177 177 - { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs }, 178 178 - { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs }, 179 179 - { .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs }, 180 180 - { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_dp_descs }, 181 181 - { .compatible = "qcom,sdm845-dp", .data = &sc7180_dp_descs }, 182 182 - { .compatible = "qcom,sm8350-dp", .data = &sc7180_dp_descs }, 183 183 - { .compatible = "qcom,sm8650-dp", .data = &sm8650_dp_descs }, 184 184 - { .compatible = "qcom,x1e80100-dp", .data = &x1e80100_dp_descs }, 172 172 + static const struct of_device_id msm_dp_dt_match[] = { 173 173 + { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p }, 174 174 + { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 }, 175 175 + { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 }, 176 176 + { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 }, 177 177 + { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x }, 178 178 + { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x }, 179 179 + { .compatible = "qcom,sc8280xp-dp", .data = &msm_dp_desc_sc8280xp }, 180 180 + { .compatible = "qcom,sc8280xp-edp", .data = &msm_dp_desc_sc8280xp }, 181 181 + { .compatible = "qcom,sdm845-dp", .data = &msm_dp_desc_sc7180 }, 182 182 + { .compatible = "qcom,sm8350-dp", .data = &msm_dp_desc_sc7180 }, 183 183 + { .compatible = "qcom,sm8650-dp", .data = &msm_dp_desc_sm8650 }, 184 184 + { .compatible = "qcom,x1e80100-dp", .data = &msm_dp_desc_x1e80100 }, 185 185 {} 186 186 }; 187 187 188 188 - static struct dp_display_private *dev_get_dp_display_private(struct device *dev) 188 188 + static struct msm_dp_display_private *dev_get_dp_display_private(struct device *dev) 189 189 { 190 190 struct msm_dp *dp = dev_get_drvdata(dev); 191 191 192 192 - return container_of(dp, struct dp_display_private, dp_display); 192 192 + return container_of(dp, struct msm_dp_display_private, msm_dp_display); 193 193 } 194 194 195 195 - static int dp_add_event(struct dp_display_private *dp_priv, u32 event, 195 195 + static int msm_dp_add_event(struct msm_dp_display_private *msm_dp_priv, u32 event, 196 196 u32 data, u32 delay) 197 197 { 198 198 unsigned long flag; 199 199 - struct dp_event *todo; 199 199 + struct msm_dp_event *todo; 200 200 int pndx; 201 201 202 202 - spin_lock_irqsave(&dp_priv->event_lock, flag); 203 203 - pndx = dp_priv->event_pndx + 1; 202 202 + spin_lock_irqsave(&msm_dp_priv->event_lock, flag); 203 203 + pndx = msm_dp_priv->event_pndx + 1; 204 204 pndx %= DP_EVENT_Q_MAX; 205 205 - if (pndx == dp_priv->event_gndx) { 205 205 + if (pndx == msm_dp_priv->event_gndx) { 206 206 pr_err("event_q is full: pndx=%d gndx=%d\n", 207 207 - dp_priv->event_pndx, dp_priv->event_gndx); 208 208 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 207 207 + msm_dp_priv->event_pndx, msm_dp_priv->event_gndx); 208 208 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 209 209 return -EPERM; 210 210 } 211 211 - todo = &dp_priv->event_list[dp_priv->event_pndx++]; 212 212 - dp_priv->event_pndx %= DP_EVENT_Q_MAX; 211 211 + todo = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; 212 212 + msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; 213 213 todo->event_id = event; 214 214 todo->data = data; 215 215 todo->delay = delay; 216 216 - wake_up(&dp_priv->event_q); 217 217 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 216 216 + wake_up(&msm_dp_priv->event_q); 217 217 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 218 218 219 219 return 0; 220 220 } 221 221 222 222 - static int dp_del_event(struct dp_display_private *dp_priv, u32 event) 222 222 + static int msm_dp_del_event(struct msm_dp_display_private *msm_dp_priv, u32 event) 223 223 { 224 224 unsigned long flag; 225 225 - struct dp_event *todo; 225 225 + struct msm_dp_event *todo; 226 226 u32 gndx; 227 227 228 228 - spin_lock_irqsave(&dp_priv->event_lock, flag); 229 229 - if (dp_priv->event_pndx == dp_priv->event_gndx) { 230 230 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 228 228 + spin_lock_irqsave(&msm_dp_priv->event_lock, flag); 229 229 + if (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) { 230 230 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 231 231 return -ENOENT; 232 232 } 233 233 234 234 - gndx = dp_priv->event_gndx; 235 235 - while (dp_priv->event_pndx != gndx) { 236 236 - todo = &dp_priv->event_list[gndx]; 234 234 + gndx = msm_dp_priv->event_gndx; 235 235 + while (msm_dp_priv->event_pndx != gndx) { 236 236 + todo = &msm_dp_priv->event_list[gndx]; 237 237 if (todo->event_id == event) { 238 238 todo->event_id = EV_NO_EVENT; /* deleted */ 239 239 todo->delay = 0; ··· 241 241 gndx++; 242 242 gndx %= DP_EVENT_Q_MAX; 243 243 } 244 244 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 244 244 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 245 245 246 246 return 0; 247 247 } 248 248 249 249 - void dp_display_signal_audio_start(struct msm_dp *dp_display) 249 249 + void msm_dp_display_signal_audio_start(struct msm_dp *msm_dp_display) 250 250 { 251 251 - struct dp_display_private *dp; 251 251 + struct msm_dp_display_private *dp; 252 252 253 253 - dp = container_of(dp_display, struct dp_display_private, dp_display); 253 253 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 254 254 255 255 reinit_completion(&dp->audio_comp); 256 256 } 257 257 258 258 - void dp_display_signal_audio_complete(struct msm_dp *dp_display) 258 258 + void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display) 259 259 { 260 260 - struct dp_display_private *dp; 260 260 + struct msm_dp_display_private *dp; 261 261 262 262 - dp = container_of(dp_display, struct dp_display_private, dp_display); 262 262 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 263 263 264 264 complete_all(&dp->audio_comp); 265 265 } 266 266 267 267 - static int dp_hpd_event_thread_start(struct dp_display_private *dp_priv); 267 267 + static int msm_dp_hpd_event_thread_start(struct msm_dp_display_private *msm_dp_priv); 268 268 269 269 - static int dp_display_bind(struct device *dev, struct device *master, 269 269 + static int msm_dp_display_bind(struct device *dev, struct device *master, 270 270 void *data) 271 271 { 272 272 int rc = 0; 273 273 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 273 273 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 274 274 struct msm_drm_private *priv = dev_get_drvdata(master); 275 275 struct drm_device *drm = priv->dev; 276 276 277 277 - dp->dp_display.drm_dev = drm; 278 278 - priv->dp[dp->id] = &dp->dp_display; 277 277 + dp->msm_dp_display.drm_dev = drm; 278 278 + priv->dp[dp->id] = &dp->msm_dp_display; 279 279 280 280 281 281 282 282 dp->drm_dev = drm; 283 283 dp->aux->drm_dev = drm; 284 284 - rc = dp_aux_register(dp->aux); 284 284 + rc = msm_dp_aux_register(dp->aux); 285 285 if (rc) { 286 286 DRM_ERROR("DRM DP AUX register failed\n"); 287 287 goto end; 288 288 } 289 289 290 290 291 291 - rc = dp_register_audio_driver(dev, dp->audio); 291 291 + rc = msm_dp_register_audio_driver(dev, dp->audio); 292 292 if (rc) { 293 293 DRM_ERROR("Audio registration Dp failed\n"); 294 294 goto end; 295 295 } 296 296 297 297 - rc = dp_hpd_event_thread_start(dp); 297 297 + rc = msm_dp_hpd_event_thread_start(dp); 298 298 if (rc) { 299 299 DRM_ERROR("Event thread create failed\n"); 300 300 goto end; ··· 305 305 return rc; 306 306 } 307 307 308 308 - static void dp_display_unbind(struct device *dev, struct device *master, 308 308 + static void msm_dp_display_unbind(struct device *dev, struct device *master, 309 309 void *data) 310 310 { 311 311 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 311 311 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 312 312 struct msm_drm_private *priv = dev_get_drvdata(master); 313 313 314 314 kthread_stop(dp->ev_tsk); 315 315 316 316 of_dp_aux_depopulate_bus(dp->aux); 317 317 318 318 - dp_unregister_audio_driver(dev, dp->audio); 319 319 - dp_aux_unregister(dp->aux); 318 318 + msm_dp_unregister_audio_driver(dev, dp->audio); 319 319 + msm_dp_aux_unregister(dp->aux); 320 320 dp->drm_dev = NULL; 321 321 dp->aux->drm_dev = NULL; 322 322 priv->dp[dp->id] = NULL; 323 323 } 324 324 325 325 - static const struct component_ops dp_display_comp_ops = { 326 326 - .bind = dp_display_bind, 327 327 - .unbind = dp_display_unbind, 325 325 + static const struct component_ops msm_dp_display_comp_ops = { 326 326 + .bind = msm_dp_display_bind, 327 327 + .unbind = msm_dp_display_unbind, 328 328 }; 329 329 330 330 - static void dp_display_send_hpd_event(struct msm_dp *dp_display) 330 330 + static void msm_dp_display_send_hpd_event(struct msm_dp *msm_dp_display) 331 331 { 332 332 - struct dp_display_private *dp; 332 332 + struct msm_dp_display_private *dp; 333 333 struct drm_connector *connector; 334 334 335 335 - dp = container_of(dp_display, struct dp_display_private, dp_display); 335 335 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 336 336 337 337 - connector = dp->dp_display.connector; 337 337 + connector = dp->msm_dp_display.connector; 338 338 drm_helper_hpd_irq_event(connector->dev); 339 339 } 340 340 341 341 - static int dp_display_send_hpd_notification(struct dp_display_private *dp, 341 341 + static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *dp, 342 342 bool hpd) 343 343 { 344 344 - if ((hpd && dp->dp_display.link_ready) || 345 345 - (!hpd && !dp->dp_display.link_ready)) { 344 344 + if ((hpd && dp->msm_dp_display.link_ready) || 345 345 + (!hpd && !dp->msm_dp_display.link_ready)) { 346 346 drm_dbg_dp(dp->drm_dev, "HPD already %s\n", 347 347 (hpd ? "on" : "off")); 348 348 return 0; ··· 351 351 /* reset video pattern flag on disconnect */ 352 352 if (!hpd) { 353 353 dp->panel->video_test = false; 354 354 - if (!dp->dp_display.is_edp) 355 355 - drm_dp_set_subconnector_property(dp->dp_display.connector, 354 354 + if (!dp->msm_dp_display.is_edp) 355 355 + drm_dp_set_subconnector_property(dp->msm_dp_display.connector, 356 356 connector_status_disconnected, 357 357 dp->panel->dpcd, 358 358 dp->panel->downstream_ports); 359 359 } 360 360 361 361 - dp->dp_display.link_ready = hpd; 361 361 + dp->msm_dp_display.link_ready = hpd; 362 362 363 363 drm_dbg_dp(dp->drm_dev, "type=%d hpd=%d\n", 364 364 - dp->dp_display.connector_type, hpd); 365 365 - dp_display_send_hpd_event(&dp->dp_display); 364 364 + dp->msm_dp_display.connector_type, hpd); 365 365 + msm_dp_display_send_hpd_event(&dp->msm_dp_display); 366 366 367 367 return 0; 368 368 } 369 369 370 370 - static int dp_display_process_hpd_high(struct dp_display_private *dp) 370 370 + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp) 371 371 { 372 372 - struct drm_connector *connector = dp->dp_display.connector; 372 372 + struct drm_connector *connector = dp->msm_dp_display.connector; 373 373 const struct drm_display_info *info = &connector->display_info; 374 374 int rc = 0; 375 375 376 376 - rc = dp_panel_read_sink_caps(dp->panel, connector); 376 376 + rc = msm_dp_panel_read_sink_caps(dp->panel, connector); 377 377 if (rc) 378 378 goto end; 379 379 380 380 - dp_link_process_request(dp->link); 380 380 + msm_dp_link_process_request(dp->link); 381 381 382 382 - if (!dp->dp_display.is_edp) 382 382 + if (!dp->msm_dp_display.is_edp) 383 383 drm_dp_set_subconnector_property(connector, 384 384 connector_status_connected, 385 385 dp->panel->dpcd, 386 386 dp->panel->downstream_ports); 387 387 388 388 - dp->dp_display.psr_supported = dp->panel->psr_cap.version && psr_enabled; 388 388 + dp->msm_dp_display.psr_supported = dp->panel->psr_cap.version && psr_enabled; 389 389 390 390 dp->audio_supported = info->has_audio; 391 391 - dp_panel_handle_sink_request(dp->panel); 391 391 + msm_dp_panel_handle_sink_request(dp->panel); 392 392 393 393 /* 394 394 * set sink to normal operation mode -- D0 395 395 * before dpcd read 396 396 */ 397 397 - dp_link_psm_config(dp->link, &dp->panel->link_info, false); 397 397 + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, false); 398 398 399 399 - dp_link_reset_phy_params_vx_px(dp->link); 400 400 - rc = dp_ctrl_on_link(dp->ctrl); 399 399 + msm_dp_link_reset_phy_params_vx_px(dp->link); 400 400 + rc = msm_dp_ctrl_on_link(dp->ctrl); 401 401 if (rc) { 402 402 DRM_ERROR("failed to complete DP link training\n"); 403 403 goto end; 404 404 } 405 405 406 406 - dp_add_event(dp, EV_USER_NOTIFICATION, true, 0); 406 406 + msm_dp_add_event(dp, EV_USER_NOTIFICATION, true, 0); 407 407 408 408 end: 409 409 return rc; 410 410 } 411 411 412 412 - static void dp_display_host_phy_init(struct dp_display_private *dp) 412 412 + static void msm_dp_display_host_phy_init(struct msm_dp_display_private *dp) 413 413 { 414 414 drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", 415 415 - dp->dp_display.connector_type, dp->core_initialized, 415 415 + dp->msm_dp_display.connector_type, dp->core_initialized, 416 416 dp->phy_initialized); 417 417 418 418 if (!dp->phy_initialized) { 419 419 - dp_ctrl_phy_init(dp->ctrl); 419 419 + msm_dp_ctrl_phy_init(dp->ctrl); 420 420 dp->phy_initialized = true; 421 421 } 422 422 } 423 423 424 424 - static void dp_display_host_phy_exit(struct dp_display_private *dp) 424 424 + static void msm_dp_display_host_phy_exit(struct msm_dp_display_private *dp) 425 425 { 426 426 drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", 427 427 - dp->dp_display.connector_type, dp->core_initialized, 427 427 + dp->msm_dp_display.connector_type, dp->core_initialized, 428 428 dp->phy_initialized); 429 429 430 430 if (dp->phy_initialized) { 431 431 - dp_ctrl_phy_exit(dp->ctrl); 431 431 + msm_dp_ctrl_phy_exit(dp->ctrl); 432 432 dp->phy_initialized = false; 433 433 } 434 434 } 435 435 436 436 - static void dp_display_host_init(struct dp_display_private *dp) 436 436 + static void msm_dp_display_host_init(struct msm_dp_display_private *dp) 437 437 { 438 438 drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", 439 439 - dp->dp_display.connector_type, dp->core_initialized, 439 439 + dp->msm_dp_display.connector_type, dp->core_initialized, 440 440 dp->phy_initialized); 441 441 442 442 - dp_ctrl_core_clk_enable(dp->ctrl); 443 443 - dp_ctrl_reset_irq_ctrl(dp->ctrl, true); 444 444 - dp_aux_init(dp->aux); 442 442 + msm_dp_ctrl_core_clk_enable(dp->ctrl); 443 443 + msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, true); 444 444 + msm_dp_aux_init(dp->aux); 445 445 dp->core_initialized = true; 446 446 } 447 447 448 448 - static void dp_display_host_deinit(struct dp_display_private *dp) 448 448 + static void msm_dp_display_host_deinit(struct msm_dp_display_private *dp) 449 449 { 450 450 drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", 451 451 - dp->dp_display.connector_type, dp->core_initialized, 451 451 + dp->msm_dp_display.connector_type, dp->core_initialized, 452 452 dp->phy_initialized); 453 453 454 454 - dp_ctrl_reset_irq_ctrl(dp->ctrl, false); 455 455 - dp_aux_deinit(dp->aux); 456 456 - dp_ctrl_core_clk_disable(dp->ctrl); 454 454 + msm_dp_ctrl_reset_irq_ctrl(dp->ctrl, false); 455 455 + msm_dp_aux_deinit(dp->aux); 456 456 + msm_dp_ctrl_core_clk_disable(dp->ctrl); 457 457 dp->core_initialized = false; 458 458 } 459 459 460 460 - static int dp_display_usbpd_configure_cb(struct device *dev) 460 460 + static int msm_dp_display_usbpd_configure_cb(struct device *dev) 461 461 { 462 462 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 462 462 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 463 463 464 464 - dp_display_host_phy_init(dp); 464 464 + msm_dp_display_host_phy_init(dp); 465 465 466 466 - return dp_display_process_hpd_high(dp); 466 466 + return msm_dp_display_process_hpd_high(dp); 467 467 } 468 468 469 469 - static int dp_display_notify_disconnect(struct device *dev) 469 469 + static int msm_dp_display_notify_disconnect(struct device *dev) 470 470 { 471 471 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 471 471 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 472 472 473 473 - dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); 473 473 + msm_dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); 474 474 475 475 return 0; 476 476 } 477 477 478 478 - static void dp_display_handle_video_request(struct dp_display_private *dp) 478 478 + static void msm_dp_display_handle_video_request(struct msm_dp_display_private *dp) 479 479 { 480 480 if (dp->link->sink_request & DP_TEST_LINK_VIDEO_PATTERN) { 481 481 dp->panel->video_test = true; 482 482 - dp_link_send_test_response(dp->link); 482 482 + msm_dp_link_send_test_response(dp->link); 483 483 } 484 484 } 485 485 486 486 - static int dp_display_handle_port_status_changed(struct dp_display_private *dp) 486 486 + static int msm_dp_display_handle_port_status_changed(struct msm_dp_display_private *dp) 487 487 { 488 488 int rc = 0; 489 489 ··· 491 491 drm_dbg_dp(dp->drm_dev, "sink count is zero, nothing to do\n"); 492 492 if (dp->hpd_state != ST_DISCONNECTED) { 493 493 dp->hpd_state = ST_DISCONNECT_PENDING; 494 494 - dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); 494 494 + msm_dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); 495 495 } 496 496 } else { 497 497 if (dp->hpd_state == ST_DISCONNECTED) { 498 498 dp->hpd_state = ST_MAINLINK_READY; 499 499 - rc = dp_display_process_hpd_high(dp); 499 499 + rc = msm_dp_display_process_hpd_high(dp); 500 500 if (rc) 501 501 dp->hpd_state = ST_DISCONNECTED; 502 502 } ··· 505 505 return rc; 506 506 } 507 507 508 508 - static int dp_display_handle_irq_hpd(struct dp_display_private *dp) 508 508 + static int msm_dp_display_handle_irq_hpd(struct msm_dp_display_private *dp) 509 509 { 510 510 u32 sink_request = dp->link->sink_request; 511 511 ··· 519 519 } 520 520 } 521 521 522 522 - dp_ctrl_handle_sink_request(dp->ctrl); 522 522 + msm_dp_ctrl_handle_sink_request(dp->ctrl); 523 523 524 524 if (sink_request & DP_TEST_LINK_VIDEO_PATTERN) 525 525 - dp_display_handle_video_request(dp); 525 525 + msm_dp_display_handle_video_request(dp); 526 526 527 527 return 0; 528 528 } 529 529 530 530 - static int dp_display_usbpd_attention_cb(struct device *dev) 530 530 + static int msm_dp_display_usbpd_attention_cb(struct device *dev) 531 531 { 532 532 int rc = 0; 533 533 u32 sink_request; 534 534 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 534 534 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 535 535 536 536 /* check for any test request issued by sink */ 537 537 - rc = dp_link_process_request(dp->link); 537 537 + rc = msm_dp_link_process_request(dp->link); 538 538 if (!rc) { 539 539 sink_request = dp->link->sink_request; 540 540 drm_dbg_dp(dp->drm_dev, "hpd_state=%d sink_request=%d\n", 541 541 dp->hpd_state, sink_request); 542 542 if (sink_request & DS_PORT_STATUS_CHANGED) 543 543 - rc = dp_display_handle_port_status_changed(dp); 543 543 + rc = msm_dp_display_handle_port_status_changed(dp); 544 544 else 545 545 - rc = dp_display_handle_irq_hpd(dp); 545 545 + rc = msm_dp_display_handle_irq_hpd(dp); 546 546 } 547 547 548 548 return rc; 549 549 } 550 550 551 551 - static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) 551 551 + static int msm_dp_hpd_plug_handle(struct msm_dp_display_private *dp, u32 data) 552 552 { 553 553 u32 state; 554 554 int ret; 555 555 - struct platform_device *pdev = dp->dp_display.pdev; 555 555 + struct platform_device *pdev = dp->msm_dp_display.pdev; 556 556 557 557 - dp_aux_enable_xfers(dp->aux, true); 557 557 + msm_dp_aux_enable_xfers(dp->aux, true); 558 558 559 559 mutex_lock(&dp->event_mutex); 560 560 561 561 state = dp->hpd_state; 562 562 drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", 563 563 - dp->dp_display.connector_type, state); 563 563 + dp->msm_dp_display.connector_type, state); 564 564 565 565 if (state == ST_DISPLAY_OFF) { 566 566 mutex_unlock(&dp->event_mutex); ··· 574 574 575 575 if (state == ST_DISCONNECT_PENDING) { 576 576 /* wait until ST_DISCONNECTED */ 577 577 - dp_add_event(dp, EV_HPD_PLUG_INT, 0, 1); /* delay = 1 */ 577 577 + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 1); /* delay = 1 */ 578 578 mutex_unlock(&dp->event_mutex); 579 579 return 0; 580 580 } ··· 586 586 return ret; 587 587 } 588 588 589 589 - ret = dp_display_usbpd_configure_cb(&pdev->dev); 589 589 + ret = msm_dp_display_usbpd_configure_cb(&pdev->dev); 590 590 if (ret) { /* link train failed */ 591 591 dp->hpd_state = ST_DISCONNECTED; 592 592 pm_runtime_put_sync(&pdev->dev); ··· 595 595 } 596 596 597 597 drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", 598 598 - dp->dp_display.connector_type, state); 598 598 + dp->msm_dp_display.connector_type, state); 599 599 mutex_unlock(&dp->event_mutex); 600 600 601 601 /* uevent will complete connection part */ 602 602 return 0; 603 603 }; 604 604 605 605 - static void dp_display_handle_plugged_change(struct msm_dp *dp_display, 605 605 + static void msm_dp_display_handle_plugged_change(struct msm_dp *msm_dp_display, 606 606 bool plugged) 607 607 { 608 608 - struct dp_display_private *dp; 608 608 + struct msm_dp_display_private *dp; 609 609 610 610 - dp = container_of(dp_display, 611 611 - struct dp_display_private, dp_display); 610 610 + dp = container_of(msm_dp_display, 611 611 + struct msm_dp_display_private, msm_dp_display); 612 612 613 613 /* notify audio subsystem only if sink supports audio */ 614 614 - if (dp_display->plugged_cb && dp_display->codec_dev && 614 614 + if (msm_dp_display->plugged_cb && msm_dp_display->codec_dev && 615 615 dp->audio_supported) 616 616 - dp_display->plugged_cb(dp_display->codec_dev, plugged); 616 616 + msm_dp_display->plugged_cb(msm_dp_display->codec_dev, plugged); 617 617 } 618 618 619 619 - static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) 619 619 + static int msm_dp_hpd_unplug_handle(struct msm_dp_display_private *dp, u32 data) 620 620 { 621 621 u32 state; 622 622 - struct platform_device *pdev = dp->dp_display.pdev; 622 622 + struct platform_device *pdev = dp->msm_dp_display.pdev; 623 623 624 624 - dp_aux_enable_xfers(dp->aux, false); 624 624 + msm_dp_aux_enable_xfers(dp->aux, false); 625 625 626 626 mutex_lock(&dp->event_mutex); 627 627 628 628 state = dp->hpd_state; 629 629 630 630 drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", 631 631 - dp->dp_display.connector_type, state); 631 631 + dp->msm_dp_display.connector_type, state); 632 632 633 633 /* unplugged, no more irq_hpd handle */ 634 634 - dp_del_event(dp, EV_IRQ_HPD_INT); 634 634 + msm_dp_del_event(dp, EV_IRQ_HPD_INT); 635 635 636 636 if (state == ST_DISCONNECTED) { 637 637 /* triggered by irq_hdp with sink_count = 0 */ 638 638 if (dp->link->sink_count == 0) { 639 639 - dp_display_host_phy_exit(dp); 639 639 + msm_dp_display_host_phy_exit(dp); 640 640 } 641 641 - dp_display_notify_disconnect(&dp->dp_display.pdev->dev); 641 641 + msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); 642 642 mutex_unlock(&dp->event_mutex); 643 643 return 0; 644 644 } else if (state == ST_DISCONNECT_PENDING) { 645 645 mutex_unlock(&dp->event_mutex); 646 646 return 0; 647 647 } else if (state == ST_MAINLINK_READY) { 648 648 - dp_ctrl_off_link(dp->ctrl); 649 649 - dp_display_host_phy_exit(dp); 648 648 + msm_dp_ctrl_off_link(dp->ctrl); 649 649 + msm_dp_display_host_phy_exit(dp); 650 650 dp->hpd_state = ST_DISCONNECTED; 651 651 - dp_display_notify_disconnect(&dp->dp_display.pdev->dev); 651 651 + msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); 652 652 pm_runtime_put_sync(&pdev->dev); 653 653 mutex_unlock(&dp->event_mutex); 654 654 return 0; ··· 658 658 * We don't need separate work for disconnect as 659 659 * connect/attention interrupts are disabled 660 660 */ 661 661 - dp_display_notify_disconnect(&dp->dp_display.pdev->dev); 661 661 + msm_dp_display_notify_disconnect(&dp->msm_dp_display.pdev->dev); 662 662 663 663 if (state == ST_DISPLAY_OFF) { 664 664 dp->hpd_state = ST_DISCONNECTED; ··· 667 667 } 668 668 669 669 /* signal the disconnect event early to ensure proper teardown */ 670 670 - dp_display_handle_plugged_change(&dp->dp_display, false); 670 670 + msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); 671 671 672 672 drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", 673 673 - dp->dp_display.connector_type, state); 673 673 + dp->msm_dp_display.connector_type, state); 674 674 675 675 /* uevent will complete disconnection part */ 676 676 pm_runtime_put_sync(&pdev->dev); ··· 678 678 return 0; 679 679 } 680 680 681 681 - static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) 681 681 + static int msm_dp_irq_hpd_handle(struct msm_dp_display_private *dp, u32 data) 682 682 { 683 683 u32 state; 684 684 ··· 687 687 /* irq_hpd can happen at either connected or disconnected state */ 688 688 state = dp->hpd_state; 689 689 drm_dbg_dp(dp->drm_dev, "Before, type=%d hpd_state=%d\n", 690 690 - dp->dp_display.connector_type, state); 690 690 + dp->msm_dp_display.connector_type, state); 691 691 692 692 if (state == ST_DISPLAY_OFF) { 693 693 mutex_unlock(&dp->event_mutex); ··· 696 696 697 697 if (state == ST_MAINLINK_READY || state == ST_DISCONNECT_PENDING) { 698 698 /* wait until ST_CONNECTED */ 699 699 - dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */ 699 699 + msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */ 700 700 mutex_unlock(&dp->event_mutex); 701 701 return 0; 702 702 } 703 703 704 704 - dp_display_usbpd_attention_cb(&dp->dp_display.pdev->dev); 704 704 + msm_dp_display_usbpd_attention_cb(&dp->msm_dp_display.pdev->dev); 705 705 706 706 drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", 707 707 - dp->dp_display.connector_type, state); 707 707 + dp->msm_dp_display.connector_type, state); 708 708 709 709 mutex_unlock(&dp->event_mutex); 710 710 711 711 return 0; 712 712 } 713 713 714 714 - static void dp_display_deinit_sub_modules(struct dp_display_private *dp) 714 714 + static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_private *dp) 715 715 { 716 716 - dp_audio_put(dp->audio); 717 717 - dp_panel_put(dp->panel); 718 718 - dp_aux_put(dp->aux); 716 716 + msm_dp_audio_put(dp->audio); 717 717 + msm_dp_panel_put(dp->panel); 718 718 + msm_dp_aux_put(dp->aux); 719 719 } 720 720 721 721 - static int dp_init_sub_modules(struct dp_display_private *dp) 721 721 + static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) 722 722 { 723 723 int rc = 0; 724 724 - struct device *dev = &dp->dp_display.pdev->dev; 725 725 - struct dp_panel_in panel_in = { 724 724 + struct device *dev = &dp->msm_dp_display.pdev->dev; 725 725 + struct msm_dp_panel_in panel_in = { 726 726 .dev = dev, 727 727 }; 728 728 struct phy *phy; ··· 732 732 return PTR_ERR(phy); 733 733 734 734 rc = phy_set_mode_ext(phy, PHY_MODE_DP, 735 735 - dp->dp_display.is_edp ? PHY_SUBMODE_EDP : PHY_SUBMODE_DP); 735 735 + dp->msm_dp_display.is_edp ? PHY_SUBMODE_EDP : PHY_SUBMODE_DP); 736 736 if (rc) { 737 737 DRM_ERROR("failed to set phy submode, rc = %d\n", rc); 738 738 dp->catalog = NULL; 739 739 goto error; 740 740 } 741 741 742 742 - dp->catalog = dp_catalog_get(dev); 742 742 + dp->catalog = msm_dp_catalog_get(dev); 743 743 if (IS_ERR(dp->catalog)) { 744 744 rc = PTR_ERR(dp->catalog); 745 745 DRM_ERROR("failed to initialize catalog, rc = %d\n", rc); ··· 747 747 goto error; 748 748 } 749 749 750 750 - dp->aux = dp_aux_get(dev, dp->catalog, 750 750 + dp->aux = msm_dp_aux_get(dev, dp->catalog, 751 751 phy, 752 752 - dp->dp_display.is_edp); 752 752 + dp->msm_dp_display.is_edp); 753 753 if (IS_ERR(dp->aux)) { 754 754 rc = PTR_ERR(dp->aux); 755 755 DRM_ERROR("failed to initialize aux, rc = %d\n", rc); ··· 757 757 goto error; 758 758 } 759 759 760 760 - dp->link = dp_link_get(dev, dp->aux); 760 760 + dp->link = msm_dp_link_get(dev, dp->aux); 761 761 if (IS_ERR(dp->link)) { 762 762 rc = PTR_ERR(dp->link); 763 763 DRM_ERROR("failed to initialize link, rc = %d\n", rc); ··· 769 769 panel_in.catalog = dp->catalog; 770 770 panel_in.link = dp->link; 771 771 772 772 - dp->panel = dp_panel_get(&panel_in); 772 772 + dp->panel = msm_dp_panel_get(&panel_in); 773 773 if (IS_ERR(dp->panel)) { 774 774 rc = PTR_ERR(dp->panel); 775 775 DRM_ERROR("failed to initialize panel, rc = %d\n", rc); ··· 777 777 goto error_link; 778 778 } 779 779 780 780 - dp->ctrl = dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, 780 780 + dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, 781 781 dp->catalog, 782 782 phy); 783 783 if (IS_ERR(dp->ctrl)) { ··· 787 787 goto error_ctrl; 788 788 } 789 789 790 790 - dp->audio = dp_audio_get(dp->dp_display.pdev, dp->panel, dp->catalog); 790 790 + dp->audio = msm_dp_audio_get(dp->msm_dp_display.pdev, dp->panel, dp->catalog); 791 791 if (IS_ERR(dp->audio)) { 792 792 rc = PTR_ERR(dp->audio); 793 793 pr_err("failed to initialize audio, rc = %d\n", rc); ··· 798 798 return rc; 799 799 800 800 error_ctrl: 801 801 - dp_panel_put(dp->panel); 801 801 + msm_dp_panel_put(dp->panel); 802 802 error_link: 803 803 - dp_aux_put(dp->aux); 803 803 + msm_dp_aux_put(dp->aux); 804 804 error: 805 805 return rc; 806 806 } 807 807 808 808 - static int dp_display_set_mode(struct msm_dp *dp_display, 809 809 - struct dp_display_mode *mode) 808 808 + static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, 809 809 + struct msm_dp_display_mode *mode) 810 810 { 811 811 - struct dp_display_private *dp; 811 811 + struct msm_dp_display_private *dp; 812 812 813 813 - dp = container_of(dp_display, struct dp_display_private, dp_display); 813 813 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 814 814 815 815 - drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode); 816 816 - dp->panel->dp_mode.bpp = mode->bpp; 817 817 - dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; 818 818 - dp_panel_init_panel_info(dp->panel); 815 815 + drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); 816 816 + dp->panel->msm_dp_mode.bpp = mode->bpp; 817 817 + dp->panel->msm_dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; 818 818 + msm_dp_panel_init_panel_info(dp->panel); 819 819 return 0; 820 820 } 821 821 822 822 - static int dp_display_enable(struct dp_display_private *dp, bool force_link_train) 822 822 + static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool force_link_train) 823 823 { 824 824 int rc = 0; 825 825 - struct msm_dp *dp_display = &dp->dp_display; 825 825 + struct msm_dp *msm_dp_display = &dp->msm_dp_display; 826 826 827 827 drm_dbg_dp(dp->drm_dev, "sink_count=%d\n", dp->link->sink_count); 828 828 - if (dp_display->power_on) { 828 828 + if (msm_dp_display->power_on) { 829 829 drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); 830 830 return 0; 831 831 } 832 832 833 833 - rc = dp_ctrl_on_stream(dp->ctrl, force_link_train); 833 833 + rc = msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); 834 834 if (!rc) 835 835 - dp_display->power_on = true; 835 835 + msm_dp_display->power_on = true; 836 836 837 837 return rc; 838 838 } 839 839 840 840 - static int dp_display_post_enable(struct msm_dp *dp_display) 840 840 + static int msm_dp_display_post_enable(struct msm_dp *msm_dp_display) 841 841 { 842 842 - struct dp_display_private *dp; 842 842 + struct msm_dp_display_private *dp; 843 843 u32 rate; 844 844 845 845 - dp = container_of(dp_display, struct dp_display_private, dp_display); 845 845 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 846 846 847 847 rate = dp->link->link_params.rate; 848 848 ··· 852 852 } 853 853 854 854 /* signal the connect event late to synchronize video and display */ 855 855 - dp_display_handle_plugged_change(dp_display, true); 855 855 + msm_dp_display_handle_plugged_change(msm_dp_display, true); 856 856 857 857 - if (dp_display->psr_supported) 858 858 - dp_ctrl_config_psr(dp->ctrl); 857 857 + if (msm_dp_display->psr_supported) 858 858 + msm_dp_ctrl_config_psr(dp->ctrl); 859 859 860 860 return 0; 861 861 } 862 862 863 863 - static int dp_display_disable(struct dp_display_private *dp) 863 863 + static int msm_dp_display_disable(struct msm_dp_display_private *dp) 864 864 { 865 865 - struct msm_dp *dp_display = &dp->dp_display; 865 865 + struct msm_dp *msm_dp_display = &dp->msm_dp_display; 866 866 867 867 - if (!dp_display->power_on) 867 867 + if (!msm_dp_display->power_on) 868 868 return 0; 869 869 870 870 /* wait only if audio was enabled */ 871 871 - if (dp_display->audio_enabled) { 871 871 + if (msm_dp_display->audio_enabled) { 872 872 /* signal the disconnect event */ 873 873 - dp_display_handle_plugged_change(dp_display, false); 873 873 + msm_dp_display_handle_plugged_change(msm_dp_display, false); 874 874 if (!wait_for_completion_timeout(&dp->audio_comp, 875 875 HZ * 5)) 876 876 DRM_ERROR("audio comp timeout\n"); 877 877 } 878 878 879 879 - dp_display->audio_enabled = false; 879 879 + msm_dp_display->audio_enabled = false; 880 880 881 881 if (dp->link->sink_count == 0) { 882 882 /* 883 883 * irq_hpd with sink_count = 0 884 884 * hdmi unplugged out of dongle 885 885 */ 886 886 - dp_ctrl_off_link_stream(dp->ctrl); 886 886 + msm_dp_ctrl_off_link_stream(dp->ctrl); 887 887 } else { 888 888 /* 889 889 * unplugged interrupt 890 890 * dongle unplugged out of DUT 891 891 */ 892 892 - dp_ctrl_off(dp->ctrl); 893 893 - dp_display_host_phy_exit(dp); 892 892 + msm_dp_ctrl_off(dp->ctrl); 893 893 + msm_dp_display_host_phy_exit(dp); 894 894 } 895 895 896 896 - dp_display->power_on = false; 896 896 + msm_dp_display->power_on = false; 897 897 898 898 drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); 899 899 return 0; 900 900 } 901 901 902 902 - int dp_display_set_plugged_cb(struct msm_dp *dp_display, 902 902 + int msm_dp_display_set_plugged_cb(struct msm_dp *msm_dp_display, 903 903 hdmi_codec_plugged_cb fn, struct device *codec_dev) 904 904 { 905 905 bool plugged; 906 906 907 907 - dp_display->plugged_cb = fn; 908 908 - dp_display->codec_dev = codec_dev; 909 909 - plugged = dp_display->link_ready; 910 910 - dp_display_handle_plugged_change(dp_display, plugged); 907 907 + msm_dp_display->plugged_cb = fn; 908 908 + msm_dp_display->codec_dev = codec_dev; 909 909 + plugged = msm_dp_display->link_ready; 910 910 + msm_dp_display_handle_plugged_change(msm_dp_display, plugged); 911 911 912 912 return 0; 913 913 } 914 914 915 915 /** 916 916 - * dp_bridge_mode_valid - callback to determine if specified mode is valid 916 916 + * msm_dp_bridge_mode_valid - callback to determine if specified mode is valid 917 917 * @bridge: Pointer to drm bridge structure 918 918 * @info: display info 919 919 * @mode: Pointer to drm mode structure 920 920 * Returns: Validity status for specified mode 921 921 */ 922 922 - enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, 922 922 + enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, 923 923 const struct drm_display_info *info, 924 924 const struct drm_display_mode *mode) 925 925 { 926 926 const u32 num_components = 3, default_bpp = 24; 927 927 - struct dp_display_private *dp_display; 928 928 - struct dp_link_info *link_info; 927 927 + struct msm_dp_display_private *msm_dp_display; 928 928 + struct msm_dp_link_info *link_info; 929 929 u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0; 930 930 struct msm_dp *dp; 931 931 int mode_pclk_khz = mode->clock; 932 932 933 933 - dp = to_dp_bridge(bridge)->dp_display; 933 933 + dp = to_dp_bridge(bridge)->msm_dp_display; 934 934 935 935 if (!dp || !mode_pclk_khz || !dp->connector) { 936 936 DRM_ERROR("invalid params\n"); ··· 940 940 if (mode->clock > DP_MAX_PIXEL_CLK_KHZ) 941 941 return MODE_CLOCK_HIGH; 942 942 943 943 - dp_display = container_of(dp, struct dp_display_private, dp_display); 944 944 - link_info = &dp_display->panel->link_info; 943 943 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 944 944 + link_info = &msm_dp_display->panel->link_info; 945 945 946 946 if (drm_mode_is_420_only(&dp->connector->display_info, mode) && 947 947 - dp_display->panel->vsc_sdp_supported) 947 947 + msm_dp_display->panel->vsc_sdp_supported) 948 948 mode_pclk_khz /= 2; 949 949 950 950 mode_bpp = dp->connector->display_info.bpc * num_components; 951 951 if (!mode_bpp) 952 952 mode_bpp = default_bpp; 953 953 954 954 - mode_bpp = dp_panel_get_mode_bpp(dp_display->panel, 954 954 + mode_bpp = msm_dp_panel_get_mode_bpp(msm_dp_display->panel, 955 955 mode_bpp, mode_pclk_khz); 956 956 957 957 mode_rate_khz = mode_pclk_khz * mode_bpp; ··· 963 963 return MODE_OK; 964 964 } 965 965 966 966 - int dp_display_get_modes(struct msm_dp *dp) 966 966 + int msm_dp_display_get_modes(struct msm_dp *dp) 967 967 { 968 968 - struct dp_display_private *dp_display; 968 968 + struct msm_dp_display_private *msm_dp_display; 969 969 970 970 if (!dp) { 971 971 DRM_ERROR("invalid params\n"); 972 972 return 0; 973 973 } 974 974 975 975 - dp_display = container_of(dp, struct dp_display_private, dp_display); 975 975 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 976 976 977 977 - return dp_panel_get_modes(dp_display->panel, 977 977 + return msm_dp_panel_get_modes(msm_dp_display->panel, 978 978 dp->connector); 979 979 } 980 980 981 981 - bool dp_display_check_video_test(struct msm_dp *dp) 981 981 + bool msm_dp_display_check_video_test(struct msm_dp *dp) 982 982 { 983 983 - struct dp_display_private *dp_display; 983 983 + struct msm_dp_display_private *msm_dp_display; 984 984 985 985 - dp_display = container_of(dp, struct dp_display_private, dp_display); 985 985 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 986 986 987 987 - return dp_display->panel->video_test; 987 987 + return msm_dp_display->panel->video_test; 988 988 } 989 989 990 990 - int dp_display_get_test_bpp(struct msm_dp *dp) 990 990 + int msm_dp_display_get_test_bpp(struct msm_dp *dp) 991 991 { 992 992 - struct dp_display_private *dp_display; 992 992 + struct msm_dp_display_private *msm_dp_display; 993 993 994 994 if (!dp) { 995 995 DRM_ERROR("invalid params\n"); 996 996 return 0; 997 997 } 998 998 999 999 - dp_display = container_of(dp, struct dp_display_private, dp_display); 999 999 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1000 1000 1001 1001 - return dp_link_bit_depth_to_bpp( 1002 1002 - dp_display->link->test_video.test_bit_depth); 1001 1001 + return msm_dp_link_bit_depth_to_bpp( 1002 1002 + msm_dp_display->link->test_video.test_bit_depth); 1003 1003 } 1004 1004 1005 1005 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) 1006 1006 { 1007 1007 - struct dp_display_private *dp_display; 1007 1007 + struct msm_dp_display_private *msm_dp_display; 1008 1008 1009 1009 - dp_display = container_of(dp, struct dp_display_private, dp_display); 1009 1009 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1010 1010 1011 1011 /* 1012 1012 * if we are reading registers we need the link clocks to be on ··· 1015 1015 * power_on status before dumping DP registers to avoid crash due 1016 1016 * to unclocked access 1017 1017 */ 1018 1018 - mutex_lock(&dp_display->event_mutex); 1018 1018 + mutex_lock(&msm_dp_display->event_mutex); 1019 1019 1020 1020 if (!dp->power_on) { 1021 1021 - mutex_unlock(&dp_display->event_mutex); 1021 1021 + mutex_unlock(&msm_dp_display->event_mutex); 1022 1022 return; 1023 1023 } 1024 1024 1025 1025 - dp_catalog_snapshot(dp_display->catalog, disp_state); 1025 1025 + msm_dp_catalog_snapshot(msm_dp_display->catalog, disp_state); 1026 1026 1027 1027 - mutex_unlock(&dp_display->event_mutex); 1027 1027 + mutex_unlock(&msm_dp_display->event_mutex); 1028 1028 } 1029 1029 1030 1030 - void dp_display_set_psr(struct msm_dp *dp_display, bool enter) 1030 1030 + void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) 1031 1031 { 1032 1032 - struct dp_display_private *dp; 1032 1032 + struct msm_dp_display_private *dp; 1033 1033 1034 1034 - if (!dp_display) { 1034 1034 + if (!msm_dp_display) { 1035 1035 DRM_ERROR("invalid params\n"); 1036 1036 return; 1037 1037 } 1038 1038 1039 1039 - dp = container_of(dp_display, struct dp_display_private, dp_display); 1040 1040 - dp_ctrl_set_psr(dp->ctrl, enter); 1039 1039 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1040 1040 + msm_dp_ctrl_set_psr(dp->ctrl, enter); 1041 1041 } 1042 1042 1043 1043 static int hpd_event_thread(void *data) 1044 1044 { 1045 1045 - struct dp_display_private *dp_priv; 1045 1045 + struct msm_dp_display_private *msm_dp_priv; 1046 1046 unsigned long flag; 1047 1047 - struct dp_event *todo; 1047 1047 + struct msm_dp_event *todo; 1048 1048 int timeout_mode = 0; 1049 1049 1050 1050 - dp_priv = (struct dp_display_private *)data; 1050 1050 + msm_dp_priv = (struct msm_dp_display_private *)data; 1051 1051 1052 1052 while (1) { 1053 1053 if (timeout_mode) { 1054 1054 - wait_event_timeout(dp_priv->event_q, 1055 1055 - (dp_priv->event_pndx == dp_priv->event_gndx) || 1054 1054 + wait_event_timeout(msm_dp_priv->event_q, 1055 1055 + (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) || 1056 1056 kthread_should_stop(), EVENT_TIMEOUT); 1057 1057 } else { 1058 1058 - wait_event_interruptible(dp_priv->event_q, 1059 1059 - (dp_priv->event_pndx != dp_priv->event_gndx) || 1058 1058 + wait_event_interruptible(msm_dp_priv->event_q, 1059 1059 + (msm_dp_priv->event_pndx != msm_dp_priv->event_gndx) || 1060 1060 kthread_should_stop()); 1061 1061 } 1062 1062 1063 1063 if (kthread_should_stop()) 1064 1064 break; 1065 1065 1066 1066 - spin_lock_irqsave(&dp_priv->event_lock, flag); 1067 1067 - todo = &dp_priv->event_list[dp_priv->event_gndx]; 1066 1066 + spin_lock_irqsave(&msm_dp_priv->event_lock, flag); 1067 1067 + todo = &msm_dp_priv->event_list[msm_dp_priv->event_gndx]; 1068 1068 if (todo->delay) { 1069 1069 - struct dp_event *todo_next; 1069 1069 + struct msm_dp_event *todo_next; 1070 1070 1071 1071 - dp_priv->event_gndx++; 1072 1072 - dp_priv->event_gndx %= DP_EVENT_Q_MAX; 1071 1071 + msm_dp_priv->event_gndx++; 1072 1072 + msm_dp_priv->event_gndx %= DP_EVENT_Q_MAX; 1073 1073 1074 1074 /* re enter delay event into q */ 1075 1075 - todo_next = &dp_priv->event_list[dp_priv->event_pndx++]; 1076 1076 - dp_priv->event_pndx %= DP_EVENT_Q_MAX; 1075 1075 + todo_next = &msm_dp_priv->event_list[msm_dp_priv->event_pndx++]; 1076 1076 + msm_dp_priv->event_pndx %= DP_EVENT_Q_MAX; 1077 1077 todo_next->event_id = todo->event_id; 1078 1078 todo_next->data = todo->data; 1079 1079 todo_next->delay = todo->delay - 1; ··· 1084 1084 1085 1085 /* switch to timeout mode */ 1086 1086 timeout_mode = 1; 1087 1087 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 1087 1087 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 1088 1088 continue; 1089 1089 } 1090 1090 1091 1091 /* timeout with no events in q */ 1092 1092 - if (dp_priv->event_pndx == dp_priv->event_gndx) { 1093 1093 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 1092 1092 + if (msm_dp_priv->event_pndx == msm_dp_priv->event_gndx) { 1093 1093 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 1094 1094 continue; 1095 1095 } 1096 1096 1097 1097 - dp_priv->event_gndx++; 1098 1098 - dp_priv->event_gndx %= DP_EVENT_Q_MAX; 1097 1097 + msm_dp_priv->event_gndx++; 1098 1098 + msm_dp_priv->event_gndx %= DP_EVENT_Q_MAX; 1099 1099 timeout_mode = 0; 1100 1100 - spin_unlock_irqrestore(&dp_priv->event_lock, flag); 1100 1100 + spin_unlock_irqrestore(&msm_dp_priv->event_lock, flag); 1101 1101 1102 1102 switch (todo->event_id) { 1103 1103 case EV_HPD_PLUG_INT: 1104 1104 - dp_hpd_plug_handle(dp_priv, todo->data); 1104 1104 + msm_dp_hpd_plug_handle(msm_dp_priv, todo->data); 1105 1105 break; 1106 1106 case EV_HPD_UNPLUG_INT: 1107 1107 - dp_hpd_unplug_handle(dp_priv, todo->data); 1107 1107 + msm_dp_hpd_unplug_handle(msm_dp_priv, todo->data); 1108 1108 break; 1109 1109 case EV_IRQ_HPD_INT: 1110 1110 - dp_irq_hpd_handle(dp_priv, todo->data); 1110 1110 + msm_dp_irq_hpd_handle(msm_dp_priv, todo->data); 1111 1111 break; 1112 1112 case EV_USER_NOTIFICATION: 1113 1113 - dp_display_send_hpd_notification(dp_priv, 1113 1113 + msm_dp_display_send_hpd_notification(msm_dp_priv, 1114 1114 todo->data); 1115 1115 break; 1116 1116 default: ··· 1121 1121 return 0; 1122 1122 } 1123 1123 1124 1124 - static int dp_hpd_event_thread_start(struct dp_display_private *dp_priv) 1124 1124 + static int msm_dp_hpd_event_thread_start(struct msm_dp_display_private *msm_dp_priv) 1125 1125 { 1126 1126 /* set event q to empty */ 1127 1127 - dp_priv->event_gndx = 0; 1128 1128 - dp_priv->event_pndx = 0; 1127 1127 + msm_dp_priv->event_gndx = 0; 1128 1128 + msm_dp_priv->event_pndx = 0; 1129 1129 1130 1130 - dp_priv->ev_tsk = kthread_run(hpd_event_thread, dp_priv, "dp_hpd_handler"); 1131 1131 - if (IS_ERR(dp_priv->ev_tsk)) 1132 1132 - return PTR_ERR(dp_priv->ev_tsk); 1130 1130 + msm_dp_priv->ev_tsk = kthread_run(hpd_event_thread, msm_dp_priv, "dp_hpd_handler"); 1131 1131 + if (IS_ERR(msm_dp_priv->ev_tsk)) 1132 1132 + return PTR_ERR(msm_dp_priv->ev_tsk); 1133 1133 1134 1134 return 0; 1135 1135 } 1136 1136 1137 1137 - static irqreturn_t dp_display_irq_handler(int irq, void *dev_id) 1137 1137 + static irqreturn_t msm_dp_display_irq_handler(int irq, void *dev_id) 1138 1138 { 1139 1139 - struct dp_display_private *dp = dev_id; 1139 1139 + struct msm_dp_display_private *dp = dev_id; 1140 1140 irqreturn_t ret = IRQ_NONE; 1141 1141 u32 hpd_isr_status; 1142 1142 ··· 1145 1145 return IRQ_NONE; 1146 1146 } 1147 1147 1148 1148 - hpd_isr_status = dp_catalog_hpd_get_intr_status(dp->catalog); 1148 1148 + hpd_isr_status = msm_dp_catalog_hpd_get_intr_status(dp->catalog); 1149 1149 1150 1150 if (hpd_isr_status & 0x0F) { 1151 1151 drm_dbg_dp(dp->drm_dev, "type=%d isr=0x%x\n", 1152 1152 - dp->dp_display.connector_type, hpd_isr_status); 1152 1152 + dp->msm_dp_display.connector_type, hpd_isr_status); 1153 1153 /* hpd related interrupts */ 1154 1154 if (hpd_isr_status & DP_DP_HPD_PLUG_INT_MASK) 1155 1155 - dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); 1155 1155 + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); 1156 1156 1157 1157 if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { 1158 1158 - dp_add_event(dp, EV_IRQ_HPD_INT, 0, 0); 1158 1158 + msm_dp_add_event(dp, EV_IRQ_HPD_INT, 0, 0); 1159 1159 } 1160 1160 1161 1161 if (hpd_isr_status & DP_DP_HPD_REPLUG_INT_MASK) { 1162 1162 - dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1163 1163 - dp_add_event(dp, EV_HPD_PLUG_INT, 0, 3); 1162 1162 + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1163 1163 + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 3); 1164 1164 } 1165 1165 1166 1166 if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) 1167 1167 - dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1167 1167 + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1168 1168 1169 1169 ret = IRQ_HANDLED; 1170 1170 } 1171 1171 1172 1172 /* DP controller isr */ 1173 1173 - ret |= dp_ctrl_isr(dp->ctrl); 1173 1173 + ret |= msm_dp_ctrl_isr(dp->ctrl); 1174 1174 1175 1175 /* DP aux isr */ 1176 1176 - ret |= dp_aux_isr(dp->aux); 1176 1176 + ret |= msm_dp_aux_isr(dp->aux); 1177 1177 1178 1178 return ret; 1179 1179 } 1180 1180 1181 1181 - static int dp_display_request_irq(struct dp_display_private *dp) 1181 1181 + static int msm_dp_display_request_irq(struct msm_dp_display_private *dp) 1182 1182 { 1183 1183 int rc = 0; 1184 1184 - struct platform_device *pdev = dp->dp_display.pdev; 1184 1184 + struct platform_device *pdev = dp->msm_dp_display.pdev; 1185 1185 1186 1186 dp->irq = platform_get_irq(pdev, 0); 1187 1187 if (dp->irq < 0) { ··· 1189 1189 return dp->irq; 1190 1190 } 1191 1191 1192 1192 - rc = devm_request_irq(&pdev->dev, dp->irq, dp_display_irq_handler, 1192 1192 + rc = devm_request_irq(&pdev->dev, dp->irq, msm_dp_display_irq_handler, 1193 1193 IRQF_TRIGGER_HIGH|IRQF_NO_AUTOEN, 1194 1194 "dp_display_isr", dp); 1195 1195 ··· 1202 1202 return 0; 1203 1203 } 1204 1204 1205 1205 - static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pdev) 1205 1205 + static const struct msm_dp_desc *msm_dp_display_get_desc(struct platform_device *pdev) 1206 1206 { 1207 1207 const struct msm_dp_desc *descs = of_device_get_match_data(&pdev->dev); 1208 1208 struct resource *res; ··· 1221 1221 return NULL; 1222 1222 } 1223 1223 1224 1224 - static int dp_display_probe_tail(struct device *dev) 1224 1224 + static int msm_dp_display_probe_tail(struct device *dev) 1225 1225 { 1226 1226 struct msm_dp *dp = dev_get_drvdata(dev); 1227 1227 int ret; ··· 1241 1241 return ret; 1242 1242 } 1243 1243 1244 1244 - ret = component_add(dev, &dp_display_comp_ops); 1244 1244 + ret = component_add(dev, &msm_dp_display_comp_ops); 1245 1245 if (ret) 1246 1246 DRM_ERROR("component add failed, rc=%d\n", ret); 1247 1247 1248 1248 return ret; 1249 1249 } 1250 1250 1251 1251 - static int dp_auxbus_done_probe(struct drm_dp_aux *aux) 1251 1251 + static int msm_dp_auxbus_done_probe(struct drm_dp_aux *aux) 1252 1252 { 1253 1253 - return dp_display_probe_tail(aux->dev); 1253 1253 + return msm_dp_display_probe_tail(aux->dev); 1254 1254 } 1255 1255 1256 1256 - static int dp_display_get_connector_type(struct platform_device *pdev, 1256 1256 + static int msm_dp_display_get_connector_type(struct platform_device *pdev, 1257 1257 const struct msm_dp_desc *desc) 1258 1258 { 1259 1259 struct device_node *node = pdev->dev.of_node; ··· 1272 1272 return connector_type; 1273 1273 } 1274 1274 1275 1275 - static int dp_display_probe(struct platform_device *pdev) 1275 1275 + static int msm_dp_display_probe(struct platform_device *pdev) 1276 1276 { 1277 1277 int rc = 0; 1278 1278 - struct dp_display_private *dp; 1278 1278 + struct msm_dp_display_private *dp; 1279 1279 const struct msm_dp_desc *desc; 1280 1280 1281 1281 if (!pdev || !pdev->dev.of_node) { ··· 1287 1287 if (!dp) 1288 1288 return -ENOMEM; 1289 1289 1290 1290 - desc = dp_display_get_desc(pdev); 1290 1290 + desc = msm_dp_display_get_desc(pdev); 1291 1291 if (!desc) 1292 1292 return -EINVAL; 1293 1293 1294 1294 - dp->dp_display.pdev = pdev; 1294 1294 + dp->msm_dp_display.pdev = pdev; 1295 1295 dp->id = desc->id; 1296 1296 - dp->dp_display.connector_type = dp_display_get_connector_type(pdev, desc); 1296 1296 + dp->msm_dp_display.connector_type = msm_dp_display_get_connector_type(pdev, desc); 1297 1297 dp->wide_bus_supported = desc->wide_bus_supported; 1298 1298 - dp->dp_display.is_edp = 1299 1299 - (dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); 1298 1298 + dp->msm_dp_display.is_edp = 1299 1299 + (dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); 1300 1300 1301 1301 - rc = dp_init_sub_modules(dp); 1301 1301 + rc = msm_dp_init_sub_modules(dp); 1302 1302 if (rc) { 1303 1303 DRM_ERROR("init sub module failed\n"); 1304 1304 return -EPROBE_DEFER; ··· 1310 1310 spin_lock_init(&dp->event_lock); 1311 1311 1312 1312 /* Store DP audio handle inside DP display */ 1313 1313 - dp->dp_display.dp_audio = dp->audio; 1313 1313 + dp->msm_dp_display.msm_dp_audio = dp->audio; 1314 1314 1315 1315 init_completion(&dp->audio_comp); 1316 1316 1317 1317 - platform_set_drvdata(pdev, &dp->dp_display); 1317 1317 + platform_set_drvdata(pdev, &dp->msm_dp_display); 1318 1318 1319 1319 rc = devm_pm_runtime_enable(&pdev->dev); 1320 1320 if (rc) 1321 1321 goto err; 1322 1322 1323 1323 - rc = dp_display_request_irq(dp); 1323 1323 + rc = msm_dp_display_request_irq(dp); 1324 1324 if (rc) 1325 1325 goto err; 1326 1326 1327 1327 - if (dp->dp_display.is_edp) { 1328 1328 - rc = devm_of_dp_aux_populate_bus(dp->aux, dp_auxbus_done_probe); 1327 1327 + if (dp->msm_dp_display.is_edp) { 1328 1328 + rc = devm_of_dp_aux_populate_bus(dp->aux, msm_dp_auxbus_done_probe); 1329 1329 if (rc) { 1330 1330 DRM_ERROR("eDP auxbus population failed, rc=%d\n", rc); 1331 1331 goto err; 1332 1332 } 1333 1333 } else { 1334 1334 - rc = dp_display_probe_tail(&pdev->dev); 1334 1334 + rc = msm_dp_display_probe_tail(&pdev->dev); 1335 1335 if (rc) 1336 1336 goto err; 1337 1337 } ··· 1339 1339 return rc; 1340 1340 1341 1341 err: 1342 1342 - dp_display_deinit_sub_modules(dp); 1342 1342 + msm_dp_display_deinit_sub_modules(dp); 1343 1343 return rc; 1344 1344 } 1345 1345 1346 1346 - static void dp_display_remove(struct platform_device *pdev) 1346 1346 + static void msm_dp_display_remove(struct platform_device *pdev) 1347 1347 { 1348 1348 - struct dp_display_private *dp = dev_get_dp_display_private(&pdev->dev); 1348 1348 + struct msm_dp_display_private *dp = dev_get_dp_display_private(&pdev->dev); 1349 1349 1350 1350 - component_del(&pdev->dev, &dp_display_comp_ops); 1351 1351 - dp_display_deinit_sub_modules(dp); 1350 1350 + component_del(&pdev->dev, &msm_dp_display_comp_ops); 1351 1351 + msm_dp_display_deinit_sub_modules(dp); 1352 1352 platform_set_drvdata(pdev, NULL); 1353 1353 } 1354 1354 1355 1355 - static int dp_pm_runtime_suspend(struct device *dev) 1355 1355 + static int msm_dp_pm_runtime_suspend(struct device *dev) 1356 1356 { 1357 1357 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 1357 1357 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 1358 1358 1359 1359 disable_irq(dp->irq); 1360 1360 1361 1361 - if (dp->dp_display.is_edp) { 1362 1362 - dp_display_host_phy_exit(dp); 1363 1363 - dp_catalog_ctrl_hpd_disable(dp->catalog); 1361 1361 + if (dp->msm_dp_display.is_edp) { 1362 1362 + msm_dp_display_host_phy_exit(dp); 1363 1363 + msm_dp_catalog_ctrl_hpd_disable(dp->catalog); 1364 1364 } 1365 1365 - dp_display_host_deinit(dp); 1365 1365 + msm_dp_display_host_deinit(dp); 1366 1366 1367 1367 return 0; 1368 1368 } 1369 1369 1370 1370 - static int dp_pm_runtime_resume(struct device *dev) 1370 1370 + static int msm_dp_pm_runtime_resume(struct device *dev) 1371 1371 { 1372 1372 - struct dp_display_private *dp = dev_get_dp_display_private(dev); 1372 1372 + struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); 1373 1373 1374 1374 /* 1375 1375 * for eDP, host cotroller, HPD block and PHY are enabled here 1376 1376 * but with HPD irq disabled 1377 1377 * 1378 1378 * for DP, only host controller is enabled here. 1379 1379 - * HPD block is enabled at dp_bridge_hpd_enable() 1379 1379 + * HPD block is enabled at msm_dp_bridge_hpd_enable() 1380 1380 * PHY will be enabled at plugin handler later 1381 1381 */ 1382 1382 - dp_display_host_init(dp); 1383 1383 - if (dp->dp_display.is_edp) { 1384 1384 - dp_catalog_ctrl_hpd_enable(dp->catalog); 1385 1385 - dp_display_host_phy_init(dp); 1382 1382 + msm_dp_display_host_init(dp); 1383 1383 + if (dp->msm_dp_display.is_edp) { 1384 1384 + msm_dp_catalog_ctrl_hpd_enable(dp->catalog); 1385 1385 + msm_dp_display_host_phy_init(dp); 1386 1386 } 1387 1387 1388 1388 enable_irq(dp->irq); 1389 1389 return 0; 1390 1390 } 1391 1391 1392 1392 - static const struct dev_pm_ops dp_pm_ops = { 1393 1393 - SET_RUNTIME_PM_OPS(dp_pm_runtime_suspend, dp_pm_runtime_resume, NULL) 1392 1392 + static const struct dev_pm_ops msm_dp_pm_ops = { 1393 1393 + SET_RUNTIME_PM_OPS(msm_dp_pm_runtime_suspend, msm_dp_pm_runtime_resume, NULL) 1394 1394 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1395 1395 pm_runtime_force_resume) 1396 1396 }; 1397 1397 1398 1398 - static struct platform_driver dp_display_driver = { 1399 1399 - .probe = dp_display_probe, 1400 1400 - .remove_new = dp_display_remove, 1398 1398 + static struct platform_driver msm_dp_display_driver = { 1399 1399 + .probe = msm_dp_display_probe, 1400 1400 + .remove_new = msm_dp_display_remove, 1401 1401 .driver = { 1402 1402 .name = "msm-dp-display", 1403 1403 - .of_match_table = dp_dt_match, 1403 1403 + .of_match_table = msm_dp_dt_match, 1404 1404 .suppress_bind_attrs = true, 1405 1405 - .pm = &dp_pm_ops, 1405 1405 + .pm = &msm_dp_pm_ops, 1406 1406 }, 1407 1407 }; 1408 1408 ··· 1410 1410 { 1411 1411 int ret; 1412 1412 1413 1413 - ret = platform_driver_register(&dp_display_driver); 1413 1413 + ret = platform_driver_register(&msm_dp_display_driver); 1414 1414 if (ret) 1415 1415 DRM_ERROR("Dp display driver register failed"); 1416 1416 ··· 1419 1419 1420 1420 void __exit msm_dp_unregister(void) 1421 1421 { 1422 1422 - platform_driver_unregister(&dp_display_driver); 1422 1422 + platform_driver_unregister(&msm_dp_display_driver); 1423 1423 } 1424 1424 1425 1425 - bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 1425 1425 + bool msm_dp_is_yuv_420_enabled(const struct msm_dp *msm_dp_display, 1426 1426 const struct drm_display_mode *mode) 1427 1427 { 1428 1428 - struct dp_display_private *dp; 1428 1428 + struct msm_dp_display_private *dp; 1429 1429 const struct drm_display_info *info; 1430 1430 1431 1431 - dp = container_of(dp_display, struct dp_display_private, dp_display); 1432 1432 - info = &dp_display->connector->display_info; 1431 1431 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1432 1432 + info = &msm_dp_display->connector->display_info; 1433 1433 1434 1434 return dp->panel->vsc_sdp_supported && drm_mode_is_420_only(info, mode); 1435 1435 } 1436 1436 1437 1437 - bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 1437 1437 + bool msm_dp_needs_periph_flush(const struct msm_dp *msm_dp_display, 1438 1438 const struct drm_display_mode *mode) 1439 1439 { 1440 1440 - return msm_dp_is_yuv_420_enabled(dp_display, mode); 1440 1440 + return msm_dp_is_yuv_420_enabled(msm_dp_display, mode); 1441 1441 } 1442 1442 1443 1443 - bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 1443 1443 + bool msm_dp_wide_bus_available(const struct msm_dp *msm_dp_display) 1444 1444 { 1445 1445 - struct dp_display_private *dp; 1445 1445 + struct msm_dp_display_private *dp; 1446 1446 1447 1447 - dp = container_of(dp_display, struct dp_display_private, dp_display); 1447 1447 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1448 1448 1449 1449 - if (dp->dp_mode.out_fmt_is_yuv_420) 1449 1449 + if (dp->msm_dp_mode.out_fmt_is_yuv_420) 1450 1450 return false; 1451 1451 1452 1452 return dp->wide_bus_supported; 1453 1453 } 1454 1454 1455 1455 - void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, bool is_edp) 1455 1455 + void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct dentry *root, bool is_edp) 1456 1456 { 1457 1457 - struct dp_display_private *dp; 1457 1457 + struct msm_dp_display_private *dp; 1458 1458 struct device *dev; 1459 1459 int rc; 1460 1460 1461 1461 - dp = container_of(dp_display, struct dp_display_private, dp_display); 1462 1462 - dev = &dp->dp_display.pdev->dev; 1461 1461 + dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1462 1462 + dev = &dp->msm_dp_display.pdev->dev; 1463 1463 1464 1464 - rc = dp_debug_init(dev, dp->panel, dp->link, dp->dp_display.connector, root, is_edp); 1464 1464 + rc = msm_dp_debug_init(dev, dp->panel, dp->link, dp->msm_dp_display.connector, root, is_edp); 1465 1465 if (rc) 1466 1466 DRM_ERROR("failed to initialize debug, rc = %d\n", rc); 1467 1467 } 1468 1468 1469 1469 - int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 1469 1469 + int msm_dp_modeset_init(struct msm_dp *msm_dp_display, struct drm_device *dev, 1470 1470 struct drm_encoder *encoder, bool yuv_supported) 1471 1471 { 1472 1472 - struct dp_display_private *dp_priv; 1472 1472 + struct msm_dp_display_private *msm_dp_priv; 1473 1473 int ret; 1474 1474 1475 1475 - dp_display->drm_dev = dev; 1475 1475 + msm_dp_display->drm_dev = dev; 1476 1476 1477 1477 - dp_priv = container_of(dp_display, struct dp_display_private, dp_display); 1477 1477 + msm_dp_priv = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1478 1478 1479 1479 - ret = dp_bridge_init(dp_display, dev, encoder, yuv_supported); 1479 1479 + ret = msm_dp_bridge_init(msm_dp_display, dev, encoder, yuv_supported); 1480 1480 if (ret) { 1481 1481 DRM_DEV_ERROR(dev->dev, 1482 1482 "failed to create dp bridge: %d\n", ret); 1483 1483 return ret; 1484 1484 } 1485 1485 1486 1486 - dp_display->connector = dp_drm_connector_init(dp_display, encoder); 1487 1487 - if (IS_ERR(dp_display->connector)) { 1488 1488 - ret = PTR_ERR(dp_display->connector); 1486 1486 + msm_dp_display->connector = msm_dp_drm_connector_init(msm_dp_display, encoder); 1487 1487 + if (IS_ERR(msm_dp_display->connector)) { 1488 1488 + ret = PTR_ERR(msm_dp_display->connector); 1489 1489 DRM_DEV_ERROR(dev->dev, 1490 1490 "failed to create dp connector: %d\n", ret); 1491 1491 - dp_display->connector = NULL; 1491 1491 + msm_dp_display->connector = NULL; 1492 1492 return ret; 1493 1493 } 1494 1494 1495 1495 - dp_priv->panel->connector = dp_display->connector; 1495 1495 + msm_dp_priv->panel->connector = msm_dp_display->connector; 1496 1496 1497 1497 return 0; 1498 1498 } 1499 1499 1500 1500 - void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 1500 1500 + void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 1501 1501 struct drm_bridge_state *old_bridge_state) 1502 1502 { 1503 1503 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 1504 1504 - struct msm_dp *dp = dp_bridge->dp_display; 1503 1503 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 1504 1504 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 1505 1505 int rc = 0; 1506 1506 - struct dp_display_private *dp_display; 1506 1506 + struct msm_dp_display_private *msm_dp_display; 1507 1507 u32 state; 1508 1508 bool force_link_train = false; 1509 1509 1510 1510 - dp_display = container_of(dp, struct dp_display_private, dp_display); 1511 1511 - if (!dp_display->dp_mode.drm_mode.clock) { 1510 1510 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1511 1511 + if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { 1512 1512 DRM_ERROR("invalid params\n"); 1513 1513 return; 1514 1514 } 1515 1515 1516 1516 if (dp->is_edp) 1517 1517 - dp_hpd_plug_handle(dp_display, 0); 1517 1517 + msm_dp_hpd_plug_handle(msm_dp_display, 0); 1518 1518 1519 1519 - mutex_lock(&dp_display->event_mutex); 1519 1519 + mutex_lock(&msm_dp_display->event_mutex); 1520 1520 if (pm_runtime_resume_and_get(&dp->pdev->dev)) { 1521 1521 DRM_ERROR("failed to pm_runtime_resume\n"); 1522 1522 - mutex_unlock(&dp_display->event_mutex); 1522 1522 + mutex_unlock(&msm_dp_display->event_mutex); 1523 1523 return; 1524 1524 } 1525 1525 1526 1526 - state = dp_display->hpd_state; 1526 1526 + state = msm_dp_display->hpd_state; 1527 1527 if (state != ST_DISPLAY_OFF && state != ST_MAINLINK_READY) { 1528 1528 - mutex_unlock(&dp_display->event_mutex); 1528 1528 + mutex_unlock(&msm_dp_display->event_mutex); 1529 1529 return; 1530 1530 } 1531 1531 1532 1532 - rc = dp_display_set_mode(dp, &dp_display->dp_mode); 1532 1532 + rc = msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); 1533 1533 if (rc) { 1534 1534 DRM_ERROR("Failed to perform a mode set, rc=%d\n", rc); 1535 1535 - mutex_unlock(&dp_display->event_mutex); 1535 1535 + mutex_unlock(&msm_dp_display->event_mutex); 1536 1536 return; 1537 1537 } 1538 1538 1539 1539 - state = dp_display->hpd_state; 1539 1539 + state = msm_dp_display->hpd_state; 1540 1540 1541 1541 if (state == ST_DISPLAY_OFF) { 1542 1542 - dp_display_host_phy_init(dp_display); 1542 1542 + msm_dp_display_host_phy_init(msm_dp_display); 1543 1543 force_link_train = true; 1544 1544 } 1545 1545 1546 1546 - dp_display_enable(dp_display, force_link_train); 1546 1546 + msm_dp_display_enable(msm_dp_display, force_link_train); 1547 1547 1548 1548 - rc = dp_display_post_enable(dp); 1548 1548 + rc = msm_dp_display_post_enable(dp); 1549 1549 if (rc) { 1550 1550 DRM_ERROR("DP display post enable failed, rc=%d\n", rc); 1551 1551 - dp_display_disable(dp_display); 1551 1551 + msm_dp_display_disable(msm_dp_display); 1552 1552 } 1553 1553 1554 1554 /* completed connection */ 1555 1555 - dp_display->hpd_state = ST_CONNECTED; 1555 1555 + msm_dp_display->hpd_state = ST_CONNECTED; 1556 1556 1557 1557 drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); 1558 1558 - mutex_unlock(&dp_display->event_mutex); 1558 1558 + mutex_unlock(&msm_dp_display->event_mutex); 1559 1559 } 1560 1560 1561 1561 - void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 1561 1561 + void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 1562 1562 struct drm_bridge_state *old_bridge_state) 1563 1563 { 1564 1564 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 1565 1565 - struct msm_dp *dp = dp_bridge->dp_display; 1566 1566 - struct dp_display_private *dp_display; 1564 1564 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 1565 1565 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 1566 1566 + struct msm_dp_display_private *msm_dp_display; 1567 1567 1568 1568 - dp_display = container_of(dp, struct dp_display_private, dp_display); 1568 1568 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1569 1569 1570 1570 - dp_ctrl_push_idle(dp_display->ctrl); 1570 1570 + msm_dp_ctrl_push_idle(msm_dp_display->ctrl); 1571 1571 } 1572 1572 1573 1573 - void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 1573 1573 + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 1574 1574 struct drm_bridge_state *old_bridge_state) 1575 1575 { 1576 1576 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 1577 1577 - struct msm_dp *dp = dp_bridge->dp_display; 1576 1576 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 1577 1577 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 1578 1578 u32 state; 1579 1579 - struct dp_display_private *dp_display; 1579 1579 + struct msm_dp_display_private *msm_dp_display; 1580 1580 1581 1581 - dp_display = container_of(dp, struct dp_display_private, dp_display); 1581 1581 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1582 1582 1583 1583 if (dp->is_edp) 1584 1584 - dp_hpd_unplug_handle(dp_display, 0); 1584 1584 + msm_dp_hpd_unplug_handle(msm_dp_display, 0); 1585 1585 1586 1586 - mutex_lock(&dp_display->event_mutex); 1586 1586 + mutex_lock(&msm_dp_display->event_mutex); 1587 1587 1588 1588 - state = dp_display->hpd_state; 1588 1588 + state = msm_dp_display->hpd_state; 1589 1589 if (state != ST_DISCONNECT_PENDING && state != ST_CONNECTED) 1590 1590 drm_dbg_dp(dp->drm_dev, "type=%d wrong hpd_state=%d\n", 1591 1591 dp->connector_type, state); 1592 1592 1593 1593 - dp_display_disable(dp_display); 1593 1593 + msm_dp_display_disable(msm_dp_display); 1594 1594 1595 1595 - state = dp_display->hpd_state; 1595 1595 + state = msm_dp_display->hpd_state; 1596 1596 if (state == ST_DISCONNECT_PENDING) { 1597 1597 /* completed disconnection */ 1598 1598 - dp_display->hpd_state = ST_DISCONNECTED; 1598 1598 + msm_dp_display->hpd_state = ST_DISCONNECTED; 1599 1599 } else { 1600 1600 - dp_display->hpd_state = ST_DISPLAY_OFF; 1600 1600 + msm_dp_display->hpd_state = ST_DISPLAY_OFF; 1601 1601 } 1602 1602 1603 1603 drm_dbg_dp(dp->drm_dev, "type=%d Done\n", dp->connector_type); 1604 1604 1605 1605 pm_runtime_put_sync(&dp->pdev->dev); 1606 1606 - mutex_unlock(&dp_display->event_mutex); 1606 1606 + mutex_unlock(&msm_dp_display->event_mutex); 1607 1607 } 1608 1608 1609 1609 - void dp_bridge_mode_set(struct drm_bridge *drm_bridge, 1609 1609 + void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, 1610 1610 const struct drm_display_mode *mode, 1611 1611 const struct drm_display_mode *adjusted_mode) 1612 1612 { 1613 1613 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 1614 1614 - struct msm_dp *dp = dp_bridge->dp_display; 1615 1615 - struct dp_display_private *dp_display; 1616 1616 - struct dp_panel *dp_panel; 1613 1613 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 1614 1614 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 1615 1615 + struct msm_dp_display_private *msm_dp_display; 1616 1616 + struct msm_dp_panel *msm_dp_panel; 1617 1617 1618 1618 - dp_display = container_of(dp, struct dp_display_private, dp_display); 1619 1619 - dp_panel = dp_display->panel; 1618 1618 + msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); 1619 1619 + msm_dp_panel = msm_dp_display->panel; 1620 1620 1621 1621 - memset(&dp_display->dp_mode, 0x0, sizeof(struct dp_display_mode)); 1621 1621 + memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mode)); 1622 1622 1623 1623 - if (dp_display_check_video_test(dp)) 1624 1624 - dp_display->dp_mode.bpp = dp_display_get_test_bpp(dp); 1623 1623 + if (msm_dp_display_check_video_test(dp)) 1624 1624 + msm_dp_display->msm_dp_mode.bpp = msm_dp_display_get_test_bpp(dp); 1625 1625 else /* Default num_components per pixel = 3 */ 1626 1626 - dp_display->dp_mode.bpp = dp->connector->display_info.bpc * 3; 1626 1626 + msm_dp_display->msm_dp_mode.bpp = dp->connector->display_info.bpc * 3; 1627 1627 1628 1628 - if (!dp_display->dp_mode.bpp) 1629 1629 - dp_display->dp_mode.bpp = 24; /* Default bpp */ 1628 1628 + if (!msm_dp_display->msm_dp_mode.bpp) 1629 1629 + msm_dp_display->msm_dp_mode.bpp = 24; /* Default bpp */ 1630 1630 1631 1631 - drm_mode_copy(&dp_display->dp_mode.drm_mode, adjusted_mode); 1631 1631 + drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); 1632 1632 1633 1633 - dp_display->dp_mode.v_active_low = 1634 1634 - !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); 1633 1633 + msm_dp_display->msm_dp_mode.v_active_low = 1634 1634 + !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); 1635 1635 1636 1636 - dp_display->dp_mode.h_active_low = 1637 1637 - !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); 1636 1636 + msm_dp_display->msm_dp_mode.h_active_low = 1637 1637 + !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); 1638 1638 1639 1639 - dp_display->dp_mode.out_fmt_is_yuv_420 = 1639 1639 + msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 = 1640 1640 drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && 1641 1641 - dp_panel->vsc_sdp_supported; 1641 1641 + msm_dp_panel->vsc_sdp_supported; 1642 1642 1643 1643 /* populate wide_bus_support to different layers */ 1644 1644 - dp_display->ctrl->wide_bus_en = 1645 1645 - dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; 1646 1646 - dp_display->catalog->wide_bus_en = 1647 1647 - dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; 1644 1644 + msm_dp_display->ctrl->wide_bus_en = 1645 1645 + msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display->wide_bus_supported; 1646 1646 + msm_dp_display->catalog->wide_bus_en = 1647 1647 + msm_dp_display->msm_dp_mode.out_fmt_is_yuv_420 ? false : msm_dp_display->wide_bus_supported; 1648 1648 } 1649 1649 1650 1650 - void dp_bridge_hpd_enable(struct drm_bridge *bridge) 1650 1650 + void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) 1651 1651 { 1652 1652 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); 1653 1653 - struct msm_dp *dp_display = dp_bridge->dp_display; 1654 1654 - struct dp_display_private *dp = container_of(dp_display, struct dp_display_private, dp_display); 1652 1652 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); 1653 1653 + struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; 1654 1654 + struct msm_dp_display_private *dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1655 1655 1656 1656 /* 1657 1657 * this is for external DP with hpd irq enabled case, 1658 1658 - * step-1: dp_pm_runtime_resume() enable dp host only 1658 1658 + * step-1: msm_dp_pm_runtime_resume() enable dp host only 1659 1659 * step-2: enable hdp block and have hpd irq enabled here 1660 1660 * step-3: waiting for plugin irq while phy is not initialized 1661 1661 * step-4: DP PHY is initialized at plugin handler before link training 1662 1662 * 1663 1663 */ 1664 1664 mutex_lock(&dp->event_mutex); 1665 1665 - if (pm_runtime_resume_and_get(&dp_display->pdev->dev)) { 1665 1665 + if (pm_runtime_resume_and_get(&msm_dp_display->pdev->dev)) { 1666 1666 DRM_ERROR("failed to resume power\n"); 1667 1667 mutex_unlock(&dp->event_mutex); 1668 1668 return; 1669 1669 } 1670 1670 1671 1671 - dp_catalog_ctrl_hpd_enable(dp->catalog); 1671 1671 + msm_dp_catalog_ctrl_hpd_enable(dp->catalog); 1672 1672 1673 1673 /* enable HDP interrupts */ 1674 1674 - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, true); 1674 1674 + msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, true); 1675 1675 1676 1676 - dp_display->internal_hpd = true; 1676 1676 + msm_dp_display->internal_hpd = true; 1677 1677 mutex_unlock(&dp->event_mutex); 1678 1678 } 1679 1679 1680 1680 - void dp_bridge_hpd_disable(struct drm_bridge *bridge) 1680 1680 + void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge) 1681 1681 { 1682 1682 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); 1683 1683 - struct msm_dp *dp_display = dp_bridge->dp_display; 1684 1684 - struct dp_display_private *dp = container_of(dp_display, struct dp_display_private, dp_display); 1682 1682 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); 1683 1683 + struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; 1684 1684 + struct msm_dp_display_private *dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1685 1685 1686 1686 mutex_lock(&dp->event_mutex); 1687 1687 /* disable HDP interrupts */ 1688 1688 - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false); 1689 1689 - dp_catalog_ctrl_hpd_disable(dp->catalog); 1688 1688 + msm_dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_INT_MASK, false); 1689 1689 + msm_dp_catalog_ctrl_hpd_disable(dp->catalog); 1690 1690 1691 1691 - dp_display->internal_hpd = false; 1691 1691 + msm_dp_display->internal_hpd = false; 1692 1692 1693 1693 - pm_runtime_put_sync(&dp_display->pdev->dev); 1693 1693 + pm_runtime_put_sync(&msm_dp_display->pdev->dev); 1694 1694 mutex_unlock(&dp->event_mutex); 1695 1695 } 1696 1696 1697 1697 - void dp_bridge_hpd_notify(struct drm_bridge *bridge, 1697 1697 + void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, 1698 1698 enum drm_connector_status status) 1699 1699 { 1700 1700 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge); 1701 1701 - struct msm_dp *dp_display = dp_bridge->dp_display; 1702 1702 - struct dp_display_private *dp = container_of(dp_display, struct dp_display_private, dp_display); 1700 1700 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(bridge); 1701 1701 + struct msm_dp *msm_dp_display = msm_dp_bridge->msm_dp_display; 1702 1702 + struct msm_dp_display_private *dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); 1703 1703 1704 1704 /* Without next_bridge interrupts are handled by the DP core directly */ 1705 1705 - if (dp_display->internal_hpd) 1705 1705 + if (msm_dp_display->internal_hpd) 1706 1706 return; 1707 1707 1708 1708 - if (!dp_display->link_ready && status == connector_status_connected) 1709 1709 - dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); 1710 1710 - else if (dp_display->link_ready && status == connector_status_disconnected) 1711 1711 - dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1708 1708 + if (!msm_dp_display->link_ready && status == connector_status_connected) 1709 1709 + msm_dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0); 1710 1710 + else if (msm_dp_display->link_ready && status == connector_status_disconnected) 1711 1711 + msm_dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0); 1712 1712 }

+9 -9

drivers/gpu/drm/msm/dp/dp_display.h

reviewed

··· 27 27 28 28 hdmi_codec_plugged_cb plugged_cb; 29 29 30 30 - struct dp_audio *dp_audio; 30 30 + struct msm_dp_audio *msm_dp_audio; 31 31 bool psr_supported; 32 32 }; 33 33 34 34 - int dp_display_set_plugged_cb(struct msm_dp *dp_display, 34 34 + int msm_dp_display_set_plugged_cb(struct msm_dp *msm_dp_display, 35 35 hdmi_codec_plugged_cb fn, struct device *codec_dev); 36 36 - int dp_display_get_modes(struct msm_dp *dp_display); 37 37 - bool dp_display_check_video_test(struct msm_dp *dp_display); 38 38 - int dp_display_get_test_bpp(struct msm_dp *dp_display); 39 39 - void dp_display_signal_audio_start(struct msm_dp *dp_display); 40 40 - void dp_display_signal_audio_complete(struct msm_dp *dp_display); 41 41 - void dp_display_set_psr(struct msm_dp *dp, bool enter); 42 42 - void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *dentry, bool is_edp); 36 36 + int msm_dp_display_get_modes(struct msm_dp *msm_dp_display); 37 37 + bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display); 38 38 + int msm_dp_display_get_test_bpp(struct msm_dp *msm_dp_display); 39 39 + void msm_dp_display_signal_audio_start(struct msm_dp *msm_dp_display); 40 40 + void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); 41 41 + void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); 42 42 + void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct dentry *dentry, bool is_edp); 43 43 44 44 #endif /* _DP_DISPLAY_H_ */

+71 -71

drivers/gpu/drm/msm/dp/dp_drm.c

reviewed

··· 14 14 #include "dp_drm.h" 15 15 16 16 /** 17 17 - * dp_bridge_detect - callback to determine if connector is connected 17 17 + * msm_dp_bridge_detect - callback to determine if connector is connected 18 18 * @bridge: Pointer to drm bridge structure 19 19 * Returns: Bridge's 'is connected' status 20 20 */ 21 21 - static enum drm_connector_status dp_bridge_detect(struct drm_bridge *bridge) 21 21 + static enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge) 22 22 { 23 23 struct msm_dp *dp; 24 24 25 25 - dp = to_dp_bridge(bridge)->dp_display; 25 25 + dp = to_dp_bridge(bridge)->msm_dp_display; 26 26 27 27 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", 28 28 (dp->link_ready) ? "true" : "false"); ··· 31 31 connector_status_disconnected; 32 32 } 33 33 34 34 - static int dp_bridge_atomic_check(struct drm_bridge *bridge, 34 34 + static int msm_dp_bridge_atomic_check(struct drm_bridge *bridge, 35 35 struct drm_bridge_state *bridge_state, 36 36 struct drm_crtc_state *crtc_state, 37 37 struct drm_connector_state *conn_state) 38 38 { 39 39 struct msm_dp *dp; 40 40 41 41 - dp = to_dp_bridge(bridge)->dp_display; 41 41 + dp = to_dp_bridge(bridge)->msm_dp_display; 42 42 43 43 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", 44 44 (dp->link_ready) ? "true" : "false"); ··· 62 62 63 63 64 64 /** 65 65 - * dp_bridge_get_modes - callback to add drm modes via drm_mode_probed_add() 65 65 + * msm_dp_bridge_get_modes - callback to add drm modes via drm_mode_probed_add() 66 66 * @bridge: Poiner to drm bridge 67 67 * @connector: Pointer to drm connector structure 68 68 * Returns: Number of modes added 69 69 */ 70 70 - static int dp_bridge_get_modes(struct drm_bridge *bridge, struct drm_connector *connector) 70 70 + static int msm_dp_bridge_get_modes(struct drm_bridge *bridge, struct drm_connector *connector) 71 71 { 72 72 int rc = 0; 73 73 struct msm_dp *dp; ··· 75 75 if (!connector) 76 76 return 0; 77 77 78 78 - dp = to_dp_bridge(bridge)->dp_display; 78 78 + dp = to_dp_bridge(bridge)->msm_dp_display; 79 79 80 80 /* pluggable case assumes EDID is read when HPD */ 81 81 if (dp->link_ready) { 82 82 - rc = dp_display_get_modes(dp); 82 82 + rc = msm_dp_display_get_modes(dp); 83 83 if (rc <= 0) { 84 84 DRM_ERROR("failed to get DP sink modes, rc=%d\n", rc); 85 85 return rc; ··· 90 90 return rc; 91 91 } 92 92 93 93 - static void dp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 93 93 + static void msm_dp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 94 94 { 95 95 - struct msm_dp *dp = to_dp_bridge(bridge)->dp_display; 95 95 + struct msm_dp *dp = to_dp_bridge(bridge)->msm_dp_display; 96 96 97 97 - dp_display_debugfs_init(dp, root, false); 97 97 + msm_dp_display_debugfs_init(dp, root, false); 98 98 } 99 99 100 100 - static const struct drm_bridge_funcs dp_bridge_ops = { 100 100 + static const struct drm_bridge_funcs msm_dp_bridge_ops = { 101 101 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 102 102 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 103 103 .atomic_reset = drm_atomic_helper_bridge_reset, 104 104 - .atomic_enable = dp_bridge_atomic_enable, 105 105 - .atomic_disable = dp_bridge_atomic_disable, 106 106 - .atomic_post_disable = dp_bridge_atomic_post_disable, 107 107 - .mode_set = dp_bridge_mode_set, 108 108 - .mode_valid = dp_bridge_mode_valid, 109 109 - .get_modes = dp_bridge_get_modes, 110 110 - .detect = dp_bridge_detect, 111 111 - .atomic_check = dp_bridge_atomic_check, 112 112 - .hpd_enable = dp_bridge_hpd_enable, 113 113 - .hpd_disable = dp_bridge_hpd_disable, 114 114 - .hpd_notify = dp_bridge_hpd_notify, 115 115 - .debugfs_init = dp_bridge_debugfs_init, 104 104 + .atomic_enable = msm_dp_bridge_atomic_enable, 105 105 + .atomic_disable = msm_dp_bridge_atomic_disable, 106 106 + .atomic_post_disable = msm_dp_bridge_atomic_post_disable, 107 107 + .mode_set = msm_dp_bridge_mode_set, 108 108 + .mode_valid = msm_dp_bridge_mode_valid, 109 109 + .get_modes = msm_dp_bridge_get_modes, 110 110 + .detect = msm_dp_bridge_detect, 111 111 + .atomic_check = msm_dp_bridge_atomic_check, 112 112 + .hpd_enable = msm_dp_bridge_hpd_enable, 113 113 + .hpd_disable = msm_dp_bridge_hpd_disable, 114 114 + .hpd_notify = msm_dp_bridge_hpd_notify, 115 115 + .debugfs_init = msm_dp_bridge_debugfs_init, 116 116 }; 117 117 118 118 - static int edp_bridge_atomic_check(struct drm_bridge *drm_bridge, 118 118 + static int msm_edp_bridge_atomic_check(struct drm_bridge *drm_bridge, 119 119 struct drm_bridge_state *bridge_state, 120 120 struct drm_crtc_state *crtc_state, 121 121 struct drm_connector_state *conn_state) 122 122 { 123 123 - struct msm_dp *dp = to_dp_bridge(drm_bridge)->dp_display; 123 123 + struct msm_dp *dp = to_dp_bridge(drm_bridge)->msm_dp_display; 124 124 125 125 if (WARN_ON(!conn_state)) 126 126 return -ENODEV; ··· 136 136 return 0; 137 137 } 138 138 139 139 - static void edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 139 139 + static void msm_edp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 140 140 struct drm_bridge_state *old_bridge_state) 141 141 { 142 142 struct drm_atomic_state *atomic_state = old_bridge_state->base.state; 143 143 struct drm_crtc *crtc; 144 144 struct drm_crtc_state *old_crtc_state; 145 145 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 146 146 - struct msm_dp *dp = dp_bridge->dp_display; 145 145 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 146 146 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 147 147 148 148 /* 149 149 * Check the old state of the crtc to determine if the panel 150 150 - * was put into psr state previously by the edp_bridge_atomic_disable. 150 150 + * was put into psr state previously by the msm_edp_bridge_atomic_disable. 151 151 * If the panel is in psr, just exit psr state and skip the full 152 152 * bridge enable sequence. 153 153 */ ··· 159 159 old_crtc_state = drm_atomic_get_old_crtc_state(atomic_state, crtc); 160 160 161 161 if (old_crtc_state && old_crtc_state->self_refresh_active) { 162 162 - dp_display_set_psr(dp, false); 162 162 + msm_dp_display_set_psr(dp, false); 163 163 return; 164 164 } 165 165 166 166 - dp_bridge_atomic_enable(drm_bridge, old_bridge_state); 166 166 + msm_dp_bridge_atomic_enable(drm_bridge, old_bridge_state); 167 167 } 168 168 169 169 - static void edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 169 169 + static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 170 170 struct drm_bridge_state *old_bridge_state) 171 171 { 172 172 struct drm_atomic_state *atomic_state = old_bridge_state->base.state; 173 173 struct drm_crtc *crtc; 174 174 struct drm_crtc_state *new_crtc_state = NULL, *old_crtc_state = NULL; 175 175 - struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); 176 176 - struct msm_dp *dp = dp_bridge->dp_display; 175 175 + struct msm_dp_bridge *msm_dp_bridge = to_dp_bridge(drm_bridge); 176 176 + struct msm_dp *dp = msm_dp_bridge->msm_dp_display; 177 177 178 178 crtc = drm_atomic_get_old_crtc_for_encoder(atomic_state, 179 179 drm_bridge->encoder); ··· 194 194 * If old crtc state is active, then this is a display disable 195 195 * call while the sink is in psr state. So, exit psr here. 196 196 * The eDP controller will be disabled in the 197 197 - * edp_bridge_atomic_post_disable function. 197 197 + * msm_edp_bridge_atomic_post_disable function. 198 198 * 199 199 * We observed sink is stuck in self refresh if psr exit is skipped 200 200 * when display disable occurs while the sink is in psr state. 201 201 */ 202 202 if (new_crtc_state->self_refresh_active) { 203 203 - dp_display_set_psr(dp, true); 203 203 + msm_dp_display_set_psr(dp, true); 204 204 return; 205 205 } else if (old_crtc_state->self_refresh_active) { 206 206 - dp_display_set_psr(dp, false); 206 206 + msm_dp_display_set_psr(dp, false); 207 207 return; 208 208 } 209 209 210 210 out: 211 211 - dp_bridge_atomic_disable(drm_bridge, old_bridge_state); 211 211 + msm_dp_bridge_atomic_disable(drm_bridge, old_bridge_state); 212 212 } 213 213 214 214 - static void edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 214 214 + static void msm_edp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 215 215 struct drm_bridge_state *old_bridge_state) 216 216 { 217 217 struct drm_atomic_state *atomic_state = old_bridge_state->base.state; ··· 228 228 return; 229 229 230 230 /* 231 231 - * Self refresh mode is already set in edp_bridge_atomic_disable. 231 231 + * Self refresh mode is already set in msm_edp_bridge_atomic_disable. 232 232 */ 233 233 if (new_crtc_state->self_refresh_active) 234 234 return; 235 235 236 236 - dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state); 236 236 + msm_dp_bridge_atomic_post_disable(drm_bridge, old_bridge_state); 237 237 } 238 238 239 239 /** 240 240 - * edp_bridge_mode_valid - callback to determine if specified mode is valid 240 240 + * msm_edp_bridge_mode_valid - callback to determine if specified mode is valid 241 241 * @bridge: Pointer to drm bridge structure 242 242 * @info: display info 243 243 * @mode: Pointer to drm mode structure 244 244 * Returns: Validity status for specified mode 245 245 */ 246 246 - static enum drm_mode_status edp_bridge_mode_valid(struct drm_bridge *bridge, 246 246 + static enum drm_mode_status msm_edp_bridge_mode_valid(struct drm_bridge *bridge, 247 247 const struct drm_display_info *info, 248 248 const struct drm_display_mode *mode) 249 249 { 250 250 struct msm_dp *dp; 251 251 int mode_pclk_khz = mode->clock; 252 252 253 253 - dp = to_dp_bridge(bridge)->dp_display; 253 253 + dp = to_dp_bridge(bridge)->msm_dp_display; 254 254 255 255 if (!dp || !mode_pclk_khz || !dp->connector) { 256 256 DRM_ERROR("invalid params\n"); ··· 268 268 return MODE_OK; 269 269 } 270 270 271 271 - static void edp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 271 271 + static void msm_edp_bridge_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 272 272 { 273 273 - struct msm_dp *dp = to_dp_bridge(bridge)->dp_display; 273 273 + struct msm_dp *dp = to_dp_bridge(bridge)->msm_dp_display; 274 274 275 275 - dp_display_debugfs_init(dp, root, true); 275 275 + msm_dp_display_debugfs_init(dp, root, true); 276 276 } 277 277 278 278 - static const struct drm_bridge_funcs edp_bridge_ops = { 279 279 - .atomic_enable = edp_bridge_atomic_enable, 280 280 - .atomic_disable = edp_bridge_atomic_disable, 281 281 - .atomic_post_disable = edp_bridge_atomic_post_disable, 282 282 - .mode_set = dp_bridge_mode_set, 283 283 - .mode_valid = edp_bridge_mode_valid, 278 278 + static const struct drm_bridge_funcs msm_edp_bridge_ops = { 279 279 + .atomic_enable = msm_edp_bridge_atomic_enable, 280 280 + .atomic_disable = msm_edp_bridge_atomic_disable, 281 281 + .atomic_post_disable = msm_edp_bridge_atomic_post_disable, 282 282 + .mode_set = msm_dp_bridge_mode_set, 283 283 + .mode_valid = msm_edp_bridge_mode_valid, 284 284 .atomic_reset = drm_atomic_helper_bridge_reset, 285 285 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 286 286 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 287 287 - .atomic_check = edp_bridge_atomic_check, 288 288 - .debugfs_init = edp_bridge_debugfs_init, 287 287 + .atomic_check = msm_edp_bridge_atomic_check, 288 288 + .debugfs_init = msm_edp_bridge_debugfs_init, 289 289 }; 290 290 291 291 - int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, 291 291 + int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, 292 292 struct drm_encoder *encoder, bool yuv_supported) 293 293 { 294 294 int rc; 295 295 - struct msm_dp_bridge *dp_bridge; 295 295 + struct msm_dp_bridge *msm_dp_bridge; 296 296 struct drm_bridge *bridge; 297 297 298 298 - dp_bridge = devm_kzalloc(dev->dev, sizeof(*dp_bridge), GFP_KERNEL); 299 299 - if (!dp_bridge) 298 298 + msm_dp_bridge = devm_kzalloc(dev->dev, sizeof(*msm_dp_bridge), GFP_KERNEL); 299 299 + if (!msm_dp_bridge) 300 300 return -ENOMEM; 301 301 302 302 - dp_bridge->dp_display = dp_display; 302 302 + msm_dp_bridge->msm_dp_display = msm_dp_display; 303 303 304 304 - bridge = &dp_bridge->bridge; 305 305 - bridge->funcs = dp_display->is_edp ? &edp_bridge_ops : &dp_bridge_ops; 306 306 - bridge->type = dp_display->connector_type; 304 304 + bridge = &msm_dp_bridge->bridge; 305 305 + bridge->funcs = msm_dp_display->is_edp ? &msm_edp_bridge_ops : &msm_dp_bridge_ops; 306 306 + bridge->type = msm_dp_display->connector_type; 307 307 bridge->ycbcr_420_allowed = yuv_supported; 308 308 309 309 /* ··· 317 317 * allows the panel driver to properly power itself on to read the 318 318 * modes. 319 319 */ 320 320 - if (!dp_display->is_edp) { 320 320 + if (!msm_dp_display->is_edp) { 321 321 bridge->ops = 322 322 DRM_BRIDGE_OP_DETECT | 323 323 DRM_BRIDGE_OP_HPD | ··· 338 338 return rc; 339 339 } 340 340 341 341 - if (dp_display->next_bridge) { 341 341 + if (msm_dp_display->next_bridge) { 342 342 rc = drm_bridge_attach(encoder, 343 343 - dp_display->next_bridge, bridge, 343 343 + msm_dp_display->next_bridge, bridge, 344 344 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 345 345 if (rc < 0) { 346 346 DRM_ERROR("failed to attach panel bridge: %d\n", rc); ··· 352 352 } 353 353 354 354 /* connector initialization */ 355 355 - struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, 355 355 + struct drm_connector *msm_dp_drm_connector_init(struct msm_dp *msm_dp_display, 356 356 struct drm_encoder *encoder) 357 357 { 358 358 struct drm_connector *connector = NULL; 359 359 360 360 - connector = drm_bridge_connector_init(dp_display->drm_dev, encoder); 360 360 + connector = drm_bridge_connector_init(msm_dp_display->drm_dev, encoder); 361 361 if (IS_ERR(connector)) 362 362 return connector; 363 363 364 364 - if (!dp_display->is_edp) 364 364 + if (!msm_dp_display->is_edp) 365 365 drm_connector_attach_dp_subconnector_property(connector); 366 366 367 367 drm_connector_attach_encoder(connector, encoder);

+11 -11

drivers/gpu/drm/msm/dp/dp_drm.h

reviewed

··· 14 14 15 15 struct msm_dp_bridge { 16 16 struct drm_bridge bridge; 17 17 - struct msm_dp *dp_display; 17 17 + struct msm_dp *msm_dp_display; 18 18 }; 19 19 20 20 #define to_dp_bridge(x) container_of((x), struct msm_dp_bridge, bridge) 21 21 22 22 - struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, 22 22 + struct drm_connector *msm_dp_drm_connector_init(struct msm_dp *msm_dp_display, 23 23 struct drm_encoder *encoder); 24 24 - int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, 24 24 + int msm_dp_bridge_init(struct msm_dp *msm_dp_display, struct drm_device *dev, 25 25 struct drm_encoder *encoder, 26 26 bool yuv_supported); 27 27 28 28 - void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 28 28 + void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, 29 29 struct drm_bridge_state *old_bridge_state); 30 30 - void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 30 30 + void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, 31 31 struct drm_bridge_state *old_bridge_state); 32 32 - void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 32 32 + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, 33 33 struct drm_bridge_state *old_bridge_state); 34 34 - enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, 34 34 + enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, 35 35 const struct drm_display_info *info, 36 36 const struct drm_display_mode *mode); 37 37 - void dp_bridge_mode_set(struct drm_bridge *drm_bridge, 37 37 + void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, 38 38 const struct drm_display_mode *mode, 39 39 const struct drm_display_mode *adjusted_mode); 40 40 - void dp_bridge_hpd_enable(struct drm_bridge *bridge); 41 41 - void dp_bridge_hpd_disable(struct drm_bridge *bridge); 42 42 - void dp_bridge_hpd_notify(struct drm_bridge *bridge, 40 40 + void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge); 41 41 + void msm_dp_bridge_hpd_disable(struct drm_bridge *bridge); 42 42 + void msm_dp_bridge_hpd_notify(struct drm_bridge *bridge, 43 43 enum drm_connector_status status); 44 44 45 45 #endif /* _DP_DRM_H_ */

+216 -216

drivers/gpu/drm/msm/dp/dp_link.c

reviewed

··· 28 28 AUDIO_TEST_PATTERN_SAWTOOTH = 0x01, 29 29 }; 30 30 31 31 - struct dp_link_request { 31 31 + struct msm_dp_link_request { 32 32 u32 test_requested; 33 33 u32 test_link_rate; 34 34 u32 test_lane_count; 35 35 }; 36 36 37 37 - struct dp_link_private { 37 37 + struct msm_dp_link_private { 38 38 u32 prev_sink_count; 39 39 struct drm_device *drm_dev; 40 40 struct drm_dp_aux *aux; 41 41 - struct dp_link dp_link; 41 41 + struct msm_dp_link msm_dp_link; 42 42 43 43 - struct dp_link_request request; 43 43 + struct msm_dp_link_request request; 44 44 struct mutex psm_mutex; 45 45 u8 link_status[DP_LINK_STATUS_SIZE]; 46 46 }; 47 47 48 48 - static int dp_aux_link_power_up(struct drm_dp_aux *aux, 49 49 - struct dp_link_info *link) 48 48 + static int msm_dp_aux_link_power_up(struct drm_dp_aux *aux, 49 49 + struct msm_dp_link_info *link) 50 50 { 51 51 u8 value; 52 52 ssize_t len; ··· 73 73 return 0; 74 74 } 75 75 76 76 - static int dp_aux_link_power_down(struct drm_dp_aux *aux, 77 77 - struct dp_link_info *link) 76 76 + static int msm_dp_aux_link_power_down(struct drm_dp_aux *aux, 77 77 + struct msm_dp_link_info *link) 78 78 { 79 79 u8 value; 80 80 int err; ··· 96 96 return 0; 97 97 } 98 98 99 99 - static int dp_link_get_period(struct dp_link_private *link, int const addr) 99 99 + static int msm_dp_link_get_period(struct msm_dp_link_private *link, int const addr) 100 100 { 101 101 int ret = 0; 102 102 u8 data; ··· 122 122 return ret; 123 123 } 124 124 125 125 - static int dp_link_parse_audio_channel_period(struct dp_link_private *link) 125 125 + static int msm_dp_link_parse_audio_channel_period(struct msm_dp_link_private *link) 126 126 { 127 127 int ret = 0; 128 128 - struct dp_link_test_audio *req = &link->dp_link.test_audio; 128 128 + struct msm_dp_link_test_audio *req = &link->msm_dp_link.test_audio; 129 129 130 130 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH1); 130 130 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH1); 131 131 if (ret == -EINVAL) 132 132 goto exit; 133 133 134 134 req->test_audio_period_ch_1 = ret; 135 135 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_1 = 0x%x\n", ret); 136 136 137 137 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH2); 137 137 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH2); 138 138 if (ret == -EINVAL) 139 139 goto exit; 140 140 ··· 142 142 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_2 = 0x%x\n", ret); 143 143 144 144 /* TEST_AUDIO_PERIOD_CH_3 (Byte 0x275) */ 145 145 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH3); 145 145 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH3); 146 146 if (ret == -EINVAL) 147 147 goto exit; 148 148 149 149 req->test_audio_period_ch_3 = ret; 150 150 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_3 = 0x%x\n", ret); 151 151 152 152 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH4); 152 152 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH4); 153 153 if (ret == -EINVAL) 154 154 goto exit; 155 155 156 156 req->test_audio_period_ch_4 = ret; 157 157 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_4 = 0x%x\n", ret); 158 158 159 159 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH5); 159 159 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH5); 160 160 if (ret == -EINVAL) 161 161 goto exit; 162 162 163 163 req->test_audio_period_ch_5 = ret; 164 164 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_5 = 0x%x\n", ret); 165 165 166 166 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH6); 166 166 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH6); 167 167 if (ret == -EINVAL) 168 168 goto exit; 169 169 170 170 req->test_audio_period_ch_6 = ret; 171 171 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_6 = 0x%x\n", ret); 172 172 173 173 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH7); 173 173 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH7); 174 174 if (ret == -EINVAL) 175 175 goto exit; 176 176 177 177 req->test_audio_period_ch_7 = ret; 178 178 drm_dbg_dp(link->drm_dev, "test_audio_period_ch_7 = 0x%x\n", ret); 179 179 180 180 - ret = dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH8); 180 180 + ret = msm_dp_link_get_period(link, DP_TEST_AUDIO_PERIOD_CH8); 181 181 if (ret == -EINVAL) 182 182 goto exit; 183 183 ··· 187 187 return ret; 188 188 } 189 189 190 190 - static int dp_link_parse_audio_pattern_type(struct dp_link_private *link) 190 190 + static int msm_dp_link_parse_audio_pattern_type(struct msm_dp_link_private *link) 191 191 { 192 192 int ret = 0; 193 193 u8 data; ··· 208 208 goto exit; 209 209 } 210 210 211 211 - link->dp_link.test_audio.test_audio_pattern_type = data; 211 211 + link->msm_dp_link.test_audio.test_audio_pattern_type = data; 212 212 drm_dbg_dp(link->drm_dev, "audio pattern type = 0x%x\n", data); 213 213 exit: 214 214 return ret; 215 215 } 216 216 217 217 - static int dp_link_parse_audio_mode(struct dp_link_private *link) 217 217 + static int msm_dp_link_parse_audio_mode(struct msm_dp_link_private *link) 218 218 { 219 219 int ret = 0; 220 220 u8 data; ··· 248 248 goto exit; 249 249 } 250 250 251 251 - link->dp_link.test_audio.test_audio_sampling_rate = sampling_rate; 252 252 - link->dp_link.test_audio.test_audio_channel_count = channel_count; 251 251 + link->msm_dp_link.test_audio.test_audio_sampling_rate = sampling_rate; 252 252 + link->msm_dp_link.test_audio.test_audio_channel_count = channel_count; 253 253 drm_dbg_dp(link->drm_dev, 254 254 "sampling_rate = 0x%x, channel_count = 0x%x\n", 255 255 sampling_rate, channel_count); ··· 257 257 return ret; 258 258 } 259 259 260 260 - static int dp_link_parse_audio_pattern_params(struct dp_link_private *link) 260 260 + static int msm_dp_link_parse_audio_pattern_params(struct msm_dp_link_private *link) 261 261 { 262 262 int ret = 0; 263 263 264 264 - ret = dp_link_parse_audio_mode(link); 264 264 + ret = msm_dp_link_parse_audio_mode(link); 265 265 if (ret) 266 266 goto exit; 267 267 268 268 - ret = dp_link_parse_audio_pattern_type(link); 268 268 + ret = msm_dp_link_parse_audio_pattern_type(link); 269 269 if (ret) 270 270 goto exit; 271 271 272 272 - ret = dp_link_parse_audio_channel_period(link); 272 272 + ret = msm_dp_link_parse_audio_channel_period(link); 273 273 274 274 exit: 275 275 return ret; 276 276 } 277 277 278 278 - static bool dp_link_is_video_pattern_valid(u32 pattern) 278 278 + static bool msm_dp_link_is_video_pattern_valid(u32 pattern) 279 279 { 280 280 switch (pattern) { 281 281 case DP_NO_TEST_PATTERN: ··· 289 289 } 290 290 291 291 /** 292 292 - * dp_link_is_bit_depth_valid() - validates the bit depth requested 292 292 + * msm_dp_link_is_bit_depth_valid() - validates the bit depth requested 293 293 * @tbd: bit depth requested by the sink 294 294 * 295 295 * Returns true if the requested bit depth is supported. 296 296 */ 297 297 - static bool dp_link_is_bit_depth_valid(u32 tbd) 297 297 + static bool msm_dp_link_is_bit_depth_valid(u32 tbd) 298 298 { 299 299 /* DP_TEST_VIDEO_PATTERN_NONE is treated as invalid */ 300 300 switch (tbd) { ··· 307 307 } 308 308 } 309 309 310 310 - static int dp_link_parse_timing_params1(struct dp_link_private *link, 310 310 + static int msm_dp_link_parse_timing_params1(struct msm_dp_link_private *link, 311 311 int addr, int len, u32 *val) 312 312 { 313 313 u8 bp[2]; ··· 328 328 return 0; 329 329 } 330 330 331 331 - static int dp_link_parse_timing_params2(struct dp_link_private *link, 331 331 + static int msm_dp_link_parse_timing_params2(struct msm_dp_link_private *link, 332 332 int addr, int len, 333 333 u32 *val1, u32 *val2) 334 334 { ··· 351 351 return 0; 352 352 } 353 353 354 354 - static int dp_link_parse_timing_params3(struct dp_link_private *link, 354 354 + static int msm_dp_link_parse_timing_params3(struct msm_dp_link_private *link, 355 355 int addr, u32 *val) 356 356 { 357 357 u8 bp; ··· 369 369 } 370 370 371 371 /** 372 372 - * dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD 372 372 + * msm_dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD 373 373 * @link: Display Port Driver data 374 374 * 375 375 * Returns 0 if it successfully parses the video link pattern and the link 376 376 * bit depth requested by the sink and, and if the values parsed are valid. 377 377 */ 378 378 - static int dp_link_parse_video_pattern_params(struct dp_link_private *link) 378 378 + static int msm_dp_link_parse_video_pattern_params(struct msm_dp_link_private *link) 379 379 { 380 380 int ret = 0; 381 381 ssize_t rlen; ··· 388 388 return rlen; 389 389 } 390 390 391 391 - if (!dp_link_is_video_pattern_valid(bp)) { 391 391 + if (!msm_dp_link_is_video_pattern_valid(bp)) { 392 392 DRM_ERROR("invalid link video pattern = 0x%x\n", bp); 393 393 ret = -EINVAL; 394 394 return ret; 395 395 } 396 396 397 397 - link->dp_link.test_video.test_video_pattern = bp; 397 397 + link->msm_dp_link.test_video.test_video_pattern = bp; 398 398 399 399 /* Read the requested color bit depth and dynamic range (Byte 0x232) */ 400 400 rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_MISC0, &bp); ··· 404 404 } 405 405 406 406 /* Dynamic Range */ 407 407 - link->dp_link.test_video.test_dyn_range = 407 407 + link->msm_dp_link.test_video.test_dyn_range = 408 408 (bp & DP_TEST_DYNAMIC_RANGE_CEA); 409 409 410 410 /* Color bit depth */ 411 411 bp &= DP_TEST_BIT_DEPTH_MASK; 412 412 - if (!dp_link_is_bit_depth_valid(bp)) { 412 412 + if (!msm_dp_link_is_bit_depth_valid(bp)) { 413 413 DRM_ERROR("invalid link bit depth = 0x%x\n", bp); 414 414 ret = -EINVAL; 415 415 return ret; 416 416 } 417 417 418 418 - link->dp_link.test_video.test_bit_depth = bp; 418 418 + link->msm_dp_link.test_video.test_bit_depth = bp; 419 419 420 420 /* resolution timing params */ 421 421 - ret = dp_link_parse_timing_params1(link, DP_TEST_H_TOTAL_HI, 2, 422 422 - &link->dp_link.test_video.test_h_total); 421 421 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_H_TOTAL_HI, 2, 422 422 + &link->msm_dp_link.test_video.test_h_total); 423 423 if (ret) { 424 424 DRM_ERROR("failed to parse test_htotal(DP_TEST_H_TOTAL_HI)\n"); 425 425 return ret; 426 426 } 427 427 428 428 - ret = dp_link_parse_timing_params1(link, DP_TEST_V_TOTAL_HI, 2, 429 429 - &link->dp_link.test_video.test_v_total); 428 428 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_V_TOTAL_HI, 2, 429 429 + &link->msm_dp_link.test_video.test_v_total); 430 430 if (ret) { 431 431 DRM_ERROR("failed to parse test_v_total(DP_TEST_V_TOTAL_HI)\n"); 432 432 return ret; 433 433 } 434 434 435 435 - ret = dp_link_parse_timing_params1(link, DP_TEST_H_START_HI, 2, 436 436 - &link->dp_link.test_video.test_h_start); 435 435 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_H_START_HI, 2, 436 436 + &link->msm_dp_link.test_video.test_h_start); 437 437 if (ret) { 438 438 DRM_ERROR("failed to parse test_h_start(DP_TEST_H_START_HI)\n"); 439 439 return ret; 440 440 } 441 441 442 442 - ret = dp_link_parse_timing_params1(link, DP_TEST_V_START_HI, 2, 443 443 - &link->dp_link.test_video.test_v_start); 442 442 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_V_START_HI, 2, 443 443 + &link->msm_dp_link.test_video.test_v_start); 444 444 if (ret) { 445 445 DRM_ERROR("failed to parse test_v_start(DP_TEST_V_START_HI)\n"); 446 446 return ret; 447 447 } 448 448 449 449 - ret = dp_link_parse_timing_params2(link, DP_TEST_HSYNC_HI, 2, 450 450 - &link->dp_link.test_video.test_hsync_pol, 451 451 - &link->dp_link.test_video.test_hsync_width); 449 449 + ret = msm_dp_link_parse_timing_params2(link, DP_TEST_HSYNC_HI, 2, 450 450 + &link->msm_dp_link.test_video.test_hsync_pol, 451 451 + &link->msm_dp_link.test_video.test_hsync_width); 452 452 if (ret) { 453 453 DRM_ERROR("failed to parse (DP_TEST_HSYNC_HI)\n"); 454 454 return ret; 455 455 } 456 456 457 457 - ret = dp_link_parse_timing_params2(link, DP_TEST_VSYNC_HI, 2, 458 458 - &link->dp_link.test_video.test_vsync_pol, 459 459 - &link->dp_link.test_video.test_vsync_width); 457 457 + ret = msm_dp_link_parse_timing_params2(link, DP_TEST_VSYNC_HI, 2, 458 458 + &link->msm_dp_link.test_video.test_vsync_pol, 459 459 + &link->msm_dp_link.test_video.test_vsync_width); 460 460 if (ret) { 461 461 DRM_ERROR("failed to parse (DP_TEST_VSYNC_HI)\n"); 462 462 return ret; 463 463 } 464 464 465 465 - ret = dp_link_parse_timing_params1(link, DP_TEST_H_WIDTH_HI, 2, 466 466 - &link->dp_link.test_video.test_h_width); 465 465 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_H_WIDTH_HI, 2, 466 466 + &link->msm_dp_link.test_video.test_h_width); 467 467 if (ret) { 468 468 DRM_ERROR("failed to parse test_h_width(DP_TEST_H_WIDTH_HI)\n"); 469 469 return ret; 470 470 } 471 471 472 472 - ret = dp_link_parse_timing_params1(link, DP_TEST_V_HEIGHT_HI, 2, 473 473 - &link->dp_link.test_video.test_v_height); 472 472 + ret = msm_dp_link_parse_timing_params1(link, DP_TEST_V_HEIGHT_HI, 2, 473 473 + &link->msm_dp_link.test_video.test_v_height); 474 474 if (ret) { 475 475 DRM_ERROR("failed to parse test_v_height\n"); 476 476 return ret; 477 477 } 478 478 479 479 - ret = dp_link_parse_timing_params3(link, DP_TEST_MISC1, 480 480 - &link->dp_link.test_video.test_rr_d); 481 481 - link->dp_link.test_video.test_rr_d &= DP_TEST_REFRESH_DENOMINATOR; 479 479 + ret = msm_dp_link_parse_timing_params3(link, DP_TEST_MISC1, 480 480 + &link->msm_dp_link.test_video.test_rr_d); 481 481 + link->msm_dp_link.test_video.test_rr_d &= DP_TEST_REFRESH_DENOMINATOR; 482 482 if (ret) { 483 483 DRM_ERROR("failed to parse test_rr_d (DP_TEST_MISC1)\n"); 484 484 return ret; 485 485 } 486 486 487 487 - ret = dp_link_parse_timing_params3(link, DP_TEST_REFRESH_RATE_NUMERATOR, 488 488 - &link->dp_link.test_video.test_rr_n); 487 487 + ret = msm_dp_link_parse_timing_params3(link, DP_TEST_REFRESH_RATE_NUMERATOR, 488 488 + &link->msm_dp_link.test_video.test_rr_n); 489 489 if (ret) { 490 490 DRM_ERROR("failed to parse test_rr_n\n"); 491 491 return ret; ··· 505 505 "TEST_V_HEIGHT = %d\n" 506 506 "TEST_REFRESH_DENOMINATOR = %d\n" 507 507 "TEST_REFRESH_NUMERATOR = %d\n", 508 508 - link->dp_link.test_video.test_video_pattern, 509 509 - link->dp_link.test_video.test_dyn_range, 510 510 - link->dp_link.test_video.test_bit_depth, 511 511 - link->dp_link.test_video.test_h_total, 512 512 - link->dp_link.test_video.test_v_total, 513 513 - link->dp_link.test_video.test_h_start, 514 514 - link->dp_link.test_video.test_v_start, 515 515 - link->dp_link.test_video.test_hsync_pol, 516 516 - link->dp_link.test_video.test_hsync_width, 517 517 - link->dp_link.test_video.test_vsync_pol, 518 518 - link->dp_link.test_video.test_vsync_width, 519 519 - link->dp_link.test_video.test_h_width, 520 520 - link->dp_link.test_video.test_v_height, 521 521 - link->dp_link.test_video.test_rr_d, 522 522 - link->dp_link.test_video.test_rr_n); 508 508 + link->msm_dp_link.test_video.test_video_pattern, 509 509 + link->msm_dp_link.test_video.test_dyn_range, 510 510 + link->msm_dp_link.test_video.test_bit_depth, 511 511 + link->msm_dp_link.test_video.test_h_total, 512 512 + link->msm_dp_link.test_video.test_v_total, 513 513 + link->msm_dp_link.test_video.test_h_start, 514 514 + link->msm_dp_link.test_video.test_v_start, 515 515 + link->msm_dp_link.test_video.test_hsync_pol, 516 516 + link->msm_dp_link.test_video.test_hsync_width, 517 517 + link->msm_dp_link.test_video.test_vsync_pol, 518 518 + link->msm_dp_link.test_video.test_vsync_width, 519 519 + link->msm_dp_link.test_video.test_h_width, 520 520 + link->msm_dp_link.test_video.test_v_height, 521 521 + link->msm_dp_link.test_video.test_rr_d, 522 522 + link->msm_dp_link.test_video.test_rr_n); 523 523 524 524 return ret; 525 525 } 526 526 527 527 /** 528 528 - * dp_link_parse_link_training_params() - parses link training parameters from 528 528 + * msm_dp_link_parse_link_training_params() - parses link training parameters from 529 529 * DPCD 530 530 * @link: Display Port Driver data 531 531 * 532 532 * Returns 0 if it successfully parses the link rate (Byte 0x219) and lane 533 533 * count (Byte 0x220), and if these values parse are valid. 534 534 */ 535 535 - static int dp_link_parse_link_training_params(struct dp_link_private *link) 535 535 + static int msm_dp_link_parse_link_training_params(struct msm_dp_link_private *link) 536 536 { 537 537 u8 bp; 538 538 ssize_t rlen; ··· 571 571 } 572 572 573 573 /** 574 574 - * dp_link_parse_phy_test_params() - parses the phy link parameters 574 574 + * msm_dp_link_parse_phy_test_params() - parses the phy link parameters 575 575 * @link: Display Port Driver data 576 576 * 577 577 * Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is being 578 578 * requested. 579 579 */ 580 580 - static int dp_link_parse_phy_test_params(struct dp_link_private *link) 580 580 + static int msm_dp_link_parse_phy_test_params(struct msm_dp_link_private *link) 581 581 { 582 582 u8 data; 583 583 ssize_t rlen; ··· 589 589 return rlen; 590 590 } 591 591 592 592 - link->dp_link.phy_params.phy_test_pattern_sel = data & 0x07; 592 592 + link->msm_dp_link.phy_params.phy_test_pattern_sel = data & 0x07; 593 593 594 594 drm_dbg_dp(link->drm_dev, "phy_test_pattern_sel = 0x%x\n", data); 595 595 ··· 608 608 } 609 609 610 610 /** 611 611 - * dp_link_is_video_audio_test_requested() - checks for audio/video link request 611 611 + * msm_dp_link_is_video_audio_test_requested() - checks for audio/video link request 612 612 * @link: link requested by the sink 613 613 * 614 614 * Returns true if the requested link is a permitted audio/video link. 615 615 */ 616 616 - static bool dp_link_is_video_audio_test_requested(u32 link) 616 616 + static bool msm_dp_link_is_video_audio_test_requested(u32 link) 617 617 { 618 618 u8 video_audio_test = (DP_TEST_LINK_VIDEO_PATTERN | 619 619 DP_TEST_LINK_AUDIO_PATTERN | ··· 624 624 } 625 625 626 626 /** 627 627 - * dp_link_parse_request() - parses link request parameters from sink 627 627 + * msm_dp_link_parse_request() - parses link request parameters from sink 628 628 * @link: Display Port Driver data 629 629 * 630 630 * Parses the DPCD to check if an automated link is requested (Byte 0x201), 631 631 * and what type of link automation is being requested (Byte 0x218). 632 632 */ 633 633 - static int dp_link_parse_request(struct dp_link_private *link) 633 633 + static int msm_dp_link_parse_request(struct msm_dp_link_private *link) 634 634 { 635 635 int ret = 0; 636 636 u8 data; ··· 672 672 drm_dbg_dp(link->drm_dev, "Test:(0x%x) requested\n", data); 673 673 link->request.test_requested = data; 674 674 if (link->request.test_requested == DP_TEST_LINK_PHY_TEST_PATTERN) { 675 675 - ret = dp_link_parse_phy_test_params(link); 675 675 + ret = msm_dp_link_parse_phy_test_params(link); 676 676 if (ret) 677 677 goto end; 678 678 - ret = dp_link_parse_link_training_params(link); 678 678 + ret = msm_dp_link_parse_link_training_params(link); 679 679 if (ret) 680 680 goto end; 681 681 } 682 682 683 683 if (link->request.test_requested == DP_TEST_LINK_TRAINING) { 684 684 - ret = dp_link_parse_link_training_params(link); 684 684 + ret = msm_dp_link_parse_link_training_params(link); 685 685 if (ret) 686 686 goto end; 687 687 } 688 688 689 689 - if (dp_link_is_video_audio_test_requested( 689 689 + if (msm_dp_link_is_video_audio_test_requested( 690 690 link->request.test_requested)) { 691 691 - ret = dp_link_parse_video_pattern_params(link); 691 691 + ret = msm_dp_link_parse_video_pattern_params(link); 692 692 if (ret) 693 693 goto end; 694 694 695 695 - ret = dp_link_parse_audio_pattern_params(link); 695 695 + ret = msm_dp_link_parse_audio_pattern_params(link); 696 696 } 697 697 end: 698 698 /* ··· 700 700 * a DP_TEST_NAK. 701 701 */ 702 702 if (ret) { 703 703 - link->dp_link.test_response = DP_TEST_NAK; 703 703 + link->msm_dp_link.test_response = DP_TEST_NAK; 704 704 } else { 705 705 if (link->request.test_requested != DP_TEST_LINK_EDID_READ) 706 706 - link->dp_link.test_response = DP_TEST_ACK; 706 706 + link->msm_dp_link.test_response = DP_TEST_ACK; 707 707 else 708 708 - link->dp_link.test_response = 708 708 + link->msm_dp_link.test_response = 709 709 DP_TEST_EDID_CHECKSUM_WRITE; 710 710 } 711 711 712 712 return ret; 713 713 } 714 714 715 715 - static int dp_link_parse_sink_status_field(struct dp_link_private *link) 715 715 + static int msm_dp_link_parse_sink_status_field(struct msm_dp_link_private *link) 716 716 { 717 717 int len; 718 718 719 719 - link->prev_sink_count = link->dp_link.sink_count; 719 719 + link->prev_sink_count = link->msm_dp_link.sink_count; 720 720 len = drm_dp_read_sink_count(link->aux); 721 721 if (len < 0) { 722 722 DRM_ERROR("DP parse sink count failed\n"); 723 723 return len; 724 724 } 725 725 - link->dp_link.sink_count = len; 725 725 + link->msm_dp_link.sink_count = len; 726 726 727 727 len = drm_dp_dpcd_read_link_status(link->aux, 728 728 link->link_status); ··· 731 731 return len; 732 732 } 733 733 734 734 - return dp_link_parse_request(link); 734 734 + return msm_dp_link_parse_request(link); 735 735 } 736 736 737 737 /** 738 738 - * dp_link_process_link_training_request() - processes new training requests 738 738 + * msm_dp_link_process_link_training_request() - processes new training requests 739 739 * @link: Display Port link data 740 740 * 741 741 * This function will handle new link training requests that are initiated by ··· 745 745 * The function will return 0 if a link training request has been processed, 746 746 * otherwise it will return -EINVAL. 747 747 */ 748 748 - static int dp_link_process_link_training_request(struct dp_link_private *link) 748 748 + static int msm_dp_link_process_link_training_request(struct msm_dp_link_private *link) 749 749 { 750 750 if (link->request.test_requested != DP_TEST_LINK_TRAINING) 751 751 return -EINVAL; ··· 756 756 link->request.test_link_rate, 757 757 link->request.test_lane_count); 758 758 759 759 - link->dp_link.link_params.num_lanes = link->request.test_lane_count; 760 760 - link->dp_link.link_params.rate = 759 759 + link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; 760 760 + link->msm_dp_link.link_params.rate = 761 761 drm_dp_bw_code_to_link_rate(link->request.test_link_rate); 762 762 763 763 return 0; 764 764 } 765 765 766 766 - bool dp_link_send_test_response(struct dp_link *dp_link) 766 766 + bool msm_dp_link_send_test_response(struct msm_dp_link *msm_dp_link) 767 767 { 768 768 - struct dp_link_private *link = NULL; 768 768 + struct msm_dp_link_private *link = NULL; 769 769 int ret = 0; 770 770 771 771 - if (!dp_link) { 771 771 + if (!msm_dp_link) { 772 772 DRM_ERROR("invalid input\n"); 773 773 return false; 774 774 } 775 775 776 776 - link = container_of(dp_link, struct dp_link_private, dp_link); 776 776 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 777 777 778 778 ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_RESPONSE, 779 779 - dp_link->test_response); 779 779 + msm_dp_link->test_response); 780 780 781 781 return ret == 1; 782 782 } 783 783 784 784 - int dp_link_psm_config(struct dp_link *dp_link, 785 785 - struct dp_link_info *link_info, bool enable) 784 784 + int msm_dp_link_psm_config(struct msm_dp_link *msm_dp_link, 785 785 + struct msm_dp_link_info *link_info, bool enable) 786 786 { 787 787 - struct dp_link_private *link = NULL; 787 787 + struct msm_dp_link_private *link = NULL; 788 788 int ret = 0; 789 789 790 790 - if (!dp_link) { 790 790 + if (!msm_dp_link) { 791 791 DRM_ERROR("invalid params\n"); 792 792 return -EINVAL; 793 793 } 794 794 795 795 - link = container_of(dp_link, struct dp_link_private, dp_link); 795 795 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 796 796 797 797 mutex_lock(&link->psm_mutex); 798 798 if (enable) 799 799 - ret = dp_aux_link_power_down(link->aux, link_info); 799 799 + ret = msm_dp_aux_link_power_down(link->aux, link_info); 800 800 else 801 801 - ret = dp_aux_link_power_up(link->aux, link_info); 801 801 + ret = msm_dp_aux_link_power_up(link->aux, link_info); 802 802 803 803 if (ret) 804 804 DRM_ERROR("Failed to %s low power mode\n", enable ? ··· 808 808 return ret; 809 809 } 810 810 811 811 - bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum) 811 811 + bool msm_dp_link_send_edid_checksum(struct msm_dp_link *msm_dp_link, u8 checksum) 812 812 { 813 813 - struct dp_link_private *link = NULL; 813 813 + struct msm_dp_link_private *link = NULL; 814 814 int ret = 0; 815 815 816 816 - if (!dp_link) { 816 816 + if (!msm_dp_link) { 817 817 DRM_ERROR("invalid input\n"); 818 818 return false; 819 819 } 820 820 821 821 - link = container_of(dp_link, struct dp_link_private, dp_link); 821 821 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 822 822 823 823 ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_EDID_CHECKSUM, 824 824 checksum); 825 825 return ret == 1; 826 826 } 827 827 828 828 - static void dp_link_parse_vx_px(struct dp_link_private *link) 828 828 + static void msm_dp_link_parse_vx_px(struct msm_dp_link_private *link) 829 829 { 830 830 drm_dbg_dp(link->drm_dev, "vx: 0=%d, 1=%d, 2=%d, 3=%d\n", 831 831 drm_dp_get_adjust_request_voltage(link->link_status, 0), ··· 845 845 */ 846 846 drm_dbg_dp(link->drm_dev, 847 847 "Current: v_level = 0x%x, p_level = 0x%x\n", 848 848 - link->dp_link.phy_params.v_level, 849 849 - link->dp_link.phy_params.p_level); 850 850 - link->dp_link.phy_params.v_level = 848 848 + link->msm_dp_link.phy_params.v_level, 849 849 + link->msm_dp_link.phy_params.p_level); 850 850 + link->msm_dp_link.phy_params.v_level = 851 851 drm_dp_get_adjust_request_voltage(link->link_status, 0); 852 852 - link->dp_link.phy_params.p_level = 852 852 + link->msm_dp_link.phy_params.p_level = 853 853 drm_dp_get_adjust_request_pre_emphasis(link->link_status, 0); 854 854 855 855 - link->dp_link.phy_params.p_level >>= DP_TRAIN_PRE_EMPHASIS_SHIFT; 855 855 + link->msm_dp_link.phy_params.p_level >>= DP_TRAIN_PRE_EMPHASIS_SHIFT; 856 856 857 857 drm_dbg_dp(link->drm_dev, 858 858 "Requested: v_level = 0x%x, p_level = 0x%x\n", 859 859 - link->dp_link.phy_params.v_level, 860 860 - link->dp_link.phy_params.p_level); 859 859 + link->msm_dp_link.phy_params.v_level, 860 860 + link->msm_dp_link.phy_params.p_level); 861 861 } 862 862 863 863 /** 864 864 - * dp_link_process_phy_test_pattern_request() - process new phy link requests 864 864 + * msm_dp_link_process_phy_test_pattern_request() - process new phy link requests 865 865 * @link: Display Port Driver data 866 866 * 867 867 * This function will handle new phy link pattern requests that are initiated 868 868 * by the sink. The function will return 0 if a phy link pattern has been 869 869 * processed, otherwise it will return -EINVAL. 870 870 */ 871 871 - static int dp_link_process_phy_test_pattern_request( 872 872 - struct dp_link_private *link) 871 871 + static int msm_dp_link_process_phy_test_pattern_request( 872 872 + struct msm_dp_link_private *link) 873 873 { 874 874 if (!(link->request.test_requested & DP_TEST_LINK_PHY_TEST_PATTERN)) { 875 875 drm_dbg_dp(link->drm_dev, "no phy test\n"); ··· 886 886 887 887 drm_dbg_dp(link->drm_dev, 888 888 "Current: rate = 0x%x, lane count = 0x%x\n", 889 889 - link->dp_link.link_params.rate, 890 890 - link->dp_link.link_params.num_lanes); 889 889 + link->msm_dp_link.link_params.rate, 890 890 + link->msm_dp_link.link_params.num_lanes); 891 891 892 892 drm_dbg_dp(link->drm_dev, 893 893 "Requested: rate = 0x%x, lane count = 0x%x\n", 894 894 link->request.test_link_rate, 895 895 link->request.test_lane_count); 896 896 897 897 - link->dp_link.link_params.num_lanes = link->request.test_lane_count; 898 898 - link->dp_link.link_params.rate = 897 897 + link->msm_dp_link.link_params.num_lanes = link->request.test_lane_count; 898 898 + link->msm_dp_link.link_params.rate = 899 899 drm_dp_bw_code_to_link_rate(link->request.test_link_rate); 900 900 901 901 - dp_link_parse_vx_px(link); 901 901 + msm_dp_link_parse_vx_px(link); 902 902 903 903 return 0; 904 904 } 905 905 906 906 - static bool dp_link_read_psr_error_status(struct dp_link_private *link) 906 906 + static bool msm_dp_link_read_psr_error_status(struct msm_dp_link_private *link) 907 907 { 908 908 u8 status; 909 909 ··· 921 921 return true; 922 922 } 923 923 924 924 - static bool dp_link_psr_capability_changed(struct dp_link_private *link) 924 924 + static bool msm_dp_link_psr_capability_changed(struct msm_dp_link_private *link) 925 925 { 926 926 u8 status; 927 927 ··· 941 941 } 942 942 943 943 /** 944 944 - * dp_link_process_link_status_update() - processes link status updates 944 944 + * msm_dp_link_process_link_status_update() - processes link status updates 945 945 * @link: Display Port link module data 946 946 * 947 947 * This function will check for changes in the link status, e.g. clock ··· 951 951 * The function will return 0 if the a link status update has been processed, 952 952 * otherwise it will return -EINVAL. 953 953 */ 954 954 - static int dp_link_process_link_status_update(struct dp_link_private *link) 954 954 + static int msm_dp_link_process_link_status_update(struct msm_dp_link_private *link) 955 955 { 956 956 bool channel_eq_done = drm_dp_channel_eq_ok(link->link_status, 957 957 - link->dp_link.link_params.num_lanes); 957 957 + link->msm_dp_link.link_params.num_lanes); 958 958 959 959 bool clock_recovery_done = drm_dp_clock_recovery_ok(link->link_status, 960 960 - link->dp_link.link_params.num_lanes); 960 960 + link->msm_dp_link.link_params.num_lanes); 961 961 962 962 drm_dbg_dp(link->drm_dev, 963 963 "channel_eq_done = %d, clock_recovery_done = %d\n", ··· 970 970 } 971 971 972 972 /** 973 973 - * dp_link_process_ds_port_status_change() - process port status changes 973 973 + * msm_dp_link_process_ds_port_status_change() - process port status changes 974 974 * @link: Display Port Driver data 975 975 * 976 976 * This function will handle downstream port updates that are initiated by ··· 980 980 * The function will return 0 if a downstream port update has been 981 981 * processed, otherwise it will return -EINVAL. 982 982 */ 983 983 - static int dp_link_process_ds_port_status_change(struct dp_link_private *link) 983 983 + static int msm_dp_link_process_ds_port_status_change(struct msm_dp_link_private *link) 984 984 { 985 985 if (get_link_status(link->link_status, DP_LANE_ALIGN_STATUS_UPDATED) & 986 986 DP_DOWNSTREAM_PORT_STATUS_CHANGED) 987 987 goto reset; 988 988 989 989 - if (link->prev_sink_count == link->dp_link.sink_count) 989 989 + if (link->prev_sink_count == link->msm_dp_link.sink_count) 990 990 return -EINVAL; 991 991 992 992 reset: 993 993 /* reset prev_sink_count */ 994 994 - link->prev_sink_count = link->dp_link.sink_count; 994 994 + link->prev_sink_count = link->msm_dp_link.sink_count; 995 995 996 996 return 0; 997 997 } 998 998 999 999 - static bool dp_link_is_video_pattern_requested(struct dp_link_private *link) 999 999 + static bool msm_dp_link_is_video_pattern_requested(struct msm_dp_link_private *link) 1000 1000 { 1001 1001 return (link->request.test_requested & DP_TEST_LINK_VIDEO_PATTERN) 1002 1002 && !(link->request.test_requested & 1003 1003 DP_TEST_LINK_AUDIO_DISABLED_VIDEO); 1004 1004 } 1005 1005 1006 1006 - static bool dp_link_is_audio_pattern_requested(struct dp_link_private *link) 1006 1006 + static bool msm_dp_link_is_audio_pattern_requested(struct msm_dp_link_private *link) 1007 1007 { 1008 1008 return (link->request.test_requested & DP_TEST_LINK_AUDIO_PATTERN); 1009 1009 } 1010 1010 1011 1011 - static void dp_link_reset_data(struct dp_link_private *link) 1011 1011 + static void msm_dp_link_reset_data(struct msm_dp_link_private *link) 1012 1012 { 1013 1013 - link->request = (const struct dp_link_request){ 0 }; 1014 1014 - link->dp_link.test_video = (const struct dp_link_test_video){ 0 }; 1015 1015 - link->dp_link.test_video.test_bit_depth = DP_TEST_BIT_DEPTH_UNKNOWN; 1016 1016 - link->dp_link.test_audio = (const struct dp_link_test_audio){ 0 }; 1017 1017 - link->dp_link.phy_params.phy_test_pattern_sel = 0; 1018 1018 - link->dp_link.sink_request = 0; 1019 1019 - link->dp_link.test_response = 0; 1013 1013 + link->request = (const struct msm_dp_link_request){ 0 }; 1014 1014 + link->msm_dp_link.test_video = (const struct msm_dp_link_test_video){ 0 }; 1015 1015 + link->msm_dp_link.test_video.test_bit_depth = DP_TEST_BIT_DEPTH_UNKNOWN; 1016 1016 + link->msm_dp_link.test_audio = (const struct msm_dp_link_test_audio){ 0 }; 1017 1017 + link->msm_dp_link.phy_params.phy_test_pattern_sel = 0; 1018 1018 + link->msm_dp_link.sink_request = 0; 1019 1019 + link->msm_dp_link.test_response = 0; 1020 1020 } 1021 1021 1022 1022 /** 1023 1023 - * dp_link_process_request() - handle HPD IRQ transition to HIGH 1024 1024 - * @dp_link: pointer to link module data 1023 1023 + * msm_dp_link_process_request() - handle HPD IRQ transition to HIGH 1024 1024 + * @msm_dp_link: pointer to link module data 1025 1025 * 1026 1026 * This function will handle the HPD IRQ state transitions from LOW to HIGH 1027 1027 * (including cases when there are back to back HPD IRQ HIGH) indicating 1028 1028 * the start of a new link training request or sink status update. 1029 1029 */ 1030 1030 - int dp_link_process_request(struct dp_link *dp_link) 1030 1030 + int msm_dp_link_process_request(struct msm_dp_link *msm_dp_link) 1031 1031 { 1032 1032 int ret = 0; 1033 1033 - struct dp_link_private *link; 1033 1033 + struct msm_dp_link_private *link; 1034 1034 1035 1035 - if (!dp_link) { 1035 1035 + if (!msm_dp_link) { 1036 1036 DRM_ERROR("invalid input\n"); 1037 1037 return -EINVAL; 1038 1038 } 1039 1039 1040 1040 - link = container_of(dp_link, struct dp_link_private, dp_link); 1040 1040 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 1041 1041 1042 1042 - dp_link_reset_data(link); 1042 1042 + msm_dp_link_reset_data(link); 1043 1043 1044 1044 - ret = dp_link_parse_sink_status_field(link); 1044 1044 + ret = msm_dp_link_parse_sink_status_field(link); 1045 1045 if (ret) 1046 1046 return ret; 1047 1047 1048 1048 if (link->request.test_requested == DP_TEST_LINK_EDID_READ) { 1049 1049 - dp_link->sink_request |= DP_TEST_LINK_EDID_READ; 1050 1050 - } else if (!dp_link_process_ds_port_status_change(link)) { 1051 1051 - dp_link->sink_request |= DS_PORT_STATUS_CHANGED; 1052 1052 - } else if (!dp_link_process_link_training_request(link)) { 1053 1053 - dp_link->sink_request |= DP_TEST_LINK_TRAINING; 1054 1054 - } else if (!dp_link_process_phy_test_pattern_request(link)) { 1055 1055 - dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN; 1056 1056 - } else if (dp_link_read_psr_error_status(link)) { 1049 1049 + msm_dp_link->sink_request |= DP_TEST_LINK_EDID_READ; 1050 1050 + } else if (!msm_dp_link_process_ds_port_status_change(link)) { 1051 1051 + msm_dp_link->sink_request |= DS_PORT_STATUS_CHANGED; 1052 1052 + } else if (!msm_dp_link_process_link_training_request(link)) { 1053 1053 + msm_dp_link->sink_request |= DP_TEST_LINK_TRAINING; 1054 1054 + } else if (!msm_dp_link_process_phy_test_pattern_request(link)) { 1055 1055 + msm_dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN; 1056 1056 + } else if (msm_dp_link_read_psr_error_status(link)) { 1057 1057 DRM_ERROR("PSR IRQ_HPD received\n"); 1058 1058 - } else if (dp_link_psr_capability_changed(link)) { 1058 1058 + } else if (msm_dp_link_psr_capability_changed(link)) { 1059 1059 drm_dbg_dp(link->drm_dev, "PSR Capability changed\n"); 1060 1060 } else { 1061 1061 - ret = dp_link_process_link_status_update(link); 1061 1061 + ret = msm_dp_link_process_link_status_update(link); 1062 1062 if (!ret) { 1063 1063 - dp_link->sink_request |= DP_LINK_STATUS_UPDATED; 1063 1063 + msm_dp_link->sink_request |= DP_LINK_STATUS_UPDATED; 1064 1064 } else { 1065 1065 - if (dp_link_is_video_pattern_requested(link)) { 1065 1065 + if (msm_dp_link_is_video_pattern_requested(link)) { 1066 1066 ret = 0; 1067 1067 - dp_link->sink_request |= DP_TEST_LINK_VIDEO_PATTERN; 1067 1067 + msm_dp_link->sink_request |= DP_TEST_LINK_VIDEO_PATTERN; 1068 1068 } 1069 1069 - if (dp_link_is_audio_pattern_requested(link)) { 1070 1070 - dp_link->sink_request |= DP_TEST_LINK_AUDIO_PATTERN; 1069 1069 + if (msm_dp_link_is_audio_pattern_requested(link)) { 1070 1070 + msm_dp_link->sink_request |= DP_TEST_LINK_AUDIO_PATTERN; 1071 1071 ret = -EINVAL; 1072 1072 } 1073 1073 } 1074 1074 } 1075 1075 1076 1076 drm_dbg_dp(link->drm_dev, "sink request=%#x\n", 1077 1077 - dp_link->sink_request); 1077 1077 + msm_dp_link->sink_request); 1078 1078 return ret; 1079 1079 } 1080 1080 1081 1081 - int dp_link_get_colorimetry_config(struct dp_link *dp_link) 1081 1081 + int msm_dp_link_get_colorimetry_config(struct msm_dp_link *msm_dp_link) 1082 1082 { 1083 1083 u32 cc = DP_MISC0_COLORIMERY_CFG_LEGACY_RGB; 1084 1084 - struct dp_link_private *link; 1084 1084 + struct msm_dp_link_private *link; 1085 1085 1086 1086 - if (!dp_link) { 1086 1086 + if (!msm_dp_link) { 1087 1087 DRM_ERROR("invalid input\n"); 1088 1088 return -EINVAL; 1089 1089 } 1090 1090 1091 1091 - link = container_of(dp_link, struct dp_link_private, dp_link); 1091 1091 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 1092 1092 1093 1093 /* 1094 1094 * Unless a video pattern CTS test is ongoing, use RGB_VESA 1095 1095 * Only RGB_VESA and RGB_CEA supported for now 1096 1096 */ 1097 1097 - if (dp_link_is_video_pattern_requested(link)) { 1098 1098 - if (link->dp_link.test_video.test_dyn_range & 1097 1097 + if (msm_dp_link_is_video_pattern_requested(link)) { 1098 1098 + if (link->msm_dp_link.test_video.test_dyn_range & 1099 1099 DP_TEST_DYNAMIC_RANGE_CEA) 1100 1100 cc = DP_MISC0_COLORIMERY_CFG_CEA_RGB; 1101 1101 } ··· 1103 1103 return cc; 1104 1104 } 1105 1105 1106 1106 - int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status) 1106 1106 + int msm_dp_link_adjust_levels(struct msm_dp_link *msm_dp_link, u8 *link_status) 1107 1107 { 1108 1108 int i; 1109 1109 u8 max_p_level; 1110 1110 int v_max = 0, p_max = 0; 1111 1111 - struct dp_link_private *link; 1111 1111 + struct msm_dp_link_private *link; 1112 1112 1113 1113 - if (!dp_link) { 1113 1113 + if (!msm_dp_link) { 1114 1114 DRM_ERROR("invalid input\n"); 1115 1115 return -EINVAL; 1116 1116 } 1117 1117 1118 1118 - link = container_of(dp_link, struct dp_link_private, dp_link); 1118 1118 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 1119 1119 1120 1120 /* use the max level across lanes */ 1121 1121 - for (i = 0; i < dp_link->link_params.num_lanes; i++) { 1121 1121 + for (i = 0; i < msm_dp_link->link_params.num_lanes; i++) { 1122 1122 u8 data_v = drm_dp_get_adjust_request_voltage(link_status, i); 1123 1123 u8 data_p = drm_dp_get_adjust_request_pre_emphasis(link_status, 1124 1124 i); ··· 1131 1131 p_max = data_p; 1132 1132 } 1133 1133 1134 1134 - dp_link->phy_params.v_level = v_max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; 1135 1135 - dp_link->phy_params.p_level = p_max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; 1134 1134 + msm_dp_link->phy_params.v_level = v_max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; 1135 1135 + msm_dp_link->phy_params.p_level = p_max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; 1136 1136 1137 1137 /** 1138 1138 * Adjust the voltage swing and pre-emphasis level combination to within 1139 1139 * the allowable range. 1140 1140 */ 1141 1141 - if (dp_link->phy_params.v_level > DP_TRAIN_LEVEL_MAX) { 1141 1141 + if (msm_dp_link->phy_params.v_level > DP_TRAIN_LEVEL_MAX) { 1142 1142 drm_dbg_dp(link->drm_dev, 1143 1143 "Requested vSwingLevel=%d, change to %d\n", 1144 1144 - dp_link->phy_params.v_level, 1144 1144 + msm_dp_link->phy_params.v_level, 1145 1145 DP_TRAIN_LEVEL_MAX); 1146 1146 - dp_link->phy_params.v_level = DP_TRAIN_LEVEL_MAX; 1146 1146 + msm_dp_link->phy_params.v_level = DP_TRAIN_LEVEL_MAX; 1147 1147 } 1148 1148 1149 1149 - if (dp_link->phy_params.p_level > DP_TRAIN_LEVEL_MAX) { 1149 1149 + if (msm_dp_link->phy_params.p_level > DP_TRAIN_LEVEL_MAX) { 1150 1150 drm_dbg_dp(link->drm_dev, 1151 1151 "Requested preEmphasisLevel=%d, change to %d\n", 1152 1152 - dp_link->phy_params.p_level, 1152 1152 + msm_dp_link->phy_params.p_level, 1153 1153 DP_TRAIN_LEVEL_MAX); 1154 1154 - dp_link->phy_params.p_level = DP_TRAIN_LEVEL_MAX; 1154 1154 + msm_dp_link->phy_params.p_level = DP_TRAIN_LEVEL_MAX; 1155 1155 } 1156 1156 1157 1157 - max_p_level = DP_TRAIN_LEVEL_MAX - dp_link->phy_params.v_level; 1158 1158 - if (dp_link->phy_params.p_level > max_p_level) { 1157 1157 + max_p_level = DP_TRAIN_LEVEL_MAX - msm_dp_link->phy_params.v_level; 1158 1158 + if (msm_dp_link->phy_params.p_level > max_p_level) { 1159 1159 drm_dbg_dp(link->drm_dev, 1160 1160 "Requested preEmphasisLevel=%d, change to %d\n", 1161 1161 - dp_link->phy_params.p_level, 1161 1161 + msm_dp_link->phy_params.p_level, 1162 1162 max_p_level); 1163 1163 - dp_link->phy_params.p_level = max_p_level; 1163 1163 + msm_dp_link->phy_params.p_level = max_p_level; 1164 1164 } 1165 1165 1166 1166 drm_dbg_dp(link->drm_dev, "adjusted: v_level=%d, p_level=%d\n", 1167 1167 - dp_link->phy_params.v_level, dp_link->phy_params.p_level); 1167 1167 + msm_dp_link->phy_params.v_level, msm_dp_link->phy_params.p_level); 1168 1168 1169 1169 return 0; 1170 1170 } 1171 1171 1172 1172 - void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link) 1172 1172 + void msm_dp_link_reset_phy_params_vx_px(struct msm_dp_link *msm_dp_link) 1173 1173 { 1174 1174 - dp_link->phy_params.v_level = 0; 1175 1175 - dp_link->phy_params.p_level = 0; 1174 1174 + msm_dp_link->phy_params.v_level = 0; 1175 1175 + msm_dp_link->phy_params.p_level = 0; 1176 1176 } 1177 1177 1178 1178 - u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp) 1178 1178 + u32 msm_dp_link_get_test_bits_depth(struct msm_dp_link *msm_dp_link, u32 bpp) 1179 1179 { 1180 1180 u32 tbd; 1181 1181 - struct dp_link_private *link; 1181 1181 + struct msm_dp_link_private *link; 1182 1182 1183 1183 - link = container_of(dp_link, struct dp_link_private, dp_link); 1183 1183 + link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link); 1184 1184 1185 1185 /* 1186 1186 * Few simplistic rules and assumptions made here: ··· 1209 1209 return tbd; 1210 1210 } 1211 1211 1212 1212 - struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux) 1212 1212 + struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux) 1213 1213 { 1214 1214 - struct dp_link_private *link; 1215 1215 - struct dp_link *dp_link; 1214 1214 + struct msm_dp_link_private *link; 1215 1215 + struct msm_dp_link *msm_dp_link; 1216 1216 1217 1217 if (!dev || !aux) { 1218 1218 DRM_ERROR("invalid input\n"); ··· 1226 1226 link->aux = aux; 1227 1227 1228 1228 mutex_init(&link->psm_mutex); 1229 1229 - dp_link = &link->dp_link; 1229 1229 + msm_dp_link = &link->msm_dp_link; 1230 1230 1231 1231 - return dp_link; 1231 1231 + return msm_dp_link; 1232 1232 }

+22 -22

drivers/gpu/drm/msm/dp/dp_link.h

reviewed

··· 12 12 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF 13 13 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 14 14 15 15 - struct dp_link_info { 15 15 + struct msm_dp_link_info { 16 16 unsigned char revision; 17 17 unsigned int rate; 18 18 unsigned int num_lanes; ··· 21 21 22 22 #define DP_TRAIN_LEVEL_MAX 3 23 23 24 24 - struct dp_link_test_video { 24 24 + struct msm_dp_link_test_video { 25 25 u32 test_video_pattern; 26 26 u32 test_bit_depth; 27 27 u32 test_dyn_range; ··· 39 39 u32 test_rr_n; 40 40 }; 41 41 42 42 - struct dp_link_test_audio { 42 42 + struct msm_dp_link_test_audio { 43 43 u32 test_audio_sampling_rate; 44 44 u32 test_audio_channel_count; 45 45 u32 test_audio_pattern_type; ··· 53 53 u32 test_audio_period_ch_8; 54 54 }; 55 55 56 56 - struct dp_link_phy_params { 56 56 + struct msm_dp_link_phy_params { 57 57 u32 phy_test_pattern_sel; 58 58 u8 v_level; 59 59 u8 p_level; 60 60 }; 61 61 62 62 - struct dp_link { 62 62 + struct msm_dp_link { 63 63 u32 sink_request; 64 64 u32 test_response; 65 65 66 66 u8 sink_count; 67 67 - struct dp_link_test_video test_video; 68 68 - struct dp_link_test_audio test_audio; 69 69 - struct dp_link_phy_params phy_params; 70 70 - struct dp_link_info link_params; 67 67 + struct msm_dp_link_test_video test_video; 68 68 + struct msm_dp_link_test_audio test_audio; 69 69 + struct msm_dp_link_phy_params phy_params; 70 70 + struct msm_dp_link_info link_params; 71 71 }; 72 72 73 73 /** ··· 78 78 * git bit depth value. This function assumes that bit depth has 79 79 * already been validated. 80 80 */ 81 81 - static inline u32 dp_link_bit_depth_to_bpp(u32 tbd) 81 81 + static inline u32 msm_dp_link_bit_depth_to_bpp(u32 tbd) 82 82 { 83 83 /* 84 84 * Few simplistic rules and assumptions made here: ··· 99 99 } 100 100 } 101 101 102 102 - void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link); 103 103 - u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp); 104 104 - int dp_link_process_request(struct dp_link *dp_link); 105 105 - int dp_link_get_colorimetry_config(struct dp_link *dp_link); 106 106 - int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status); 107 107 - bool dp_link_send_test_response(struct dp_link *dp_link); 108 108 - int dp_link_psm_config(struct dp_link *dp_link, 109 109 - struct dp_link_info *link_info, bool enable); 110 110 - bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum); 102 102 + void msm_dp_link_reset_phy_params_vx_px(struct msm_dp_link *msm_dp_link); 103 103 + u32 msm_dp_link_get_test_bits_depth(struct msm_dp_link *msm_dp_link, u32 bpp); 104 104 + int msm_dp_link_process_request(struct msm_dp_link *msm_dp_link); 105 105 + int msm_dp_link_get_colorimetry_config(struct msm_dp_link *msm_dp_link); 106 106 + int msm_dp_link_adjust_levels(struct msm_dp_link *msm_dp_link, u8 *link_status); 107 107 + bool msm_dp_link_send_test_response(struct msm_dp_link *msm_dp_link); 108 108 + int msm_dp_link_psm_config(struct msm_dp_link *msm_dp_link, 109 109 + struct msm_dp_link_info *link_info, bool enable); 110 110 + bool msm_dp_link_send_edid_checksum(struct msm_dp_link *msm_dp_link, u8 checksum); 111 111 112 112 /** 113 113 - * dp_link_get() - get the functionalities of dp test module 113 113 + * msm_dp_link_get() - get the functionalities of dp test module 114 114 * 115 115 * 116 116 - * return: a pointer to dp_link struct 116 116 + * return: a pointer to msm_dp_link struct 117 117 */ 118 118 - struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux); 118 118 + struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux); 119 119 120 120 #endif /* _DP_LINK_H_ */

+127 -127

drivers/gpu/drm/msm/dp/dp_panel.c

reviewed

··· 14 14 #define DP_MAX_NUM_DP_LANES 4 15 15 #define DP_LINK_RATE_HBR2 540000 /* kbytes */ 16 16 17 17 - struct dp_panel_private { 17 17 + struct msm_dp_panel_private { 18 18 struct device *dev; 19 19 struct drm_device *drm_dev; 20 20 - struct dp_panel dp_panel; 20 20 + struct msm_dp_panel msm_dp_panel; 21 21 struct drm_dp_aux *aux; 22 22 - struct dp_link *link; 23 23 - struct dp_catalog *catalog; 22 22 + struct msm_dp_link *link; 23 23 + struct msm_dp_catalog *catalog; 24 24 bool panel_on; 25 25 }; 26 26 27 27 - static void dp_panel_read_psr_cap(struct dp_panel_private *panel) 27 27 + static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) 28 28 { 29 29 ssize_t rlen; 30 30 - struct dp_panel *dp_panel; 30 30 + struct msm_dp_panel *msm_dp_panel; 31 31 32 32 - dp_panel = &panel->dp_panel; 32 32 + msm_dp_panel = &panel->msm_dp_panel; 33 33 34 34 /* edp sink */ 35 35 - if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 35 35 + if (msm_dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) { 36 36 rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT, 37 37 - &dp_panel->psr_cap, sizeof(dp_panel->psr_cap)); 38 38 - if (rlen == sizeof(dp_panel->psr_cap)) { 37 37 + &msm_dp_panel->psr_cap, sizeof(msm_dp_panel->psr_cap)); 38 38 + if (rlen == sizeof(msm_dp_panel->psr_cap)) { 39 39 drm_dbg_dp(panel->drm_dev, 40 40 "psr version: 0x%x, psr_cap: 0x%x\n", 41 41 - dp_panel->psr_cap.version, 42 42 - dp_panel->psr_cap.capabilities); 41 41 + msm_dp_panel->psr_cap.version, 42 42 + msm_dp_panel->psr_cap.capabilities); 43 43 } else 44 44 DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen); 45 45 } 46 46 } 47 47 48 48 - static int dp_panel_read_dpcd(struct dp_panel *dp_panel) 48 48 + static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel) 49 49 { 50 50 int rc; 51 51 - struct dp_panel_private *panel; 52 52 - struct dp_link_info *link_info; 51 51 + struct msm_dp_panel_private *panel; 52 52 + struct msm_dp_link_info *link_info; 53 53 u8 *dpcd, major, minor; 54 54 55 55 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 56 56 - dpcd = dp_panel->dpcd; 55 55 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 56 56 + dpcd = msm_dp_panel->dpcd; 57 57 rc = drm_dp_read_dpcd_caps(panel->aux, dpcd); 58 58 if (rc) 59 59 return rc; 60 60 61 61 - dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); 62 62 - link_info = &dp_panel->link_info; 61 61 + msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); 62 62 + link_info = &msm_dp_panel->link_info; 63 63 link_info->revision = dpcd[DP_DPCD_REV]; 64 64 major = (link_info->revision >> 4) & 0x0f; 65 65 minor = link_info->revision & 0x0f; ··· 68 68 link_info->num_lanes = drm_dp_max_lane_count(dpcd); 69 69 70 70 /* Limit data lanes from data-lanes of endpoint property of dtsi */ 71 71 - if (link_info->num_lanes > dp_panel->max_dp_lanes) 72 72 - link_info->num_lanes = dp_panel->max_dp_lanes; 71 71 + if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) 72 72 + link_info->num_lanes = msm_dp_panel->max_dp_lanes; 73 73 74 74 /* Limit link rate from link-frequencies of endpoint property of dtsi */ 75 75 - if (link_info->rate > dp_panel->max_dp_link_rate) 76 76 - link_info->rate = dp_panel->max_dp_link_rate; 75 75 + if (link_info->rate > msm_dp_panel->max_dp_link_rate) 76 76 + link_info->rate = msm_dp_panel->max_dp_link_rate; 77 77 78 78 drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor); 79 79 drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate); ··· 82 82 if (drm_dp_enhanced_frame_cap(dpcd)) 83 83 link_info->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; 84 84 85 85 - dp_panel_read_psr_cap(panel); 85 85 + msm_dp_panel_read_psr_cap(panel); 86 86 87 87 return rc; 88 88 } 89 89 90 90 - static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, 90 90 + static u32 msm_dp_panel_get_supported_bpp(struct msm_dp_panel *msm_dp_panel, 91 91 u32 mode_edid_bpp, u32 mode_pclk_khz) 92 92 { 93 93 - const struct dp_link_info *link_info; 93 93 + const struct msm_dp_link_info *link_info; 94 94 const u32 max_supported_bpp = 30, min_supported_bpp = 18; 95 95 u32 bpp, data_rate_khz; 96 96 97 97 bpp = min(mode_edid_bpp, max_supported_bpp); 98 98 99 99 - link_info = &dp_panel->link_info; 99 99 + link_info = &msm_dp_panel->link_info; 100 100 data_rate_khz = link_info->num_lanes * link_info->rate * 8; 101 101 102 102 do { ··· 108 108 return min_supported_bpp; 109 109 } 110 110 111 111 - int dp_panel_read_sink_caps(struct dp_panel *dp_panel, 111 111 + int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, 112 112 struct drm_connector *connector) 113 113 { 114 114 int rc, bw_code; 115 115 int count; 116 116 - struct dp_panel_private *panel; 116 116 + struct msm_dp_panel_private *panel; 117 117 118 118 - if (!dp_panel || !connector) { 118 118 + if (!msm_dp_panel || !connector) { 119 119 DRM_ERROR("invalid input\n"); 120 120 return -EINVAL; 121 121 } 122 122 123 123 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 123 123 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 124 124 125 125 drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n", 126 126 - dp_panel->max_dp_lanes, dp_panel->max_dp_link_rate); 126 126 + msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate); 127 127 128 128 - rc = dp_panel_read_dpcd(dp_panel); 128 128 + rc = msm_dp_panel_read_dpcd(msm_dp_panel); 129 129 if (rc) { 130 130 DRM_ERROR("read dpcd failed %d\n", rc); 131 131 return rc; 132 132 } 133 133 134 134 - bw_code = drm_dp_link_rate_to_bw_code(dp_panel->link_info.rate); 134 134 + bw_code = drm_dp_link_rate_to_bw_code(msm_dp_panel->link_info.rate); 135 135 if (!is_link_rate_valid(bw_code) || 136 136 - !is_lane_count_valid(dp_panel->link_info.num_lanes) || 137 137 - (bw_code > dp_panel->max_bw_code)) { 138 138 - DRM_ERROR("Illegal link rate=%d lane=%d\n", dp_panel->link_info.rate, 139 139 - dp_panel->link_info.num_lanes); 136 136 + !is_lane_count_valid(msm_dp_panel->link_info.num_lanes) || 137 137 + (bw_code > msm_dp_panel->max_bw_code)) { 138 138 + DRM_ERROR("Illegal link rate=%d lane=%d\n", msm_dp_panel->link_info.rate, 139 139 + msm_dp_panel->link_info.num_lanes); 140 140 return -EINVAL; 141 141 } 142 142 143 143 - if (drm_dp_is_branch(dp_panel->dpcd)) { 143 143 + if (drm_dp_is_branch(msm_dp_panel->dpcd)) { 144 144 count = drm_dp_read_sink_count(panel->aux); 145 145 if (!count) { 146 146 panel->link->sink_count = 0; ··· 148 148 } 149 149 } 150 150 151 151 - rc = drm_dp_read_downstream_info(panel->aux, dp_panel->dpcd, 152 152 - dp_panel->downstream_ports); 151 151 + rc = drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, 152 152 + msm_dp_panel->downstream_ports); 153 153 if (rc) 154 154 return rc; 155 155 156 156 - drm_edid_free(dp_panel->drm_edid); 156 156 + drm_edid_free(msm_dp_panel->drm_edid); 157 157 158 158 - dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc); 158 158 + msm_dp_panel->drm_edid = drm_edid_read_ddc(connector, &panel->aux->ddc); 159 159 160 160 - drm_edid_connector_update(connector, dp_panel->drm_edid); 160 160 + drm_edid_connector_update(connector, msm_dp_panel->drm_edid); 161 161 162 162 - if (!dp_panel->drm_edid) { 162 162 + if (!msm_dp_panel->drm_edid) { 163 163 DRM_ERROR("panel edid read failed\n"); 164 164 /* check edid read fail is due to unplug */ 165 165 - if (!dp_catalog_link_is_connected(panel->catalog)) { 165 165 + if (!msm_dp_catalog_link_is_connected(panel->catalog)) { 166 166 rc = -ETIMEDOUT; 167 167 goto end; 168 168 } ··· 172 172 return rc; 173 173 } 174 174 175 175 - u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, 175 175 + u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, 176 176 u32 mode_edid_bpp, u32 mode_pclk_khz) 177 177 { 178 178 - struct dp_panel_private *panel; 178 178 + struct msm_dp_panel_private *panel; 179 179 u32 bpp; 180 180 181 181 - if (!dp_panel || !mode_edid_bpp || !mode_pclk_khz) { 181 181 + if (!msm_dp_panel || !mode_edid_bpp || !mode_pclk_khz) { 182 182 DRM_ERROR("invalid input\n"); 183 183 return 0; 184 184 } 185 185 186 186 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 186 186 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 187 187 188 188 - if (dp_panel->video_test) 189 189 - bpp = dp_link_bit_depth_to_bpp( 188 188 + if (msm_dp_panel->video_test) 189 189 + bpp = msm_dp_link_bit_depth_to_bpp( 190 190 panel->link->test_video.test_bit_depth); 191 191 else 192 192 - bpp = dp_panel_get_supported_bpp(dp_panel, mode_edid_bpp, 192 192 + bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp, 193 193 mode_pclk_khz); 194 194 195 195 return bpp; 196 196 } 197 197 198 198 - int dp_panel_get_modes(struct dp_panel *dp_panel, 198 198 + int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, 199 199 struct drm_connector *connector) 200 200 { 201 201 - if (!dp_panel) { 201 201 + if (!msm_dp_panel) { 202 202 DRM_ERROR("invalid input\n"); 203 203 return -EINVAL; 204 204 } 205 205 206 206 - if (dp_panel->drm_edid) 206 206 + if (msm_dp_panel->drm_edid) 207 207 return drm_edid_connector_add_modes(connector); 208 208 209 209 return 0; 210 210 } 211 211 212 212 - static u8 dp_panel_get_edid_checksum(const struct edid *edid) 212 212 + static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) 213 213 { 214 214 edid += edid->extensions; 215 215 216 216 return edid->checksum; 217 217 } 218 218 219 219 - void dp_panel_handle_sink_request(struct dp_panel *dp_panel) 219 219 + void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) 220 220 { 221 221 - struct dp_panel_private *panel; 221 221 + struct msm_dp_panel_private *panel; 222 222 223 223 - if (!dp_panel) { 223 223 + if (!msm_dp_panel) { 224 224 DRM_ERROR("invalid input\n"); 225 225 return; 226 226 } 227 227 228 228 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 228 228 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 229 229 230 230 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { 231 231 /* FIXME: get rid of drm_edid_raw() */ 232 232 - const struct edid *edid = drm_edid_raw(dp_panel->drm_edid); 232 232 + const struct edid *edid = drm_edid_raw(msm_dp_panel->drm_edid); 233 233 u8 checksum; 234 234 235 235 if (edid) 236 236 - checksum = dp_panel_get_edid_checksum(edid); 236 236 + checksum = msm_dp_panel_get_edid_checksum(edid); 237 237 else 238 238 - checksum = dp_panel->connector->real_edid_checksum; 238 238 + checksum = msm_dp_panel->connector->real_edid_checksum; 239 239 240 240 - dp_link_send_edid_checksum(panel->link, checksum); 241 241 - dp_link_send_test_response(panel->link); 240 240 + msm_dp_link_send_edid_checksum(panel->link, checksum); 241 241 + msm_dp_link_send_test_response(panel->link); 242 242 } 243 243 } 244 244 245 245 - void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable) 245 245 + void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) 246 246 { 247 247 - struct dp_catalog *catalog; 248 248 - struct dp_panel_private *panel; 247 247 + struct msm_dp_catalog *catalog; 248 248 + struct msm_dp_panel_private *panel; 249 249 250 250 - if (!dp_panel) { 250 250 + if (!msm_dp_panel) { 251 251 DRM_ERROR("invalid input\n"); 252 252 return; 253 253 } 254 254 255 255 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 255 255 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 256 256 catalog = panel->catalog; 257 257 258 258 if (!panel->panel_on) { ··· 262 262 } 263 263 264 264 if (!enable) { 265 265 - dp_catalog_panel_tpg_disable(catalog); 265 265 + msm_dp_catalog_panel_tpg_disable(catalog); 266 266 return; 267 267 } 268 268 269 269 drm_dbg_dp(panel->drm_dev, "calling catalog tpg_enable\n"); 270 270 - dp_catalog_panel_tpg_enable(catalog, &panel->dp_panel.dp_mode.drm_mode); 270 270 + msm_dp_catalog_panel_tpg_enable(catalog, &panel->msm_dp_panel.msm_dp_mode.drm_mode); 271 271 } 272 272 273 273 - static int dp_panel_setup_vsc_sdp_yuv_420(struct dp_panel *dp_panel) 273 273 + static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) 274 274 { 275 275 - struct dp_catalog *catalog; 276 276 - struct dp_panel_private *panel; 277 277 - struct dp_display_mode *dp_mode; 275 275 + struct msm_dp_catalog *catalog; 276 276 + struct msm_dp_panel_private *panel; 277 277 + struct msm_dp_display_mode *msm_dp_mode; 278 278 struct drm_dp_vsc_sdp vsc_sdp_data; 279 279 struct dp_sdp vsc_sdp; 280 280 ssize_t len; 281 281 282 282 - if (!dp_panel) { 282 282 + if (!msm_dp_panel) { 283 283 DRM_ERROR("invalid input\n"); 284 284 return -EINVAL; 285 285 } 286 286 287 287 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 287 287 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 288 288 catalog = panel->catalog; 289 289 - dp_mode = &dp_panel->dp_mode; 289 289 + msm_dp_mode = &msm_dp_panel->msm_dp_mode; 290 290 291 291 memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); 292 292 ··· 300 300 vsc_sdp_data.colorimetry = DP_COLORIMETRY_DEFAULT; 301 301 302 302 /* VSC SDP Payload for DB17 */ 303 303 - vsc_sdp_data.bpc = dp_mode->bpp / 3; 303 303 + vsc_sdp_data.bpc = msm_dp_mode->bpp / 3; 304 304 vsc_sdp_data.dynamic_range = DP_DYNAMIC_RANGE_CTA; 305 305 306 306 /* VSC SDP Payload for DB18 */ ··· 312 312 return len; 313 313 } 314 314 315 315 - dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); 315 315 + msm_dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); 316 316 317 317 return 0; 318 318 } 319 319 320 320 - void dp_panel_dump_regs(struct dp_panel *dp_panel) 320 320 + void msm_dp_panel_dump_regs(struct msm_dp_panel *msm_dp_panel) 321 321 { 322 322 - struct dp_catalog *catalog; 323 323 - struct dp_panel_private *panel; 322 322 + struct msm_dp_catalog *catalog; 323 323 + struct msm_dp_panel_private *panel; 324 324 325 325 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 325 325 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 326 326 catalog = panel->catalog; 327 327 328 328 - dp_catalog_dump_regs(catalog); 328 328 + msm_dp_catalog_dump_regs(catalog); 329 329 } 330 330 331 331 - int dp_panel_timing_cfg(struct dp_panel *dp_panel) 331 331 + int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel) 332 332 { 333 333 u32 data, total_ver, total_hor; 334 334 - struct dp_catalog *catalog; 335 335 - struct dp_panel_private *panel; 334 334 + struct msm_dp_catalog *catalog; 335 335 + struct msm_dp_panel_private *panel; 336 336 struct drm_display_mode *drm_mode; 337 337 u32 width_blanking; 338 338 u32 sync_start; 339 339 - u32 dp_active; 339 339 + u32 msm_dp_active; 340 340 u32 total; 341 341 342 342 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 342 342 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 343 343 catalog = panel->catalog; 344 344 - drm_mode = &panel->dp_panel.dp_mode.drm_mode; 344 344 + drm_mode = &panel->msm_dp_panel.msm_dp_mode.drm_mode; 345 345 346 346 drm_dbg_dp(panel->drm_dev, "width=%d hporch= %d %d %d\n", 347 347 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, ··· 371 371 372 372 data = drm_mode->vsync_end - drm_mode->vsync_start; 373 373 data <<= 16; 374 374 - data |= (panel->dp_panel.dp_mode.v_active_low << 31); 374 374 + data |= (panel->msm_dp_panel.msm_dp_mode.v_active_low << 31); 375 375 data |= drm_mode->hsync_end - drm_mode->hsync_start; 376 376 - data |= (panel->dp_panel.dp_mode.h_active_low << 15); 376 376 + data |= (panel->msm_dp_panel.msm_dp_mode.h_active_low << 15); 377 377 378 378 width_blanking = data; 379 379 ··· 381 381 data <<= 16; 382 382 data |= drm_mode->hdisplay; 383 383 384 384 - dp_active = data; 384 384 + msm_dp_active = data; 385 385 386 386 - dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blanking, dp_active); 386 386 + msm_dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blanking, msm_dp_active); 387 387 388 388 - if (dp_panel->dp_mode.out_fmt_is_yuv_420) 389 389 - dp_panel_setup_vsc_sdp_yuv_420(dp_panel); 388 388 + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) 389 389 + msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); 390 390 391 391 panel->panel_on = true; 392 392 393 393 return 0; 394 394 } 395 395 396 396 - int dp_panel_init_panel_info(struct dp_panel *dp_panel) 396 396 + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) 397 397 { 398 398 struct drm_display_mode *drm_mode; 399 399 - struct dp_panel_private *panel; 399 399 + struct msm_dp_panel_private *panel; 400 400 401 401 - drm_mode = &dp_panel->dp_mode.drm_mode; 401 401 + drm_mode = &msm_dp_panel->msm_dp_mode.drm_mode; 402 402 403 403 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 403 403 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 404 404 405 405 /* 406 406 * print resolution info as this is a result ··· 421 421 drm_mode->vsync_end - drm_mode->vsync_start); 422 422 drm_dbg_dp(panel->drm_dev, "pixel clock (KHz)=(%d)\n", 423 423 drm_mode->clock); 424 424 - drm_dbg_dp(panel->drm_dev, "bpp = %d\n", dp_panel->dp_mode.bpp); 424 424 + drm_dbg_dp(panel->drm_dev, "bpp = %d\n", msm_dp_panel->msm_dp_mode.bpp); 425 425 426 426 - dp_panel->dp_mode.bpp = dp_panel_get_mode_bpp(dp_panel, dp_panel->dp_mode.bpp, 427 427 - dp_panel->dp_mode.drm_mode.clock); 426 426 + msm_dp_panel->msm_dp_mode.bpp = msm_dp_panel_get_mode_bpp(msm_dp_panel, msm_dp_panel->msm_dp_mode.bpp, 427 427 + msm_dp_panel->msm_dp_mode.drm_mode.clock); 428 428 429 429 drm_dbg_dp(panel->drm_dev, "updated bpp = %d\n", 430 430 - dp_panel->dp_mode.bpp); 430 430 + msm_dp_panel->msm_dp_mode.bpp); 431 431 432 432 return 0; 433 433 } 434 434 435 435 - static u32 dp_panel_link_frequencies(struct device_node *of_node) 435 435 + static u32 msm_dp_panel_link_frequencies(struct device_node *of_node) 436 436 { 437 437 struct device_node *endpoint; 438 438 u64 frequency = 0; ··· 456 456 return frequency; 457 457 } 458 458 459 459 - static int dp_panel_parse_dt(struct dp_panel *dp_panel) 459 459 + static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) 460 460 { 461 461 - struct dp_panel_private *panel; 461 461 + struct msm_dp_panel_private *panel; 462 462 struct device_node *of_node; 463 463 int cnt; 464 464 465 465 - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); 465 465 + panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); 466 466 of_node = panel->dev->of_node; 467 467 468 468 /* 469 469 - * data-lanes is the property of dp_out endpoint 469 469 + * data-lanes is the property of msm_dp_out endpoint 470 470 */ 471 471 cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES); 472 472 if (cnt < 0) { ··· 475 475 } 476 476 477 477 if (cnt > 0) 478 478 - dp_panel->max_dp_lanes = cnt; 478 478 + msm_dp_panel->max_dp_lanes = cnt; 479 479 else 480 480 - dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ 480 480 + msm_dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ 481 481 482 482 - dp_panel->max_dp_link_rate = dp_panel_link_frequencies(of_node); 483 483 - if (!dp_panel->max_dp_link_rate) 484 484 - dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2; 482 482 + msm_dp_panel->max_dp_link_rate = msm_dp_panel_link_frequencies(of_node); 483 483 + if (!msm_dp_panel->max_dp_link_rate) 484 484 + msm_dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2; 485 485 486 486 return 0; 487 487 } 488 488 489 489 - struct dp_panel *dp_panel_get(struct dp_panel_in *in) 489 489 + struct msm_dp_panel *msm_dp_panel_get(struct msm_dp_panel_in *in) 490 490 { 491 491 - struct dp_panel_private *panel; 492 492 - struct dp_panel *dp_panel; 491 491 + struct msm_dp_panel_private *panel; 492 492 + struct msm_dp_panel *msm_dp_panel; 493 493 int ret; 494 494 495 495 if (!in->dev || !in->catalog || !in->aux || !in->link) { ··· 506 506 panel->catalog = in->catalog; 507 507 panel->link = in->link; 508 508 509 509 - dp_panel = &panel->dp_panel; 510 510 - dp_panel->max_bw_code = DP_LINK_BW_8_1; 509 509 + msm_dp_panel = &panel->msm_dp_panel; 510 510 + msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; 511 511 512 512 - ret = dp_panel_parse_dt(dp_panel); 512 512 + ret = msm_dp_panel_parse_dt(msm_dp_panel); 513 513 if (ret) 514 514 return ERR_PTR(ret); 515 515 516 516 - return dp_panel; 516 516 + return msm_dp_panel; 517 517 } 518 518 519 519 - void dp_panel_put(struct dp_panel *dp_panel) 519 519 + void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) 520 520 { 521 521 - if (!dp_panel) 521 521 + if (!msm_dp_panel) 522 522 return; 523 523 524 524 - drm_edid_free(dp_panel->drm_edid); 524 524 + drm_edid_free(msm_dp_panel->drm_edid); 525 525 }

+21 -21

drivers/gpu/drm/msm/dp/dp_panel.h

reviewed

··· 13 13 14 14 struct edid; 15 15 16 16 - struct dp_display_mode { 16 16 + struct msm_dp_display_mode { 17 17 struct drm_display_mode drm_mode; 18 18 u32 bpp; 19 19 u32 h_active_low; ··· 21 21 bool out_fmt_is_yuv_420; 22 22 }; 23 23 24 24 - struct dp_panel_in { 24 24 + struct msm_dp_panel_in { 25 25 struct device *dev; 26 26 struct drm_dp_aux *aux; 27 27 - struct dp_link *link; 28 28 - struct dp_catalog *catalog; 27 27 + struct msm_dp_link *link; 28 28 + struct msm_dp_catalog *catalog; 29 29 }; 30 30 31 31 - struct dp_panel_psr { 31 31 + struct msm_dp_panel_psr { 32 32 u8 version; 33 33 u8 capabilities; 34 34 }; 35 35 36 36 - struct dp_panel { 36 36 + struct msm_dp_panel { 37 37 /* dpcd raw data */ 38 38 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 39 39 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 40 40 41 41 - struct dp_link_info link_info; 41 41 + struct msm_dp_link_info link_info; 42 42 const struct drm_edid *drm_edid; 43 43 struct drm_connector *connector; 44 44 - struct dp_display_mode dp_mode; 45 45 - struct dp_panel_psr psr_cap; 44 44 + struct msm_dp_display_mode msm_dp_mode; 45 45 + struct msm_dp_panel_psr psr_cap; 46 46 bool video_test; 47 47 bool vsc_sdp_supported; 48 48 ··· 52 52 u32 max_bw_code; 53 53 }; 54 54 55 55 - int dp_panel_init_panel_info(struct dp_panel *dp_panel); 56 56 - int dp_panel_deinit(struct dp_panel *dp_panel); 57 57 - int dp_panel_timing_cfg(struct dp_panel *dp_panel); 58 58 - void dp_panel_dump_regs(struct dp_panel *dp_panel); 59 59 - int dp_panel_read_sink_caps(struct dp_panel *dp_panel, 55 55 + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); 56 56 + int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); 57 57 + int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel); 58 58 + void msm_dp_panel_dump_regs(struct msm_dp_panel *msm_dp_panel); 59 59 + int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, 60 60 struct drm_connector *connector); 61 61 - u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel, u32 mode_max_bpp, 61 61 + u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_max_bpp, 62 62 u32 mode_pclk_khz); 63 63 - int dp_panel_get_modes(struct dp_panel *dp_panel, 63 63 + int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, 64 64 struct drm_connector *connector); 65 65 - void dp_panel_handle_sink_request(struct dp_panel *dp_panel); 66 66 - void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable); 65 65 + void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); 66 66 + void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable); 67 67 68 68 /** 69 69 * is_link_rate_valid() - validates the link rate ··· 80 80 } 81 81 82 82 /** 83 83 - * dp_link_is_lane_count_valid() - validates the lane count 83 83 + * msm_dp_link_is_lane_count_valid() - validates the lane count 84 84 * @lane_count: lane count requested by the sink 85 85 * 86 86 * Returns true if the requested lane count is supported. ··· 92 92 lane_count == 4); 93 93 } 94 94 95 95 - struct dp_panel *dp_panel_get(struct dp_panel_in *in); 96 96 - void dp_panel_put(struct dp_panel *dp_panel); 95 95 + struct msm_dp_panel *msm_dp_panel_get(struct msm_dp_panel_in *in); 96 96 + void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel); 97 97 #endif /* _DP_PANEL_H_ */

+10 -10

drivers/gpu/drm/msm/dp/dp_utils.c

reviewed

··· 9 9 10 10 #define DP_SDP_HEADER_SIZE 8 11 11 12 12 - u8 dp_utils_get_g0_value(u8 data) 12 12 + u8 msm_dp_utils_get_g0_value(u8 data) 13 13 { 14 14 u8 c[4]; 15 15 u8 g[4]; ··· 30 30 return ret_data; 31 31 } 32 32 33 33 - u8 dp_utils_get_g1_value(u8 data) 33 33 + u8 msm_dp_utils_get_g1_value(u8 data) 34 34 { 35 35 u8 c[4]; 36 36 u8 g[4]; ··· 51 51 return ret_data; 52 52 } 53 53 54 54 - u8 dp_utils_calculate_parity(u32 data) 54 54 + u8 msm_dp_utils_calculate_parity(u32 data) 55 55 { 56 56 u8 x0 = 0; 57 57 u8 x1 = 0; ··· 65 65 iData = (data >> i * 4) & 0xF; 66 66 67 67 ci = iData ^ x1; 68 68 - x1 = x0 ^ dp_utils_get_g1_value(ci); 69 69 - x0 = dp_utils_get_g0_value(ci); 68 68 + x1 = x0 ^ msm_dp_utils_get_g1_value(ci); 69 69 + x0 = msm_dp_utils_get_g0_value(ci); 70 70 } 71 71 72 72 parity_byte = x1 | (x0 << 4); ··· 74 74 return parity_byte; 75 75 } 76 76 77 77 - ssize_t dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff) 77 77 + ssize_t msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff) 78 78 { 79 79 size_t length; 80 80 ··· 83 83 return -ENOSPC; 84 84 85 85 header_buff[0] = FIELD_PREP(HEADER_0_MASK, sdp_header->HB0) | 86 86 - FIELD_PREP(PARITY_0_MASK, dp_utils_calculate_parity(sdp_header->HB0)) | 86 86 + FIELD_PREP(PARITY_0_MASK, msm_dp_utils_calculate_parity(sdp_header->HB0)) | 87 87 FIELD_PREP(HEADER_1_MASK, sdp_header->HB1) | 88 88 - FIELD_PREP(PARITY_1_MASK, dp_utils_calculate_parity(sdp_header->HB1)); 88 88 + FIELD_PREP(PARITY_1_MASK, msm_dp_utils_calculate_parity(sdp_header->HB1)); 89 89 90 90 header_buff[1] = FIELD_PREP(HEADER_2_MASK, sdp_header->HB2) | 91 91 - FIELD_PREP(PARITY_2_MASK, dp_utils_calculate_parity(sdp_header->HB2)) | 91 91 + FIELD_PREP(PARITY_2_MASK, msm_dp_utils_calculate_parity(sdp_header->HB2)) | 92 92 FIELD_PREP(HEADER_3_MASK, sdp_header->HB3) | 93 93 - FIELD_PREP(PARITY_3_MASK, dp_utils_calculate_parity(sdp_header->HB3)); 93 93 + FIELD_PREP(PARITY_3_MASK, msm_dp_utils_calculate_parity(sdp_header->HB3)); 94 94 95 95 return length; 96 96 }

+4 -4

drivers/gpu/drm/msm/dp/dp_utils.h

reviewed

··· 28 28 #define HEADER_3_MASK GENMASK(23, 16) 29 29 #define PARITY_3_MASK GENMASK(31, 24) 30 30 31 31 - u8 dp_utils_get_g0_value(u8 data); 32 32 - u8 dp_utils_get_g1_value(u8 data); 33 33 - u8 dp_utils_calculate_parity(u32 data); 34 34 - ssize_t dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff); 31 31 + u8 msm_dp_utils_get_g0_value(u8 data); 32 32 + u8 msm_dp_utils_get_g1_value(u8 data); 33 33 + u8 msm_dp_utils_calculate_parity(u32 data); 34 34 + ssize_t msm_dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff); 35 35 36 36 #endif /* _DP_UTILS_H_ */

-18

drivers/gpu/drm/msm/msm_drv.h

reviewed

··· 52 52 struct msm_disp_state; 53 53 54 54 #define MAX_CRTCS 8 55 55 - #define MAX_BRIDGES 8 56 55 57 56 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 58 57 ··· 70 71 }; 71 72 72 73 #define MSM_GPU_MAX_RINGS 4 73 73 - #define MAX_H_TILES_PER_DISPLAY 2 74 74 - 75 75 - /** 76 76 - * struct msm_display_topology - defines a display topology pipeline 77 77 - * @num_lm: number of layer mixers used 78 78 - * @num_intf: number of interfaces the panel is mounted on 79 79 - * @num_dspp: number of dspp blocks used 80 80 - * @num_dsc: number of Display Stream Compression (DSC) blocks used 81 81 - * @needs_cdm: indicates whether cdm block is needed for this display topology 82 82 - */ 83 83 - struct msm_display_topology { 84 84 - u32 num_lm; 85 85 - u32 num_intf; 86 86 - u32 num_dspp; 87 87 - u32 num_dsc; 88 88 - bool needs_cdm; 89 89 - }; 90 74 91 75 /* Commit/Event thread specific structure */ 92 76 struct msm_drm_thread {

+15 -20

drivers/gpu/drm/msm/msm_mdss.c

reviewed

··· 19 19 #include "msm_mdss.h" 20 20 #include "msm_kms.h" 21 21 22 22 - #define HW_REV 0x0 23 23 - #define HW_INTR_STATUS 0x0010 24 24 - 25 25 - #define UBWC_DEC_HW_VERSION 0x58 26 26 - #define UBWC_STATIC 0x144 27 27 - #define UBWC_CTRL_2 0x150 28 28 - #define UBWC_PREDICTION_MODE 0x154 22 22 + #include <generated/mdss.xml.h> 29 23 30 24 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 31 25 ··· 77 83 78 84 chained_irq_enter(chip, desc); 79 85 80 80 - interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 86 86 + interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); 81 87 82 88 while (interrupts) { 83 89 irq_hw_number_t hwirq = fls(interrupts) - 1; ··· 167 173 { 168 174 const struct msm_mdss_data *data = msm_mdss->mdss_data; 169 175 170 170 - writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); 176 176 + writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 171 177 } 172 178 173 179 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) ··· 183 189 if (data->ubwc_enc_version == UBWC_1_0) 184 190 value |= BIT(8); 185 191 186 186 - writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 192 192 + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 187 193 } 188 194 189 195 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) ··· 194 200 (data->highest_bank_bit & 0x7) << 4 | 195 201 (data->macrotile_mode & 0x1) << 12; 196 202 197 197 - writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 203 203 + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 198 204 199 205 if (data->ubwc_enc_version == UBWC_3_0) { 200 200 - writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 201 201 - writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 206 206 + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 207 207 + writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 202 208 } else { 203 209 if (data->ubwc_dec_version == UBWC_4_3) 204 204 - writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); 210 210 + writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 205 211 else 206 206 - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 207 207 - writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 212 212 + writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 213 213 + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 208 214 } 209 215 } 210 216 211 211 - #define MDSS_HW_MAJ_MIN GENMASK(31, 16) 217 217 + #define MDSS_HW_MAJ_MIN \ 218 218 + (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) 212 219 213 220 #define MDSS_HW_MSM8996 0x1007 214 221 #define MDSS_HW_MSM8937 0x100e ··· 230 235 if (!data) 231 236 return NULL; 232 237 233 233 - hw_rev = readl_relaxed(mdss->mmio + HW_REV); 238 238 + hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION); 234 239 hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); 235 240 236 241 if (hw_rev == MDSS_HW_MSM8996 || ··· 329 334 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 330 335 msm_mdss->mdss_data->ubwc_dec_version); 331 336 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 332 332 - readl_relaxed(msm_mdss->mmio + HW_REV)); 337 337 + readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION)); 333 338 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 334 334 - readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 339 339 + readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION)); 335 340 break; 336 341 } 337 342

-16

drivers/gpu/drm/msm/registers/display/mdp5.xml

reviewed

··· 9 9 <domain name="VBIF" width="32"> 10 10 </domain> 11 11 12 12 - <domain name="MDSS" width="32"> 13 13 - <reg32 offset="0x00000" name="HW_VERSION"> 14 14 - <bitfield name="STEP" low="0" high="15" type="uint"/> 15 15 - <bitfield name="MINOR" low="16" high="27" type="uint"/> 16 16 - <bitfield name="MAJOR" low="28" high="31" type="uint"/> 17 17 - </reg32> 18 18 - 19 19 - <reg32 offset="0x00010" name="HW_INTR_STATUS"> 20 20 - <bitfield name="INTR_MDP" pos="0" type="boolean"/> 21 21 - <bitfield name="INTR_DSI0" pos="4" type="boolean"/> 22 22 - <bitfield name="INTR_DSI1" pos="5" type="boolean"/> 23 23 - <bitfield name="INTR_HDMI" pos="8" type="boolean"/> 24 24 - <bitfield name="INTR_EDP" pos="12" type="boolean"/> 25 25 - </reg32> 26 26 - </domain> 27 27 - 28 12 <domain name="MDP5" width="32"> 29 13 30 14 <enum name="mdp5_intf_type">

+29

drivers/gpu/drm/msm/registers/display/mdss.xml

reviewed

··· 1 1 + <?xml version="1.0" encoding="UTF-8"?> 2 2 + <database xmlns="http://nouveau.freedesktop.org/" 3 3 + xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4 4 + xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5 5 + <import file="freedreno_copyright.xml"/> 6 6 + 7 7 + <domain name="MDSS" width="32"> 8 8 + <reg32 offset="0x00000" name="HW_VERSION"> 9 9 + <bitfield name="STEP" low="0" high="15" type="uint"/> 10 10 + <bitfield name="MINOR" low="16" high="27" type="uint"/> 11 11 + <bitfield name="MAJOR" low="28" high="31" type="uint"/> 12 12 + </reg32> 13 13 + 14 14 + <reg32 offset="0x00010" name="HW_INTR_STATUS"> 15 15 + <bitfield name="INTR_MDP" pos="0" type="boolean"/> 16 16 + <bitfield name="INTR_DSI0" pos="4" type="boolean"/> 17 17 + <bitfield name="INTR_DSI1" pos="5" type="boolean"/> 18 18 + <bitfield name="INTR_HDMI" pos="8" type="boolean"/> 19 19 + <bitfield name="INTR_EDP" pos="12" type="boolean"/> 20 20 + </reg32> 21 21 + 22 22 + <reg32 offset="0x00058" name="UBWC_DEC_HW_VERSION"/> 23 23 + 24 24 + <reg32 offset="0x00144" name="UBWC_STATIC"/> 25 25 + <reg32 offset="0x00150" name="UBWC_CTRL_2"/> 26 26 + <reg32 offset="0x00154" name="UBWC_PREDICTION_MODE"/> 27 27 + </domain> 28 28 + 29 29 + </database>