tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux

Pull i2c embedded fixes from Wolfram Sang:
"Two patches are usual stuff.

The bigger patch is needed to correct a wrong decision made in this
merge window. We hoped to get the PIOQUEUE mode in the mxs driver
working with DMA, but it turned out to be too broken (leading to data
loss), so we now think it is best to remove it entirely and work only
with DMA now. The patch should be in 3.7. IMO, so users never get
the chance to use both modes in parallel."

* 'i2c-embedded/for-current' of git://git.pengutronix.de/git/wsa/linux:
i2c: tegra: set irq name as device name
i2c-nomadik: Fixup clock handling
i2c: mxs: remove broken PIOQUEUE support

Linus Torvalds 209c510e 53f9313f

+22 -175
+14 -172
drivers/i2c/busses/i2c-mxs.c
··· 1 1 /* 2 2 * Freescale MXS I2C bus driver 3 3 * 4 - * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. 4 + * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. 5 5 * 6 6 * based on a (non-working) driver which was: 7 7 * ··· 34 34 #include <linux/fsl/mxs-dma.h> 35 35 36 36 #define DRIVER_NAME "mxs-i2c" 37 - 38 - static bool use_pioqueue; 39 - module_param(use_pioqueue, bool, 0); 40 - MODULE_PARM_DESC(use_pioqueue, "Use PIOQUEUE mode for transfer instead of DMA"); 41 37 42 38 #define MXS_I2C_CTRL0 (0x00) 43 39 #define MXS_I2C_CTRL0_SET (0x04) ··· 70 74 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ 71 75 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ 72 76 MXS_I2C_CTRL1_SLAVE_IRQ) 73 - 74 - #define MXS_I2C_QUEUECTRL (0x60) 75 - #define MXS_I2C_QUEUECTRL_SET (0x64) 76 - #define MXS_I2C_QUEUECTRL_CLR (0x68) 77 - 78 - #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20 79 - #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04 80 - 81 - #define MXS_I2C_QUEUESTAT (0x70) 82 - #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000 83 - #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F 84 - 85 - #define MXS_I2C_QUEUECMD (0x80) 86 - 87 - #define MXS_I2C_QUEUEDATA (0x90) 88 - 89 - #define MXS_I2C_DATA (0xa0) 90 77 91 78 92 79 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ ··· 132 153 const struct mxs_i2c_speed_config *speed; 133 154 134 155 /* DMA support components */ 135 - bool dma_mode; 136 156 int dma_channel; 137 157 struct dma_chan *dmach; 138 158 struct mxs_dma_data dma_data; ··· 150 172 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); 151 173 152 174 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 153 - if (i2c->dma_mode) 154 - writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 155 - i2c->regs + MXS_I2C_QUEUECTRL_CLR); 156 - else 157 - writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE, 158 - i2c->regs + MXS_I2C_QUEUECTRL_SET); 159 - } 160 - 161 - static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len, 162 - int flags) 163 - { 164 - u32 data; 165 - 166 - writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD); 167 - 168 - data = (addr << 1) | I2C_SMBUS_READ; 169 - writel(data, i2c->regs + MXS_I2C_DATA); 170 - 171 - data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags; 172 - writel(data, i2c->regs + MXS_I2C_QUEUECMD); 173 - } 174 - 175 - static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c, 176 - u8 addr, u8 *buf, int len, int flags) 177 - { 178 - u32 data; 179 - int i, shifts_left; 180 - 181 - data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags; 182 - writel(data, i2c->regs + MXS_I2C_QUEUECMD); 183 - 184 - /* 185 - * We have to copy the slave address (u8) and buffer (arbitrary number 186 - * of u8) into the data register (u32). To achieve that, the u8 are put 187 - * into the MSBs of 'data' which is then shifted for the next u8. When 188 - * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32 189 - * looks like this: 190 - * 191 - * 3 2 1 0 192 - * 10987654|32109876|54321098|76543210 193 - * --------+--------+--------+-------- 194 - * buffer+2|buffer+1|buffer+0|slave_addr 195 - */ 196 - 197 - data = ((addr << 1) | I2C_SMBUS_WRITE) << 24; 198 - 199 - for (i = 0; i < len; i++) { 200 - data >>= 8; 201 - data |= buf[i] << 24; 202 - if ((i & 3) == 2) 203 - writel(data, i2c->regs + MXS_I2C_DATA); 204 - } 205 - 206 - /* Write out the remaining bytes if any */ 207 - shifts_left = 24 - (i & 3) * 8; 208 - if (shifts_left) 209 - writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA); 210 - } 211 - 212 - /* 213 - * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the 214 - * rd_threshold to 1). Couldn't get this to work, though. 215 - */ 216 - static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c) 217 - { 218 - unsigned long timeout = jiffies + msecs_to_jiffies(1000); 219 - 220 - while (readl(i2c->regs + MXS_I2C_QUEUESTAT) 221 - & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) { 222 - if (time_after(jiffies, timeout)) 223 - return -ETIMEDOUT; 224 - cond_resched(); 225 - } 226 - 227 - return 0; 228 - } 229 - 230 - static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len) 231 - { 232 - u32 uninitialized_var(data); 233 - int i; 234 - 235 - for (i = 0; i < len; i++) { 236 - if ((i & 3) == 0) { 237 - if (mxs_i2c_wait_for_data(i2c)) 238 - return -ETIMEDOUT; 239 - data = readl(i2c->regs + MXS_I2C_QUEUEDATA); 240 - } 241 - buf[i] = data & 0xff; 242 - data >>= 8; 243 - } 244 - 245 - return 0; 246 175 } 247 176 248 177 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) ··· 317 432 init_completion(&i2c->cmd_complete); 318 433 i2c->cmd_err = 0; 319 434 320 - if (i2c->dma_mode) { 321 - ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); 322 - if (ret) 323 - return ret; 324 - } else { 325 - if (msg->flags & I2C_M_RD) { 326 - mxs_i2c_pioq_setup_read(i2c, msg->addr, 327 - msg->len, flags); 328 - } else { 329 - mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, 330 - msg->len, flags); 331 - } 332 - 333 - writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, 334 - i2c->regs + MXS_I2C_QUEUECTRL_SET); 335 - } 435 + ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); 436 + if (ret) 437 + return ret; 336 438 337 439 ret = wait_for_completion_timeout(&i2c->cmd_complete, 338 440 msecs_to_jiffies(1000)); 339 441 if (ret == 0) 340 442 goto timeout; 341 443 342 - if (!i2c->dma_mode && !i2c->cmd_err && (msg->flags & I2C_M_RD)) { 343 - ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len); 344 - if (ret) 345 - goto timeout; 346 - } 347 - 348 444 if (i2c->cmd_err == -ENXIO) 349 445 mxs_i2c_reset(i2c); 350 - else 351 - writel(MXS_I2C_QUEUECTRL_QUEUE_RUN, 352 - i2c->regs + MXS_I2C_QUEUECTRL_CLR); 353 446 354 447 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err); 355 448 ··· 335 472 336 473 timeout: 337 474 dev_dbg(i2c->dev, "Timeout!\n"); 338 - if (i2c->dma_mode) 339 - mxs_i2c_dma_finish(i2c); 475 + mxs_i2c_dma_finish(i2c); 340 476 mxs_i2c_reset(i2c); 341 477 return -ETIMEDOUT; 342 478 } ··· 364 502 { 365 503 struct mxs_i2c_dev *i2c = dev_id; 366 504 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; 367 - bool is_last_cmd; 368 505 369 506 if (!stat) 370 507 return IRQ_NONE; ··· 375 514 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) 376 515 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ 377 516 i2c->cmd_err = -EIO; 378 - 379 - if (!i2c->dma_mode) { 380 - is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) & 381 - MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0; 382 - 383 - if (is_last_cmd || i2c->cmd_err) 384 - complete(&i2c->cmd_complete); 385 - } 386 517 387 518 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); 388 519 ··· 409 556 int ret; 410 557 411 558 /* 412 - * The MXS I2C DMA mode is prefered and enabled by default. 413 - * The PIO mode is still supported, but should be used only 414 - * for debuging purposes etc. 415 - */ 416 - i2c->dma_mode = !use_pioqueue; 417 - if (!i2c->dma_mode) 418 - dev_info(dev, "Using PIOQUEUE mode for I2C transfers!\n"); 419 - 420 - /* 421 559 * TODO: This is a temporary solution and should be changed 422 560 * to use generic DMA binding later when the helpers get in. 423 561 */ 424 562 ret = of_property_read_u32(node, "fsl,i2c-dma-channel", 425 563 &i2c->dma_channel); 426 564 if (ret) { 427 - dev_warn(dev, "Failed to get DMA channel, using PIOQUEUE!\n"); 428 - i2c->dma_mode = 0; 565 + dev_err(dev, "Failed to get DMA channel!\n"); 566 + return -ENODEV; 429 567 } 430 568 431 569 ret = of_property_read_u32(node, "clock-frequency", &speed); ··· 478 634 } 479 635 480 636 /* Setup the DMA */ 481 - if (i2c->dma_mode) { 482 - dma_cap_zero(mask); 483 - dma_cap_set(DMA_SLAVE, mask); 484 - i2c->dma_data.chan_irq = dmairq; 485 - i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c); 486 - if (!i2c->dmach) { 487 - dev_err(dev, "Failed to request dma\n"); 488 - return -ENODEV; 489 - } 637 + dma_cap_zero(mask); 638 + dma_cap_set(DMA_SLAVE, mask); 639 + i2c->dma_data.chan_irq = dmairq; 640 + i2c->dmach = dma_request_channel(mask, mxs_i2c_dma_filter, i2c); 641 + if (!i2c->dmach) { 642 + dev_err(dev, "Failed to request dma\n"); 643 + return -ENODEV; 490 644 } 491 645 492 646 platform_set_drvdata(pdev, i2c);
+7 -2
drivers/i2c/busses/i2c-nomadik.c
··· 644 644 645 645 pm_runtime_get_sync(&dev->adev->dev); 646 646 647 - clk_enable(dev->clk); 647 + status = clk_prepare_enable(dev->clk); 648 + if (status) { 649 + dev_err(&dev->adev->dev, "can't prepare_enable clock\n"); 650 + goto out_clk; 651 + } 648 652 649 653 status = init_hw(dev); 650 654 if (status) ··· 675 671 } 676 672 677 673 out: 678 - clk_disable(dev->clk); 674 + clk_disable_unprepare(dev->clk); 675 + out_clk: 679 676 pm_runtime_put_sync(&dev->adev->dev); 680 677 681 678 dev->busy = false;
+1 -1
drivers/i2c/busses/i2c-tegra.c
··· 742 742 } 743 743 744 744 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 745 - tegra_i2c_isr, 0, pdev->name, i2c_dev); 745 + tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 746 746 if (ret) { 747 747 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 748 748 return ret;