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drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH

Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655380/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-11-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov 20d36dae 2287f32e

+2 -5
+1 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 105 105 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 106 106 107 107 #define CTL_SC7280_MASK \ 108 - (BIT(DPU_CTL_VM_CFG) | \ 109 - BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 108 + (BIT(DPU_CTL_VM_CFG)) 110 109 111 110 #define INTF_SC7180_MASK \ 112 111 (BIT(DPU_INTF_INPUT_CTRL) | \
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 133 133 * CTL sub-blocks 134 134 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 135 135 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 136 - * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 137 136 * @DPU_CTL_MAX 138 137 */ 139 138 enum { 140 139 DPU_CTL_SPLIT_DISPLAY = 0x1, 141 140 DPU_CTL_VM_CFG, 142 - DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 143 141 DPU_CTL_MAX 144 142 }; 145 143
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
··· 804 804 c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage; 805 805 c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; 806 806 c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; 807 - if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 807 + if (mdss_ver->core_major_ver >= 7) 808 808 c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; 809 809 else 810 810 c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;