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drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE

Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655379/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-10-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov 2287f32e ef31cf53

+2 -5
+1 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 105 105 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 106 106 107 107 #define CTL_SC7280_MASK \ 108 - (BIT(DPU_CTL_FETCH_ACTIVE) | \ 109 - BIT(DPU_CTL_VM_CFG) | \ 108 + (BIT(DPU_CTL_VM_CFG) | \ 110 109 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 111 110 112 111 #define INTF_SC7180_MASK \
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 132 132 /** 133 133 * CTL sub-blocks 134 134 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 135 - * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 136 135 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 137 136 * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 138 137 * @DPU_CTL_MAX 139 138 */ 140 139 enum { 141 140 DPU_CTL_SPLIT_DISPLAY = 0x1, 142 - DPU_CTL_FETCH_ACTIVE, 143 141 DPU_CTL_VM_CFG, 144 142 DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 145 143 DPU_CTL_MAX
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
··· 809 809 else 810 810 c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; 811 811 812 - if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) 812 + if (mdss_ver->core_major_ver >= 7) 813 813 c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes; 814 814 815 815 c->idx = cfg->id;