Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
RDMA/hns: Remove Receive Queue of CMDQ
The CRQ of CMDQ is unused, so remove code about it.
Link: https://lore.kernel.org/r/1621482876-35780-3-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
authored by
Lang Cheng
and committed by
Jason Gunthorpe
21090b5d
4511624a
+23
-71
+23
-70
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+23
-70
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
···
1209
1209
kfree(ring->desc);
1210
1210
ring->desc = NULL;
1211
1211
1212
-
dev_err_ratelimited(hr_dev->dev,
1213
-
"failed to map cmq desc addr.\n");
1214
1212
return -ENOMEM;
1215
1213
}
1216
1214
···
1226
1228
kfree(ring->desc);
1227
1229
}
1228
1230
1229
-
static int hns_roce_init_cmq_ring(struct hns_roce_dev *hr_dev, bool ring_type)
1231
+
static int init_csq(struct hns_roce_dev *hr_dev,
1232
+
struct hns_roce_v2_cmq_ring *csq)
1230
1233
{
1231
-
struct hns_roce_v2_priv *priv = hr_dev->priv;
1232
-
struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
1233
-
&priv->cmq.csq : &priv->cmq.crq;
1234
+
dma_addr_t dma;
1235
+
int ret;
1234
1236
1235
-
ring->flag = ring_type;
1236
-
ring->head = 0;
1237
+
csq->desc_num = CMD_CSQ_DESC_NUM;
1238
+
spin_lock_init(&csq->lock);
1239
+
csq->flag = TYPE_CSQ;
1240
+
csq->head = 0;
1237
1241
1238
-
return hns_roce_alloc_cmq_desc(hr_dev, ring);
1239
-
}
1242
+
ret = hns_roce_alloc_cmq_desc(hr_dev, csq);
1243
+
if (ret)
1244
+
return ret;
1240
1245
1241
-
static void hns_roce_cmq_init_regs(struct hns_roce_dev *hr_dev, bool ring_type)
1242
-
{
1243
-
struct hns_roce_v2_priv *priv = hr_dev->priv;
1244
-
struct hns_roce_v2_cmq_ring *ring = (ring_type == TYPE_CSQ) ?
1245
-
&priv->cmq.csq : &priv->cmq.crq;
1246
-
dma_addr_t dma = ring->desc_dma_addr;
1246
+
dma = csq->desc_dma_addr;
1247
+
roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, lower_32_bits(dma));
1248
+
roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG, upper_32_bits(dma));
1249
+
roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1250
+
(u32)csq->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1247
1251
1248
-
if (ring_type == TYPE_CSQ) {
1249
-
roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_L_REG, (u32)dma);
1250
-
roce_write(hr_dev, ROCEE_TX_CMQ_BASEADDR_H_REG,
1251
-
upper_32_bits(dma));
1252
-
roce_write(hr_dev, ROCEE_TX_CMQ_DEPTH_REG,
1253
-
(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1252
+
/* Make sure to write CI first and then PI */
1253
+
roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1254
+
roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1254
1255
1255
-
/* Make sure to write tail first and then head */
1256
-
roce_write(hr_dev, ROCEE_TX_CMQ_CI_REG, 0);
1257
-
roce_write(hr_dev, ROCEE_TX_CMQ_PI_REG, 0);
1258
-
} else {
1259
-
roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_L_REG, (u32)dma);
1260
-
roce_write(hr_dev, ROCEE_RX_CMQ_BASEADDR_H_REG,
1261
-
upper_32_bits(dma));
1262
-
roce_write(hr_dev, ROCEE_RX_CMQ_DEPTH_REG,
1263
-
(u32)ring->desc_num >> HNS_ROCE_CMQ_DESC_NUM_S);
1264
-
roce_write(hr_dev, ROCEE_RX_CMQ_HEAD_REG, 0);
1265
-
roce_write(hr_dev, ROCEE_RX_CMQ_TAIL_REG, 0);
1266
-
}
1256
+
return 0;
1267
1257
}
1268
1258
1269
1259
static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev)
···
1259
1273
struct hns_roce_v2_priv *priv = hr_dev->priv;
1260
1274
int ret;
1261
1275
1262
-
/* Setup the queue entries for command queue */
1263
-
priv->cmq.csq.desc_num = CMD_CSQ_DESC_NUM;
1264
-
priv->cmq.crq.desc_num = CMD_CRQ_DESC_NUM;
1265
-
1266
-
/* Setup the lock for command queue */
1267
-
spin_lock_init(&priv->cmq.csq.lock);
1268
-
spin_lock_init(&priv->cmq.crq.lock);
1269
-
1270
-
/* Setup Tx write back timeout */
1271
1276
priv->cmq.tx_timeout = HNS_ROCE_CMQ_TX_TIMEOUT;
1272
1277
1273
-
/* Init CSQ */
1274
-
ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CSQ);
1275
-
if (ret) {
1276
-
dev_err_ratelimited(hr_dev->dev,
1277
-
"failed to init CSQ, ret = %d.\n", ret);
1278
-
return ret;
1279
-
}
1280
-
1281
-
/* Init CRQ */
1282
-
ret = hns_roce_init_cmq_ring(hr_dev, TYPE_CRQ);
1283
-
if (ret) {
1284
-
dev_err_ratelimited(hr_dev->dev,
1285
-
"failed to init CRQ, ret = %d.\n", ret);
1286
-
goto err_crq;
1287
-
}
1288
-
1289
-
/* Init CSQ REG */
1290
-
hns_roce_cmq_init_regs(hr_dev, TYPE_CSQ);
1291
-
1292
-
/* Init CRQ REG */
1293
-
hns_roce_cmq_init_regs(hr_dev, TYPE_CRQ);
1294
-
1295
-
return 0;
1296
-
1297
-
err_crq:
1298
-
hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1278
+
ret = init_csq(hr_dev, &priv->cmq.csq);
1279
+
if (ret)
1280
+
dev_err(hr_dev->dev, "failed to init CSQ, ret = %d.\n", ret);
1299
1281
1300
1282
return ret;
1301
1283
}
···
1273
1319
struct hns_roce_v2_priv *priv = hr_dev->priv;
1274
1320
1275
1321
hns_roce_free_cmq_desc(hr_dev, &priv->cmq.csq);
1276
-
hns_roce_free_cmq_desc(hr_dev, &priv->cmq.crq);
1277
1322
}
1278
1323
1279
1324
static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,