phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsets

Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ
for the same version number. So in order to be able to differentiate
between them, add these ones with DP prefix.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-3-4fcba75a6fa9@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Abel Vesa and committed by

Vinod Koul 6 months ago 212cdedc 2d472a67

+52

1 changed file

expand all

drivers

phy

qualcomm

phy-qcom-qmp-qserdes-dp-com-v8.h

+52

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-dp-com-v8.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (C) 2025 Linaro Ltd. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_DP_COM_V8_H_ 7 + #define QCOM_PHY_QMP_QSERDES_DP_COM_V8_H_ 8 + 9 + /* Only for DP QMP V8 PHY - QSERDES COM registers */ 10 + #define DP_QSERDES_V8_COM_HSCLK_SEL_1 0x03c 11 + #define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 12 + #define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c 13 + #define DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 14 + #define DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 15 + #define DP_QSERDES_V8_COM_CP_CTRL_MODE0 0x070 16 + #define DP_QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 17 + #define DP_QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 18 + #define DP_QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c 19 + #define DP_QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 20 + #define DP_QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 21 + #define DP_QSERDES_V8_COM_DEC_START_MODE0 0x088 22 + #define DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 23 + #define DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 24 + #define DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 25 + #define DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 26 + #define DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 27 + #define DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 28 + #define DP_QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac 29 + #define DP_QSERDES_V8_COM_BG_TIMER 0x0bc 30 + #define DP_QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 31 + #define DP_QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 32 + #define DP_QSERDES_V8_COM_SSC_PER1 0x0cc 33 + #define DP_QSERDES_V8_COM_SSC_PER2 0x0d0 34 + #define DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc 35 + #define DP_QSERDES_V8_COM_CLK_ENABLE1 0x0e0 36 + #define DP_QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 37 + #define DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 38 + #define DP_QSERDES_V8_COM_PLL_IVCO 0x0f4 39 + #define DP_QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 40 + #define DP_QSERDES_V8_COM_RESETSM_CNTRL 0x118 41 + #define DP_QSERDES_V8_COM_LOCK_CMP_EN 0x120 42 + #define DP_QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c 43 + #define DP_QSERDES_V8_COM_VCO_TUNE_MAP 0x140 44 + #define DP_QSERDES_V8_COM_CLK_SELECT 0x164 45 + #define DP_QSERDES_V8_COM_CORE_CLK_EN 0x170 46 + #define DP_QSERDES_V8_COM_CMN_CONFIG_1 0x174 47 + #define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL 0x180 48 + #define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 49 + #define DP_QSERDES_V8_COM_CMN_STATUS 0x314 50 + #define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c 51 + 52 + #endif

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