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drm/amdgpu: add helpers to access cross-die registers smn addr for soc v1_0

Encode die_id/socket_id for upper 32bits of soc v1_0 registers SMN address.

v2: fix logical error caught by clang

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Le Ma and committed by
Alex Deucher
21677982 0dd72af5

+33
+32
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
··· 72 72 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 73 73 } 74 74 75 + /* Fixed pattern for upper 32bits smn addressing. 76 + * bit[47:40]: Socket ID 77 + * bit[39:34]: Die ID 78 + * bit[32]: local or remote die in same socket 79 + * The ext_id is comprised of socket_id and die_id. 80 + * ext_id = (socket_id << 6) | (die_id) 81 + */ 82 + u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 83 + { 84 + u64 ext_offset; 85 + int socket_id, die_id; 86 + 87 + /* local die routing for MID0 on local socket */ 88 + if (ext_id == 0) 89 + return 0; 90 + 91 + die_id = ext_id & 0x3; 92 + socket_id = (ext_id >> 6) & 0xff; 93 + 94 + /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 95 + if (socket_id == 0) 96 + ext_offset = ((u64)die_id << 34) | (1ULL << 32); 97 + else if (socket_id != 0 && die_id != 0) 98 + ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 99 + (3ULL << 32); 100 + else 101 + ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 102 + 103 + return ext_offset; 104 + } 105 + 75 106 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 76 107 { 77 108 return adev->nbio.funcs->get_memsize(adev); ··· 242 211 .need_full_reset = &soc_v1_0_need_full_reset, 243 212 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 244 213 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 214 + .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 245 215 .reset = soc_v1_0_asic_reset, 246 216 }; 247 217
+1
drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
··· 32 32 int soc_v1_0_init_soc_config(struct amdgpu_device *adev); 33 33 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg); 34 34 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg); 35 + u64 soc_v1_0_encode_ext_smn_addressing(int ext_id); 35 36 36 37 #endif