drm/xe: restrict multi-lrc to VCS/VECS engines

Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
VIDEO_ENHANCE engines only. This check should have been in place from the
start, as the driver typically avoids allowing uapi cases that we have
no userspace consumer for.

Additionally, the GuC firmware on ModSched platforms no longer supports
multi-lrc on non-media engines.

V4:
- use a unified mask for all platforms since engine instance count
is an independent runtime check (Matt Roper, Matthew Brost)

V3:
- store a multi-lrc enable class mask in xe->info and populate from
xe_device_desc in xe_pci.c (Matthew Brost)

V2:
- correct the typo (Shuicheng)
- move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
- remove the graphics version check (Matt Roper)
- input more details in the commit info (Matt Roper)

Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260225022014.45394-1-x.wang@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

authored by

Xin Wang and committed by

Matt Roper 4 months ago 223b2f51 8ccf5f6b

+29

4 changed files

expand all

drivers

gpu

drm

xe_device_types.h

xe_exec_queue.c

xe_pci.c

xe_pci_types.h

drivers/gpu/drm/xe/xe_device_types.h

··· 138 138 u8 tile_count; 139 139 /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */ 140 140 u8 max_gt_per_tile; 141 + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */ 142 + u8 multi_lrc_mask; 141 143 /** @info.gt_count: Total number of GTs for entire device */ 142 144 u8 gt_count; 143 145 /** @info.vm_max_level: Max VM level */

drivers/gpu/drm/xe/xe_exec_queue.c

··· 1184 1184 if (XE_IOCTL_DBG(xe, !hwe)) 1185 1185 return -EINVAL; 1186 1186 1187 + /* multi-lrc is only supported on select engine classes */ 1188 + if (XE_IOCTL_DBG(xe, args->width > 1 && 1189 + !(xe->info.multi_lrc_mask & BIT(hwe->class)))) 1190 + return -EOPNOTSUPP; 1191 + 1187 1192 vm = xe_vm_lookup(xef, args->vm_id); 1188 1193 if (XE_IOCTL_DBG(xe, !vm)) 1189 1194 return -ENOENT;

+21

drivers/gpu/drm/xe/xe_pci.c

··· 184 184 { 3503, "Xe3p_HPM", &media_xelpmp }, 185 185 }; 186 186 187 + #define MULTI_LRC_MASK \ 188 + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \ 189 + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE) 190 + 187 191 static const struct xe_device_desc tgl_desc = { 188 192 .pre_gmdid_graphics_ip = &graphics_ip_xelp, 189 193 .pre_gmdid_media_ip = &media_ip_xem, ··· 198 194 .has_llc = true, 199 195 .has_sriov = true, 200 196 .max_gt_per_tile = 1, 197 + MULTI_LRC_MASK, 201 198 .require_force_probe = true, 202 199 .va_bits = 48, 203 200 .vm_max_level = 3, ··· 213 208 .has_display = true, 214 209 .has_llc = true, 215 210 .max_gt_per_tile = 1, 211 + MULTI_LRC_MASK, 216 212 .require_force_probe = true, 217 213 .va_bits = 48, 218 214 .vm_max_level = 3, ··· 231 225 .has_llc = true, 232 226 .has_sriov = true, 233 227 .max_gt_per_tile = 1, 228 + MULTI_LRC_MASK, 234 229 .require_force_probe = true, 235 230 .subplatforms = (const struct xe_subplatform_desc[]) { 236 231 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids }, ··· 253 246 .has_llc = true, 254 247 .has_sriov = true, 255 248 .max_gt_per_tile = 1, 249 + MULTI_LRC_MASK, 256 250 .require_force_probe = true, 257 251 .subplatforms = (const struct xe_subplatform_desc[]) { 258 252 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids }, ··· 273 265 .has_llc = true, 274 266 .has_sriov = true, 275 267 .max_gt_per_tile = 1, 268 + MULTI_LRC_MASK, 276 269 .require_force_probe = true, 277 270 .va_bits = 48, 278 271 .vm_max_level = 3, ··· 292 283 .has_gsc_nvm = 1, 293 284 .has_heci_gscfi = 1, 294 285 .max_gt_per_tile = 1, 286 + MULTI_LRC_MASK, 295 287 .require_force_probe = true, 296 288 .va_bits = 48, 297 289 .vm_max_level = 3, ··· 323 313 .pre_gmdid_media_ip = &media_ip_xehpm, 324 314 .dma_mask_size = 46, 325 315 .max_gt_per_tile = 1, 316 + MULTI_LRC_MASK, 326 317 .require_force_probe = true, 327 318 328 319 DG2_FEATURES, ··· 336 325 .pre_gmdid_media_ip = &media_ip_xehpm, 337 326 .dma_mask_size = 46, 338 327 .max_gt_per_tile = 1, 328 + MULTI_LRC_MASK, 339 329 .require_force_probe = true, 340 330 341 331 DG2_FEATURES, ··· 355 343 .has_heci_gscfi = 1, 356 344 .max_gt_per_tile = 1, 357 345 .max_remote_tiles = 1, 346 + MULTI_LRC_MASK, 358 347 .require_force_probe = true, 359 348 .va_bits = 57, 360 349 .vm_max_level = 4, ··· 371 358 .has_display = true, 372 359 .has_pxp = true, 373 360 .max_gt_per_tile = 2, 361 + MULTI_LRC_MASK, 374 362 .va_bits = 48, 375 363 .vm_max_level = 3, 376 364 }; ··· 383 369 .has_flat_ccs = 1, 384 370 .has_pxp = true, 385 371 .max_gt_per_tile = 2, 372 + MULTI_LRC_MASK, 386 373 .needs_scratch = true, 387 374 .va_bits = 48, 388 375 .vm_max_level = 4, ··· 408 393 .has_soc_remapper_telem = true, 409 394 .has_sriov = true, 410 395 .max_gt_per_tile = 2, 396 + MULTI_LRC_MASK, 411 397 .needs_scratch = true, 412 398 .subplatforms = (const struct xe_subplatform_desc[]) { 413 399 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids }, ··· 427 411 .has_pre_prod_wa = 1, 428 412 .has_pxp = true, 429 413 .max_gt_per_tile = 2, 414 + MULTI_LRC_MASK, 430 415 .needs_scratch = true, 431 416 .needs_shared_vf_gt_wq = true, 432 417 .va_bits = 48, ··· 441 424 .has_flat_ccs = 1, 442 425 .has_pre_prod_wa = 1, 443 426 .max_gt_per_tile = 2, 427 + MULTI_LRC_MASK, 444 428 .require_force_probe = true, 445 429 .va_bits = 48, 446 430 .vm_max_level = 4, ··· 463 445 .has_soc_remapper_telem = true, 464 446 .has_sriov = true, 465 447 .max_gt_per_tile = 2, 448 + MULTI_LRC_MASK, 466 449 .require_force_probe = true, 467 450 .va_bits = 57, 468 451 .vm_max_level = 4, ··· 478 459 .has_page_reclaim_hw_assist = true, 479 460 .has_pre_prod_wa = true, 480 461 .max_gt_per_tile = 2, 462 + MULTI_LRC_MASK, 481 463 .require_force_probe = true, 482 464 .va_bits = 48, 483 465 .vm_max_level = 4, ··· 765 745 xe->info.skip_pcode = desc->skip_pcode; 766 746 xe->info.needs_scratch = desc->needs_scratch; 767 747 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq; 748 + xe->info.multi_lrc_mask = desc->multi_lrc_mask; 768 749 769 750 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) && 770 751 xe_modparam.probe_display &&

drivers/gpu/drm/xe/xe_pci_types.h

··· 30 30 u8 dma_mask_size; 31 31 u8 max_remote_tiles:2; 32 32 u8 max_gt_per_tile:2; 33 + u8 multi_lrc_mask; 33 34 u8 va_bits; 34 35 u8 vm_max_level; 35 36 u8 vram_flags;

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