tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c

Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.

v2: Remove from common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-14-uma.shankar@intel.com

Uma Shankar 22625d19 a8454813

+12 -13
-1
drivers/gpu/drm/i915/display/g4x_hdmi.c
··· 8 8 #include <drm/drm_print.h> 9 9 10 10 #include "g4x_hdmi.h" 11 - #include "i915_reg.h" 12 11 #include "intel_atomic.h" 13 12 #include "intel_audio.h" 14 13 #include "intel_connector.h"
+12
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 2144 2144 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 2145 2145 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 2146 2146 2147 + /* Icelake PPS_DATA and _ECC DIP Registers. 2148 + * These are available for transcoders B,C and eDP. 2149 + * Adding the _A so as to reuse the _MMIO_TRANS2 2150 + * definition, with which it offsets to the right location. 2151 + */ 2152 + 2153 + #define _TRANSA_CHICKEN1 0xf0060 2154 + #define _TRANSB_CHICKEN1 0xf1060 2155 + #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 2156 + #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 2157 + #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 2158 + 2147 2159 #define _TRANSA_CHICKEN2 0xf0064 2148 2160 #define _TRANSB_CHICKEN2 0xf1064 2149 2161 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-12
drivers/gpu/drm/i915/i915_reg.h
··· 836 836 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 837 837 838 838 839 - /* Icelake PPS_DATA and _ECC DIP Registers. 840 - * These are available for transcoders B,C and eDP. 841 - * Adding the _A so as to reuse the _MMIO_TRANS2 842 - * definition, with which it offsets to the right location. 843 - */ 844 - 845 - #define _TRANSA_CHICKEN1 0xf0060 846 - #define _TRANSB_CHICKEN1 0xf1060 847 - #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 848 - #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 849 - #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 850 - 851 839 #define VLV_PMWGICZ _MMIO(0x1300a4) 852 840 853 841 #define HSW_EDRAM_CAP _MMIO(0x120010)