tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915: Remove i915_reg.h from i9xx_wm.c

Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include. Introduce a common
intel_gmd_misc_regs.h to define common miscellaneous
register definitions across graphics and display.

v3: MISC header included as needed, drop from i915_reg (Jani)

v2: Introdue a common misc header for GMD

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-13-uma.shankar@intel.com

Uma Shankar a8454813 5504f1ac

+38 -21
+1 -1
drivers/gpu/drm/i915/display/i9xx_wm.c
··· 6 6 #include <linux/iopoll.h> 7 7 8 8 #include <drm/drm_print.h> 9 + #include <drm/intel/intel_gmd_misc_regs.h> 9 10 10 - #include "i915_reg.h" 11 11 #include "i9xx_wm.h" 12 12 #include "i9xx_wm_regs.h" 13 13 #include "intel_atomic.h"
+1
drivers/gpu/drm/i915/display/intel_display_debugfs.c
··· 13 13 #include <drm/drm_file.h> 14 14 #include <drm/drm_fourcc.h> 15 15 #include <drm/drm_print.h> 16 + #include <drm/intel/intel_gmd_misc_regs.h> 16 17 17 18 #include "hsw_ips.h" 18 19 #include "i915_reg.h"
+6 -1
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 3132 3132 #define MTL_TRAS_MASK REG_GENMASK(16, 8) 3133 3133 #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) 3134 3134 3135 - 3135 + #define FW_BLC _MMIO(0x20d8) 3136 + #define FW_BLC2 _MMIO(0x20dc) 3137 + #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 3138 + #define FW_BLC_SELF_EN_MASK REG_BIT(31) 3139 + #define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ 3140 + #define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ 3136 3141 3137 3142 #endif /* __INTEL_DISPLAY_REGS_H__ */
+1
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
··· 6 6 #include <linux/highmem.h> 7 7 8 8 #include <drm/drm_print.h> 9 + #include <drm/intel/intel_gmd_misc_regs.h> 9 10 10 11 #include "display/intel_display.h" 11 12 #include "i915_drv.h"
+1
drivers/gpu/drm/i915/gt/intel_ring_submission.c
··· 5 5 6 6 #include <drm/drm_cache.h> 7 7 #include <drm/intel/intel_gmd_interrupt_regs.h> 8 + #include <drm/intel/intel_gmd_misc_regs.h> 8 9 9 10 #include "gem/i915_gem_internal.h" 10 11
+2
drivers/gpu/drm/i915/gt/intel_workarounds.c
··· 3 3 * Copyright © 2014-2018 Intel Corporation 4 4 */ 5 5 6 + #include <drm/intel/intel_gmd_misc_regs.h> 7 + 6 8 #include "i915_drv.h" 7 9 #include "i915_reg.h" 8 10 #include "i915_mmio_range.h"
+1
drivers/gpu/drm/i915/gvt/cmd_parser.c
··· 37 37 #include <linux/slab.h> 38 38 39 39 #include <drm/drm_print.h> 40 + #include <drm/intel/intel_gmd_misc_regs.h> 40 41 41 42 #include "display/i9xx_plane_regs.h" 42 43 #include "display/intel_display_regs.h"
+1
drivers/gpu/drm/i915/gvt/mmio_context.c
··· 34 34 */ 35 35 36 36 #include <drm/drm_print.h> 37 + #include <drm/intel/intel_gmd_misc_regs.h> 37 38 38 39 #include "gt/intel_context.h" 39 40 #include "gt/intel_engine_regs.h"
+1
drivers/gpu/drm/i915/i915_debugfs.c
··· 33 33 34 34 #include <drm/drm_debugfs.h> 35 35 #include <drm/drm_print.h> 36 + #include <drm/intel/intel_gmd_misc_regs.h> 36 37 37 38 #include "gem/i915_gem_context.h" 38 39 #include "gt/intel_gt.h"
-19
drivers/gpu/drm/i915/i915_reg.h
··· 393 393 394 394 #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) 395 395 396 - #define INSTPM _MMIO(0x20c0) 397 - #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 398 - #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 399 - will not assert AGPBUSY# and will only 400 - be delivered when out of C3. */ 401 - #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 402 - #define INSTPM_TLB_INVALIDATE (1 << 9) 403 - #define INSTPM_SYNC_FLUSH (1 << 5) 404 396 #define MEM_MODE _MMIO(0x20cc) 405 397 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 406 398 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 407 399 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 408 - #define FW_BLC _MMIO(0x20d8) 409 - #define FW_BLC2 _MMIO(0x20dc) 410 - #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 411 - #define FW_BLC_SELF_EN_MASK REG_BIT(31) 412 - #define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ 413 - #define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ 414 400 #define MM_BURST_LENGTH 0x00700000 415 401 #define MM_FIFO_WATERMARK 0x0001F000 416 402 #define LM_BURST_LENGTH 0x00000700 ··· 818 832 #define CHICKEN_PAR2_1 _MMIO(0x42090) 819 833 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) 820 834 821 - 822 - #define DISP_ARB_CTL _MMIO(0x45000) 823 - #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 824 - #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 825 - #define DISP_FBC_WM_DIS REG_BIT(15) 826 835 827 836 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 828 837 #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
+1
drivers/gpu/drm/i915/intel_clock_gating.c
··· 26 26 */ 27 27 28 28 #include <drm/drm_print.h> 29 + #include <drm/intel/intel_gmd_misc_regs.h> 29 30 30 31 #include "display/i9xx_plane_regs.h" 31 32 #include "display/intel_display.h"
+1
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
··· 4 4 */ 5 5 6 6 #include <drm/intel/intel_pcode_regs.h> 7 + #include <drm/intel/intel_gmd_misc_regs.h> 7 8 8 9 #include "display/bxt_dpio_phy_regs.h" 9 10 #include "display/i9xx_plane_regs.h"
+21
include/drm/intel/intel_gmd_misc_regs.h
··· 1 + /* SPDX-License-Identifier: MIT */ 2 + /* Copyright © 2026 Intel Corporation */ 3 + 4 + #ifndef _INTEL_GMD_MISC_REGS_H_ 5 + #define _INTEL_GMD_MISC_REGS_H_ 6 + 7 + #define DISP_ARB_CTL _MMIO(0x45000) 8 + #define DISP_FBC_MEMORY_WAKE REG_BIT(31) 9 + #define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) 10 + #define DISP_FBC_WM_DIS REG_BIT(15) 11 + 12 + #define INSTPM _MMIO(0x20c0) 13 + #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 14 + #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 15 + will not assert AGPBUSY# and will only 16 + be delivered when out of C3. */ 17 + #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 18 + #define INSTPM_TLB_INVALIDATE (1 << 9) 19 + #define INSTPM_SYNC_FLUSH (1 << 5) 20 + 21 + #endif