tjh.dev / kernel
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drm/msm: Offset MDSS HBB value by 13

The Adreno part of the driver exposes this value to userspace, and the
SMEM data source also presents a x+13 value. Keep things coherent and
make the value uniform across them.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660961/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Konrad Dybcio and committed by
Rob Clark 227d4ce0 1924272b

+26 -26
+26 -26
drivers/gpu/drm/msm/msm_mdss.c
··· 167 167 { 168 168 const struct msm_mdss_data *data = msm_mdss->mdss_data; 169 169 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | 170 - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); 170 + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 171 171 172 172 if (data->ubwc_bank_spread) 173 173 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; ··· 182 182 { 183 183 const struct msm_mdss_data *data = msm_mdss->mdss_data; 184 184 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | 185 - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); 185 + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 186 186 187 187 if (data->macrotile_mode) 188 188 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; ··· 200 200 { 201 201 const struct msm_mdss_data *data = msm_mdss->mdss_data; 202 202 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | 203 - MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); 203 + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 204 204 205 205 if (data->ubwc_bank_spread) 206 206 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; ··· 277 277 278 278 if (hw_rev == MDSS_HW_MSM8996 || 279 279 hw_rev == MDSS_HW_MSM8998) 280 - data->highest_bank_bit = 2; 280 + data->highest_bank_bit = 15; 281 281 else 282 - data->highest_bank_bit = 1; 282 + data->highest_bank_bit = 14; 283 283 284 284 return data; 285 285 } ··· 593 593 static const struct msm_mdss_data msm8998_data = { 594 594 .ubwc_enc_version = UBWC_1_0, 595 595 .ubwc_dec_version = UBWC_1_0, 596 - .highest_bank_bit = 2, 596 + .highest_bank_bit = 15, 597 597 .reg_bus_bw = 76800, 598 598 }; 599 599 600 600 static const struct msm_mdss_data qcm2290_data = { 601 601 /* no UBWC */ 602 - .highest_bank_bit = 0x2, 602 + .highest_bank_bit = 15, 603 603 .reg_bus_bw = 76800, 604 604 }; 605 605 ··· 608 608 .ubwc_dec_version = UBWC_4_0, 609 609 .ubwc_swizzle = 4, 610 610 .ubwc_bank_spread = true, 611 - .highest_bank_bit = 0, 611 + .highest_bank_bit = 13, 612 612 .macrotile_mode = true, 613 613 .reg_bus_bw = 74000, 614 614 }; ··· 618 618 .ubwc_dec_version = UBWC_4_3, 619 619 .ubwc_swizzle = 6, 620 620 .ubwc_bank_spread = true, 621 - .highest_bank_bit = 0, 621 + .highest_bank_bit = 13, 622 622 .macrotile_mode = 1, 623 623 .reg_bus_bw = 74000, 624 624 }; ··· 628 628 .ubwc_dec_version = UBWC_2_0, 629 629 .ubwc_swizzle = 6, 630 630 .ubwc_bank_spread = true, 631 - .highest_bank_bit = 0x1, 631 + .highest_bank_bit = 14, 632 632 .reg_bus_bw = 76800, 633 633 }; 634 634 ··· 637 637 .ubwc_dec_version = UBWC_4_0, 638 638 .ubwc_swizzle = 6, 639 639 .ubwc_bank_spread = true, 640 - .highest_bank_bit = 1, 640 + .highest_bank_bit = 14, 641 641 .macrotile_mode = true, 642 642 .reg_bus_bw = 74000, 643 643 }; ··· 645 645 static const struct msm_mdss_data sc8180x_data = { 646 646 .ubwc_enc_version = UBWC_3_0, 647 647 .ubwc_dec_version = UBWC_3_0, 648 - .highest_bank_bit = 3, 648 + .highest_bank_bit = 16, 649 649 .macrotile_mode = true, 650 650 .reg_bus_bw = 76800, 651 651 }; ··· 655 655 .ubwc_dec_version = UBWC_4_0, 656 656 .ubwc_swizzle = 6, 657 657 .ubwc_bank_spread = true, 658 - .highest_bank_bit = 3, 658 + .highest_bank_bit = 16, 659 659 .macrotile_mode = true, 660 660 .reg_bus_bw = 76800, 661 661 }; ··· 663 663 static const struct msm_mdss_data sdm670_data = { 664 664 .ubwc_enc_version = UBWC_2_0, 665 665 .ubwc_dec_version = UBWC_2_0, 666 - .highest_bank_bit = 1, 666 + .highest_bank_bit = 14, 667 667 .reg_bus_bw = 76800, 668 668 }; 669 669 670 670 static const struct msm_mdss_data sdm845_data = { 671 671 .ubwc_enc_version = UBWC_2_0, 672 672 .ubwc_dec_version = UBWC_2_0, 673 - .highest_bank_bit = 2, 673 + .highest_bank_bit = 15, 674 674 .reg_bus_bw = 76800, 675 675 }; 676 676 ··· 679 679 .ubwc_dec_version = UBWC_2_0, 680 680 .ubwc_swizzle = 6, 681 681 .ubwc_bank_spread = true, 682 - .highest_bank_bit = 1, 682 + .highest_bank_bit = 14, 683 683 .reg_bus_bw = 76800, 684 684 }; 685 685 686 686 static const struct msm_mdss_data sm7150_data = { 687 687 .ubwc_enc_version = UBWC_2_0, 688 688 .ubwc_dec_version = UBWC_2_0, 689 - .highest_bank_bit = 1, 689 + .highest_bank_bit = 14, 690 690 .reg_bus_bw = 76800, 691 691 }; 692 692 693 693 static const struct msm_mdss_data sm8150_data = { 694 694 .ubwc_enc_version = UBWC_3_0, 695 695 .ubwc_dec_version = UBWC_3_0, 696 - .highest_bank_bit = 2, 696 + .highest_bank_bit = 15, 697 697 .reg_bus_bw = 76800, 698 698 }; 699 699 ··· 702 702 .ubwc_dec_version = UBWC_2_0, 703 703 .ubwc_swizzle = 7, 704 704 .ubwc_bank_spread = true, 705 - .highest_bank_bit = 0x1, 705 + .highest_bank_bit = 14, 706 706 .reg_bus_bw = 76800, 707 707 }; 708 708 ··· 710 710 .ubwc_enc_version = UBWC_1_0, 711 711 .ubwc_dec_version = UBWC_3_0, 712 712 .ubwc_swizzle = 1, 713 - .highest_bank_bit = 1, 713 + .highest_bank_bit = 14, 714 714 }; 715 715 716 716 static const struct msm_mdss_data sm6150_data = { 717 717 .ubwc_enc_version = UBWC_2_0, 718 718 .ubwc_dec_version = UBWC_2_0, 719 - .highest_bank_bit = 1, 719 + .highest_bank_bit = 14, 720 720 .reg_bus_bw = 76800, 721 721 }; 722 722 ··· 726 726 .ubwc_swizzle = 6, 727 727 .ubwc_bank_spread = true, 728 728 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 729 - .highest_bank_bit = 3, 729 + .highest_bank_bit = 16, 730 730 .macrotile_mode = true, 731 731 .reg_bus_bw = 76800, 732 732 }; ··· 737 737 .ubwc_swizzle = 6, 738 738 .ubwc_bank_spread = true, 739 739 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 740 - .highest_bank_bit = 3, 740 + .highest_bank_bit = 16, 741 741 .macrotile_mode = true, 742 742 .reg_bus_bw = 74000, 743 743 }; ··· 748 748 .ubwc_swizzle = 6, 749 749 .ubwc_bank_spread = true, 750 750 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 751 - .highest_bank_bit = 3, 751 + .highest_bank_bit = 16, 752 752 .macrotile_mode = true, 753 753 .reg_bus_bw = 57000, 754 754 }; ··· 759 759 .ubwc_swizzle = 6, 760 760 .ubwc_bank_spread = true, 761 761 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 762 - .highest_bank_bit = 3, 762 + .highest_bank_bit = 16, 763 763 .macrotile_mode = true, 764 764 .reg_bus_bw = 57000, 765 765 }; ··· 770 770 .ubwc_swizzle = 6, 771 771 .ubwc_bank_spread = true, 772 772 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 773 - .highest_bank_bit = 3, 773 + .highest_bank_bit = 16, 774 774 .macrotile_mode = true, 775 775 /* TODO: Add reg_bus_bw with real value */ 776 776 };