Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655376/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-9-3b2085a07884@oss.qualcomm.com
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
ef31cf53
2ae7e2cd
+7
-57
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
···
41
41
{
42
42
.name = "ctl_0", .id = CTL_0,
43
43
.base = 0x1000, .len = 0x1e0,
44
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
45
44
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46
45
}, {
47
46
.name = "ctl_1", .id = CTL_1,
48
47
.base = 0x1200, .len = 0x1e0,
49
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
50
48
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
51
49
}, {
52
50
.name = "ctl_2", .id = CTL_2,
53
51
.base = 0x1400, .len = 0x1e0,
54
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
55
52
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
56
53
}, {
57
54
.name = "ctl_3", .id = CTL_3,
58
55
.base = 0x1600, .len = 0x1e0,
59
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
60
56
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
61
57
}, {
62
58
.name = "ctl_4", .id = CTL_4,
63
59
.base = 0x1800, .len = 0x1e0,
64
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
65
60
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
66
61
}, {
67
62
.name = "ctl_5", .id = CTL_5,
68
63
.base = 0x1a00, .len = 0x1e0,
69
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
70
64
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
71
65
},
72
66
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
···
41
41
{
42
42
.name = "ctl_0", .id = CTL_0,
43
43
.base = 0x1000, .len = 0x1e0,
44
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
45
44
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46
45
}, {
47
46
.name = "ctl_1", .id = CTL_1,
48
47
.base = 0x1200, .len = 0x1e0,
49
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
50
48
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
51
49
}, {
52
50
.name = "ctl_2", .id = CTL_2,
53
51
.base = 0x1400, .len = 0x1e0,
54
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
55
52
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
56
53
}, {
57
54
.name = "ctl_3", .id = CTL_3,
58
55
.base = 0x1600, .len = 0x1e0,
59
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
60
56
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
61
57
}, {
62
58
.name = "ctl_4", .id = CTL_4,
63
59
.base = 0x1800, .len = 0x1e0,
64
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
65
60
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
66
61
}, {
67
62
.name = "ctl_5", .id = CTL_5,
68
63
.base = 0x1a00, .len = 0x1e0,
69
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
70
64
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
71
65
},
72
66
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
···
38
38
{
39
39
.name = "ctl_0", .id = CTL_0,
40
40
.base = 0x1000, .len = 0x1e0,
41
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
42
41
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
43
42
}, {
44
43
.name = "ctl_1", .id = CTL_1,
45
44
.base = 0x1200, .len = 0x1e0,
46
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
47
45
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
48
46
}, {
49
47
.name = "ctl_2", .id = CTL_2,
50
48
.base = 0x1400, .len = 0x1e0,
51
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
52
49
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
53
50
}, {
54
51
.name = "ctl_3", .id = CTL_3,
55
52
.base = 0x1600, .len = 0x1e0,
56
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
57
53
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
58
54
}, {
59
55
.name = "ctl_4", .id = CTL_4,
60
56
.base = 0x1800, .len = 0x1e0,
61
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
62
57
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
63
58
}, {
64
59
.name = "ctl_5", .id = CTL_5,
65
60
.base = 0x1a00, .len = 0x1e0,
66
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
67
61
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
68
62
},
69
63
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
···
35
35
{
36
36
.name = "ctl_0", .id = CTL_0,
37
37
.base = 0x1000, .len = 0x1e0,
38
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
39
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
40
39
}, {
41
40
.name = "ctl_1", .id = CTL_1,
42
41
.base = 0x1200, .len = 0x1e0,
43
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
44
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45
43
}, {
46
44
.name = "ctl_2", .id = CTL_2,
47
45
.base = 0x1400, .len = 0x1e0,
48
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
49
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50
47
}, {
51
48
.name = "ctl_3", .id = CTL_3,
52
49
.base = 0x1600, .len = 0x1e0,
53
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
54
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
55
51
}, {
56
52
.name = "ctl_4", .id = CTL_4,
57
53
.base = 0x1800, .len = 0x1e0,
58
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
59
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
60
55
}, {
61
56
.name = "ctl_5", .id = CTL_5,
62
57
.base = 0x1a00, .len = 0x1e0,
63
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
64
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
65
59
},
66
60
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
···
35
35
{
36
36
.name = "ctl_0", .id = CTL_0,
37
37
.base = 0x1000, .len = 0x1e0,
38
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
39
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
40
39
}, {
41
40
.name = "ctl_1", .id = CTL_1,
42
41
.base = 0x1200, .len = 0x1e0,
43
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
44
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45
43
}, {
46
44
.name = "ctl_2", .id = CTL_2,
47
45
.base = 0x1400, .len = 0x1e0,
48
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
49
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50
47
}, {
51
48
.name = "ctl_3", .id = CTL_3,
52
49
.base = 0x1600, .len = 0x1e0,
53
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
54
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
55
51
}, {
56
52
.name = "ctl_4", .id = CTL_4,
57
53
.base = 0x1800, .len = 0x1e0,
58
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
59
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
60
55
}, {
61
56
.name = "ctl_5", .id = CTL_5,
62
57
.base = 0x1a00, .len = 0x1e0,
63
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
64
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
65
59
},
66
60
};
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
···
39
39
{
40
40
.name = "ctl_0", .id = CTL_0,
41
41
.base = 0x1000, .len = 0x1e0,
42
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
43
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
44
43
}, {
45
44
.name = "ctl_1", .id = CTL_1,
46
45
.base = 0x1200, .len = 0x1e0,
47
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
48
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
49
47
}, {
50
48
.name = "ctl_2", .id = CTL_2,
51
49
.base = 0x1400, .len = 0x1e0,
52
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
53
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
54
51
}, {
55
52
.name = "ctl_3", .id = CTL_3,
56
53
.base = 0x1600, .len = 0x1e0,
57
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
58
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
59
55
}, {
60
56
.name = "ctl_4", .id = CTL_4,
61
57
.base = 0x1800, .len = 0x1e0,
62
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
63
58
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64
59
}, {
65
60
.name = "ctl_5", .id = CTL_5,
66
61
.base = 0x1a00, .len = 0x1e0,
67
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
68
62
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
69
63
},
70
64
};
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
-3
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
···
32
32
{
33
33
.name = "ctl_0", .id = CTL_0,
34
34
.base = 0x1000, .len = 0x1dc,
35
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
36
35
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
37
36
}, {
38
37
.name = "ctl_1", .id = CTL_1,
39
38
.base = 0x1200, .len = 0x1dc,
40
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
41
39
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
42
40
}, {
43
41
.name = "ctl_2", .id = CTL_2,
44
42
.base = 0x1400, .len = 0x1dc,
45
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
46
43
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
47
44
},
48
45
};
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
···
35
35
{
36
36
.name = "ctl_0", .id = CTL_0,
37
37
.base = 0x1000, .len = 0x1dc,
38
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
39
38
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
40
39
}, {
41
40
.name = "ctl_1", .id = CTL_1,
42
41
.base = 0x1200, .len = 0x1dc,
43
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
44
42
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
45
43
}, {
46
44
.name = "ctl_2", .id = CTL_2,
47
45
.base = 0x1400, .len = 0x1dc,
48
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
49
46
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
50
47
}, {
51
48
.name = "ctl_3", .id = CTL_3,
52
49
.base = 0x1600, .len = 0x1dc,
53
-
.features = BIT(DPU_CTL_ACTIVE_CFG),
54
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
55
51
},
56
52
};
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+2
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
···
69
69
ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
70
70
71
71
/* setup which pp blk will connect to this intf */
72
-
if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
72
+
if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&
73
+
phys_enc->hw_intf->ops.bind_pingpong_blk)
73
74
phys_enc->hw_intf->ops.bind_pingpong_blk(
74
75
phys_enc->hw_intf,
75
76
phys_enc->hw_pp->idx);
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
···
377
377
static bool dpu_encoder_phys_vid_needs_single_flush(
378
378
struct dpu_encoder_phys *phys_enc)
379
379
{
380
-
return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&
380
+
return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) &&
381
381
phys_enc->split_role != ENC_ROLE_SOLO;
382
382
}
383
383
+2
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+2
-5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
···
218
218
static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
219
219
{
220
220
struct dpu_hw_wb *hw_wb;
221
-
struct dpu_hw_ctl *ctl;
222
221
struct dpu_hw_cdm *hw_cdm;
223
222
224
223
if (!phys_enc) {
···
226
227
}
227
228
228
229
hw_wb = phys_enc->hw_wb;
229
-
ctl = phys_enc->hw_ctl;
230
230
hw_cdm = phys_enc->hw_cdm;
231
231
232
-
if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
232
+
if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&
233
233
(phys_enc->hw_ctl &&
234
234
phys_enc->hw_ctl->ops.setup_intf_cfg)) {
235
235
struct dpu_hw_intf_cfg intf_cfg = {0};
···
532
534
static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
533
535
{
534
536
struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
535
-
struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
536
537
537
538
DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
538
539
···
553
556
* WB support is added to those targets will need to add
554
557
* the legacy teardown sequence as well.
555
558
*/
556
-
if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
559
+
if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
557
560
dpu_encoder_helper_phys_cleanup(phys_enc);
558
561
559
562
phys_enc->enable_state = DPU_ENC_DISABLED;
+1
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+1
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
766
766
c->caps = cfg;
767
767
c->mdss_ver = mdss_ver;
768
768
769
-
if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
769
+
if (mdss_ver->core_major_ver >= 5) {
770
770
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
771
771
c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
772
772
c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;