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phy: rockchip: naneng-combphy: use existing DT property check for rk3528

The naneng-combphy driver already has DT property checks for
"rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
the rk3528_combphy_cfg. Also aligned the indentation of the
rk3528_combphy_grfcfgs parameters (using tabs).

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20250910122000.951100-1-amadeus@jmu.edu.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chukun Pan and committed by
Vinod Koul 23c3373a d10736db

+5 -7
+5 -7
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
··· 529 529 return -EINVAL; 530 530 } 531 531 532 - if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { 532 + if (priv->ext_refclk) { 533 533 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 534 534 535 535 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ··· 554 554 } 555 555 } 556 556 557 - if (priv->type == PHY_TYPE_PCIE) { 558 - if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) 559 - rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, 560 - RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); 561 - } 557 + if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc) 558 + rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN, 559 + RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40); 562 560 563 561 return 0; 564 562 } ··· 580 582 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, 581 583 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 582 584 /* pipe-grf */ 583 - .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, 585 + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, 584 586 }; 585 587 586 588 static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {