tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platforms

Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ
for the same version number. So in order to be able to differentiate
between them, add these ones with DP prefix.

Add the necessary PHY setting tables for enabling the DP path within the
QMP subsystem. Introduced some new callbacks for v8 specific sequences,
such as for clock configurations based on the different link speeds.

Wesley Cheng added some updated settings from the hardware programming
guides on existing PHY tables and clock settings.

Co-developed-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20251209-linux-next-12825-v8-9-42133596bda0@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Abel Vesa and committed by
Vinod Koul d10736db 5b289913

+428 -4
+351 -4
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 48 48 #include "phy-qcom-qmp-dp-phy-v4.h" 49 49 #include "phy-qcom-qmp-dp-phy-v5.h" 50 50 #include "phy-qcom-qmp-dp-phy-v6.h" 51 + #include "phy-qcom-qmp-dp-phy-v8.h" 51 52 52 53 #include "phy-qcom-qmp-usb43-pcs-v8.h" 53 54 ··· 104 103 QPHY_TX_TRANSCEIVER_BIAS_EN, 105 104 106 105 QPHY_AON_TOGGLE_ENABLE, 106 + QPHY_DP_AON_TOGGLE_ENABLE, 107 107 /* Keep last to ensure regs_layout arrays are properly initialized */ 108 108 QPHY_LAYOUT_SIZE 109 109 }; ··· 279 277 280 278 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE, 281 279 [QPHY_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE, 280 + [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, 282 281 283 282 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 284 283 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 285 284 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 286 285 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 286 + 287 + [QPHY_DP_PHY_STATUS] = QSERDES_V8_DP_PHY_STATUS, 288 + [QPHY_DP_PHY_VCO_DIV] = QSERDES_V8_DP_PHY_VCO_DIV, 287 289 288 290 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_LALB_TX0_DRV_LVL, 289 291 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_LALB_TX0_EMP_POST1_LVL, ··· 1384 1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1385 1379 }; 1386 1380 1381 + static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] = { 1382 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), 1383 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1384 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), 1385 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), 1386 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1387 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1388 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1389 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1390 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 1391 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 1392 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1393 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x00), 1394 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x00), 1395 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1396 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1397 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1398 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1399 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), 1400 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), 1401 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1402 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1403 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1404 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1405 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), 1406 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1407 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1408 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 1409 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 1410 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x01), 1411 + }; 1412 + 1387 1413 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1388 1414 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1389 1415 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), ··· 1441 1403 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1442 1404 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1443 1405 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1406 + }; 1407 + 1408 + static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] = { 1409 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), 1410 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), 1411 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), 1412 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), 1413 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), 1414 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), 1415 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), 1416 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), 1417 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), 1418 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), 1419 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), 1420 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), 1421 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), 1422 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), 1423 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), 1424 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), 1425 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), 1426 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), 1427 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), 1428 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), 1429 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 1430 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 1431 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 1432 + QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), 1444 1433 }; 1445 1434 1446 1435 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { ··· 1584 1519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1585 1520 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1586 1521 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1522 + }; 1523 + 1524 + static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] = { 1525 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), 1526 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), 1527 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), 1528 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), 1529 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), 1530 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), 1531 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), 1532 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1533 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), 1534 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xfe), 1535 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), 1536 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), 1537 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1538 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1539 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), 1540 + }; 1541 + 1542 + static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] = { 1543 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), 1544 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), 1545 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), 1546 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1547 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), 1548 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), 1549 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1550 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1551 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1552 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1553 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1554 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x04), 1555 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1556 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1557 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa3), 1558 + }; 1559 + 1560 + static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { 1561 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), 1562 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), 1563 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), 1564 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), 1565 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1566 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1567 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), 1568 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x0e), 1569 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1570 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1571 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1572 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1573 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1574 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), 1575 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), 1576 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1577 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), 1578 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), 1579 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1580 + }; 1581 + 1582 + static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { 1583 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), 1584 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), 1585 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1586 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), 1587 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1588 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1589 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1590 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1591 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1592 + 1593 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), 1594 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), 1595 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), 1596 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1597 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xa0), 1598 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 1599 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1600 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1601 + 1602 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xa0), 1603 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x01), 1604 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1605 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x6b), 1606 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 1607 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1608 + 1609 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1610 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1611 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1612 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), 1613 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1614 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1615 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1616 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1617 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), 1618 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1619 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1620 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x10), 1621 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x05), 1622 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1623 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x02), 1624 + QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0x84), 1587 1625 }; 1588 1626 1589 1627 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { ··· 2238 2070 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 2239 2071 2240 2072 /* DP PHY callbacks */ 2073 + int (*configure_dp_clocks)(struct qmp_combo *qmp); 2241 2074 int (*configure_dp_phy)(struct qmp_combo *qmp); 2242 2075 void (*configure_dp_tx)(struct qmp_combo *qmp); 2243 2076 int (*calibrate_dp_phy)(struct qmp_combo *qmp); ··· 2316 2147 2317 2148 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 2318 2149 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 2150 + static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp); 2319 2151 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 2320 2152 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 2321 2153 ··· 2324 2154 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 2325 2155 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 2326 2156 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 2157 + 2158 + static void qmp_v8_dp_aux_init(struct qmp_combo *qmp); 2159 + static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp); 2160 + static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp); 2327 2161 2328 2162 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2329 2163 { ··· 2462 2288 2463 2289 .dp_aux_init = qmp_v4_dp_aux_init, 2464 2290 .configure_dp_tx = qmp_v4_configure_dp_tx, 2291 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2465 2292 .configure_dp_phy = qmp_v4_configure_dp_phy, 2466 2293 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2467 2294 ··· 2598 2423 2599 2424 .dp_aux_init = qmp_v4_dp_aux_init, 2600 2425 .configure_dp_tx = qmp_v4_configure_dp_tx, 2426 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2601 2427 .configure_dp_phy = qmp_v4_configure_dp_phy, 2602 2428 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2603 2429 ··· 2645 2469 2646 2470 .dp_aux_init = qmp_v4_dp_aux_init, 2647 2471 .configure_dp_tx = qmp_v4_configure_dp_tx, 2472 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2648 2473 .configure_dp_phy = qmp_v4_configure_dp_phy, 2649 2474 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2650 2475 ··· 2691 2514 2692 2515 .dp_aux_init = qmp_v4_dp_aux_init, 2693 2516 .configure_dp_tx = qmp_v4_configure_dp_tx, 2517 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2694 2518 .configure_dp_phy = qmp_v4_configure_dp_phy, 2695 2519 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2696 2520 ··· 2780 2602 2781 2603 .dp_aux_init = qmp_v4_dp_aux_init, 2782 2604 .configure_dp_tx = qmp_v4_configure_dp_tx, 2605 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2783 2606 .configure_dp_phy = qmp_v4_configure_dp_phy, 2784 2607 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2785 2608 ··· 2829 2650 2830 2651 .dp_aux_init = qmp_v4_dp_aux_init, 2831 2652 .configure_dp_tx = qmp_v4_configure_dp_tx, 2653 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2832 2654 .configure_dp_phy = qmp_v4_configure_dp_phy, 2833 2655 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2834 2656 ··· 2877 2697 2878 2698 .dp_aux_init = qmp_v4_dp_aux_init, 2879 2699 .configure_dp_tx = qmp_v4_configure_dp_tx, 2700 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2880 2701 .configure_dp_phy = qmp_v4_configure_dp_phy, 2881 2702 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2882 2703 ··· 2923 2742 2924 2743 .dp_aux_init = qmp_v4_dp_aux_init, 2925 2744 .configure_dp_tx = qmp_v4_configure_dp_tx, 2745 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2926 2746 .configure_dp_phy = qmp_v4_configure_dp_phy, 2927 2747 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2928 2748 ··· 2969 2787 2970 2788 .dp_aux_init = qmp_v4_dp_aux_init, 2971 2789 .configure_dp_tx = qmp_v4_configure_dp_tx, 2790 + .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2972 2791 .configure_dp_phy = qmp_v4_configure_dp_phy, 2973 2792 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2974 2793 ··· 2993 2810 .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), 2994 2811 .pcs_misc_tbl = glymur_usb43dp_pcs_misc_tbl, 2995 2812 .pcs_misc_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), 2813 + 2814 + .dp_serdes_tbl = qmp_v8_dp_serdes_tbl, 2815 + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl), 2816 + .dp_tx_tbl = qmp_v8_n3p_dp_tx_tbl, 2817 + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v8_n3p_dp_tx_tbl), 2818 + 2819 + .serdes_tbl_rbr = qmp_v8_dp_serdes_tbl_rbr, 2820 + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_rbr), 2821 + .serdes_tbl_hbr = qmp_v8_dp_serdes_tbl_hbr, 2822 + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr), 2823 + .serdes_tbl_hbr2 = qmp_v8_dp_serdes_tbl_hbr2, 2824 + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr2), 2825 + .serdes_tbl_hbr3 = qmp_v8_dp_serdes_tbl_hbr3, 2826 + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr3), 2827 + 2828 + .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2829 + .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2830 + .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2831 + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2832 + 2833 + .dp_aux_init = qmp_v8_dp_aux_init, 2834 + .configure_dp_tx = qmp_v4_configure_dp_tx, 2835 + .configure_dp_clocks = qmp_v8_configure_dp_clocks, 2836 + .configure_dp_phy = qmp_v8_configure_dp_phy, 2837 + .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2996 2838 2997 2839 .regs = qmp_v8_n3_usb43dpphy_regs_layout, 2998 2840 .reset_list = msm8996_usb3phy_reset_l, ··· 3188 2980 return reverse; 3189 2981 } 3190 2982 3191 - static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2983 + static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp) 3192 2984 { 3193 2985 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3194 2986 u32 phy_vco_div; ··· 3235 3027 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 3236 3028 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 3237 3029 3238 - ret = qmp_combo_configure_dp_clocks(qmp); 3030 + ret = qmp_v3_configure_dp_clocks(qmp); 3239 3031 if (ret) 3240 3032 return ret; 3241 3033 ··· 3321 3113 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3322 3114 } 3323 3115 3116 + static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) 3117 + { 3118 + const struct qmp_phy_cfg *cfg = qmp->cfg; 3119 + 3120 + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3121 + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3122 + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3123 + 3124 + /* Turn on BIAS current for PHY/PLL */ 3125 + writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3126 + 3127 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3128 + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3129 + writel(0x06, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3130 + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3131 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3132 + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3133 + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3134 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3135 + writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3136 + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3137 + qmp->dp_aux_cfg = 0; 3138 + 3139 + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3140 + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3141 + PHY_AUX_REQ_ERR_MASK, 3142 + qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3143 + } 3144 + 3324 3145 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 3325 3146 { 3326 3147 const struct qmp_phy_cfg *cfg = qmp->cfg; ··· 3362 3125 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3363 3126 3364 3127 qmp_combo_configure_dp_swing(qmp); 3128 + } 3129 + 3130 + static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) 3131 + { 3132 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3133 + u32 phy_vco_div; 3134 + unsigned long pixel_freq; 3135 + const struct qmp_phy_cfg *cfg = qmp->cfg; 3136 + 3137 + switch (dp_opts->link_rate) { 3138 + case 1620: 3139 + phy_vco_div = 0x4; 3140 + pixel_freq = 1620000000UL / 2; 3141 + break; 3142 + case 2700: 3143 + phy_vco_div = 0x2; 3144 + pixel_freq = 2700000000UL / 2; 3145 + break; 3146 + case 5400: 3147 + phy_vco_div = 0x4; 3148 + pixel_freq = 5400000000UL / 4; 3149 + break; 3150 + case 8100: 3151 + phy_vco_div = 0x3; 3152 + pixel_freq = 8100000000UL / 6; 3153 + break; 3154 + default: 3155 + /* Other link rates aren't supported */ 3156 + return -EINVAL; 3157 + } 3158 + writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 3159 + 3160 + /* disable core reset tsync */ 3161 + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3162 + 3163 + writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); 3164 + writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); 3165 + writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); 3166 + writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3167 + 3168 + writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); 3169 + writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); 3170 + writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); 3171 + writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); 3172 + writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3173 + writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); 3174 + writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); 3175 + 3176 + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 3177 + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 3178 + 3179 + return 0; 3365 3180 } 3366 3181 3367 3182 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) ··· 3432 3143 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 3433 3144 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 3434 3145 3435 - ret = qmp_combo_configure_dp_clocks(qmp); 3146 + ret = qmp->cfg->configure_dp_clocks(qmp); 3436 3147 if (ret) 3437 3148 return ret; 3438 3149 ··· 3546 3257 return 0; 3547 3258 } 3548 3259 3260 + static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) 3261 + { 3262 + const struct qmp_phy_cfg *cfg = qmp->cfg; 3263 + bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3264 + const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3265 + u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 3266 + u32 status; 3267 + int ret; 3268 + 3269 + ret = qmp_v456_configure_dp_phy(qmp); 3270 + if (ret < 0) 3271 + return ret; 3272 + 3273 + if (dp_opts->lanes == 1) { 3274 + bias0_en = reverse ? 0x3e : 0x15; 3275 + bias1_en = reverse ? 0x15 : 0x3e; 3276 + drvr0_en = reverse ? 0x13 : 0x10; 3277 + drvr1_en = reverse ? 0x10 : 0x13; 3278 + } else if (dp_opts->lanes == 2) { 3279 + bias0_en = reverse ? 0x3f : 0x15; 3280 + bias1_en = reverse ? 0x15 : 0x3f; 3281 + drvr0_en = 0x10; 3282 + drvr1_en = 0x10; 3283 + } else { 3284 + bias0_en = 0x3f; 3285 + bias1_en = 0x3f; 3286 + drvr0_en = 0x34; 3287 + drvr1_en = 0x34; 3288 + } 3289 + 3290 + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3291 + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3292 + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3293 + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3294 + 3295 + writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3296 + udelay(100); 3297 + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3298 + udelay(500); 3299 + 3300 + if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3301 + status, 3302 + ((status & BIT(1)) > 0), 3303 + 500, 3304 + 10000)) 3305 + return -ETIMEDOUT; 3306 + 3307 + writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3308 + writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3309 + 3310 + writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3311 + writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3312 + 3313 + return 0; 3314 + } 3315 + 3549 3316 /* 3550 3317 * We need to calibrate the aux setting here as many times 3551 3318 * as the caller tries ··· 3696 3351 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3697 3352 3698 3353 /* override hardware control for reset of qmp phy */ 3699 - if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) 3354 + if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) { 3700 3355 qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); 3356 + qphy_clrbits(pcs_aon, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1); 3357 + } 3701 3358 3702 3359 /* Use software based port select and switch on typec orientation */ 3703 3360 val = SW_PORTSELECT_MUX;
+25
drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_DP_PHY_V8_H_ 7 + #define QCOM_PHY_QMP_DP_PHY_V8_H_ 8 + 9 + /* Only for QMP V8 PHY - DP PHY registers */ 10 + #define QSERDES_V8_DP_PHY_VCO_DIV 0x070 11 + #define QSERDES_V8_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0 12 + #define QSERDES_V8_DP_PHY_TSYNC_OVRD 0x074 13 + #define QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL 0x078 14 + #define QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL 0x0bc 15 + #define QSERDES_V8_DP_PHY_AUXLESS_CFG1 0x0c8 16 + #define QSERDES_V8_DP_PHY_LFPS_PERIOD 0x0d0 17 + #define QSERDES_V8_DP_PHY_LFPS_CYC 0x0d4 18 + #define QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC 0x0d8 19 + #define QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC 0x0d8 20 + #define QSERDES_V8_DP_PHY_LN0_DRV_LVL 0x0e0 21 + #define QSERDES_V8_DP_PHY_LN1_DRV_LVL 0x0e4 22 + #define QSERDES_V8_DP_PHY_STATUS 0x114 23 + 24 + 25 + #endif
+52
drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (C) 2025 Linaro Ltd. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ 7 + #define QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ 8 + 9 + /* Only for DP QMP V8 PHY - QSERDES COM registers */ 10 + #define DP_QSERDES_V8_COM_HSCLK_SEL_1 0x03c 11 + #define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 12 + #define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c 13 + #define DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 14 + #define DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 15 + #define DP_QSERDES_V8_COM_CP_CTRL_MODE0 0x070 16 + #define DP_QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 17 + #define DP_QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 18 + #define DP_QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c 19 + #define DP_QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 20 + #define DP_QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 21 + #define DP_QSERDES_V8_COM_DEC_START_MODE0 0x088 22 + #define DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 23 + #define DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 24 + #define DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 25 + #define DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 26 + #define DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 27 + #define DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 28 + #define DP_QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac 29 + #define DP_QSERDES_V8_COM_BG_TIMER 0x0bc 30 + #define DP_QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 31 + #define DP_QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 32 + #define DP_QSERDES_V8_COM_SSC_PER1 0x0cc 33 + #define DP_QSERDES_V8_COM_SSC_PER2 0x0d0 34 + #define DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc 35 + #define DP_QSERDES_V8_COM_CLK_ENABLE1 0x0e0 36 + #define DP_QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 37 + #define DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 38 + #define DP_QSERDES_V8_COM_PLL_IVCO 0x0f4 39 + #define DP_QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 40 + #define DP_QSERDES_V8_COM_RESETSM_CNTRL 0x118 41 + #define DP_QSERDES_V8_COM_LOCK_CMP_EN 0x120 42 + #define DP_QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c 43 + #define DP_QSERDES_V8_COM_VCO_TUNE_MAP 0x140 44 + #define DP_QSERDES_V8_COM_CLK_SELECT 0x164 45 + #define DP_QSERDES_V8_COM_CORE_CLK_EN 0x170 46 + #define DP_QSERDES_V8_COM_CMN_CONFIG_1 0x174 47 + #define DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL 0x180 48 + #define DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1 0x2f4 49 + #define DP_QSERDES_V8_COM_CMN_STATUS 0x314 50 + #define DP_QSERDES_V8_COM_C_READY_STATUS 0x33c 51 + 52 + #endif