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usb: dwc3: dwc3-octeon: Pass dwc3_octeon to setup functions

Pass dwc3_octeon instead of just the base. It fits with the
function names and it requires less change in the future if
access to dwc3_octeon is needed.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZMd/gt58laSlqAAT@lenoch
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Ladislav Michl and committed by
Greg Kroah-Hartman 23f87bca 41784066

+12 -11
+12 -11
drivers/usb/dwc3/dwc3-octeon.c
··· 300 300 return 0; 301 301 } 302 302 303 - static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) 303 + static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) 304 304 { 305 305 int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; 306 306 u32 clock_rate; 307 307 u64 val; 308 - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; 308 + struct device *dev = octeon->dev; 309 + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; 309 310 310 311 if (dev->of_node) { 311 312 const char *ss_clock_type; ··· 453 452 /* Step 8b: Wait 10 controller-clock cycles. */ 454 453 udelay(10); 455 454 456 - /* Steo 8c: Setup power-power control. */ 457 - if (dwc3_octeon_config_power(dev, base)) 455 + /* Step 8c: Setup power control. */ 456 + if (dwc3_octeon_config_power(dev, octeon->base)) 458 457 return -EINVAL; 459 458 460 459 /* Step 8d: Deassert UAHC reset signal. */ ··· 478 477 return 0; 479 478 } 480 479 481 - static void __init dwc3_octeon_set_endian_mode(void __iomem *base) 480 + static void dwc3_octeon_set_endian_mode(struct dwc3_octeon *octeon) 482 481 { 483 482 u64 val; 484 - void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; 483 + void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG; 485 484 486 485 val = dwc3_octeon_readq(uctl_shim_cfg_reg); 487 486 val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; ··· 493 492 dwc3_octeon_writeq(uctl_shim_cfg_reg, val); 494 493 } 495 494 496 - static void __init dwc3_octeon_phy_reset(void __iomem *base) 495 + static void dwc3_octeon_phy_reset(struct dwc3_octeon *octeon) 497 496 { 498 497 u64 val; 499 - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; 498 + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; 500 499 501 500 val = dwc3_octeon_readq(uctl_ctl_reg); 502 501 val &= ~USBDRD_UCTL_CTL_UPHY_RST; ··· 519 518 if (IS_ERR(octeon->base)) 520 519 return PTR_ERR(octeon->base); 521 520 522 - err = dwc3_octeon_clocks_start(dev, octeon->base); 521 + err = dwc3_octeon_clocks_start(octeon); 523 522 if (err) 524 523 return err; 525 524 526 - dwc3_octeon_set_endian_mode(octeon->base); 527 - dwc3_octeon_phy_reset(octeon->base); 525 + dwc3_octeon_set_endian_mode(octeon); 526 + dwc3_octeon_phy_reset(octeon); 528 527 529 528 platform_set_drvdata(pdev, octeon); 530 529