Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
usb: dwc3: dwc3-octeon: Use _ULL bitfields defines
While driver is intended to run on 64bit machines, it is compile time
tested for 32bit targets as well. Here shift count overflow is reported
for bits greater than 31, so use _ULL versions of BIT and GENMASK macros
to silence these warnings.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202307260537.MROrhVNM-lkp@intel.com/
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/ZMd/aa2ncz6tJGNU@lenoch
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Ladislav Michl
and committed by
Greg Kroah-Hartman
41784066
976f82e8
+39
-39
+39
-39
drivers/usb/dwc3/dwc3-octeon.c
+39
-39
drivers/usb/dwc3/dwc3-octeon.c
···
24
24
/* BIST fast-clear mode select. A BIST run with this bit set
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* clears all entries in USBH RAMs to 0x0.
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*/
27
-
# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63)
27
+
# define USBDRD_UCTL_CTL_CLEAR_BIST BIT_ULL(63)
28
28
/* 1 = Start BIST and cleared by hardware */
29
-
# define USBDRD_UCTL_CTL_START_BIST BIT(62)
29
+
# define USBDRD_UCTL_CTL_START_BIST BIT_ULL(62)
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/* Reference clock select for SuperSpeed and HighSpeed PLLs:
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* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
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* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
···
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* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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*/
38
-
# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60)
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+
# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60)
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39
/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
40
-
# define USBDRD_UCTL_CTL_SSC_EN BIT(59)
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+
# define USBDRD_UCTL_CTL_SSC_EN BIT_ULL(59)
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/* Spread-spectrum clock modulation range:
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* 0x0 = -4980 ppm downspread
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* 0x1 = -4492 ppm downspread
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* 0x2 = -4003 ppm downspread
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* 0x3 - 0x7 = Reserved
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*/
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-
# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56)
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+
# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK_ULL(58, 56)
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/* Enable non-standard oscillator frequencies:
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* [55:53] = modules -1
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* [52:47] = 2's complement push amount, 0 = Feature disabled
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*/
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-
# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47)
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+
# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47)
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/* Reference clock multiplier for non-standard frequencies:
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* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* Other Values = Reserved
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*/
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-
# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40)
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+
# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40)
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/* Enable reference clock to prescaler for SuperSpeed functionality.
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* Should always be set to "1"
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*/
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-
# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39)
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+
# define USBDRD_UCTL_CTL_REF_SSP_EN BIT_ULL(39)
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/* Divide the reference clock by 2 before entering the
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* REF_CLK_FSEL divider:
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* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
···
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* 0x1 = DLMC_REF_CLK* is 125MHz
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* 0x0 = DLMC_REF_CLK* is another supported frequency
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*/
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-
# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38)
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+
# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38)
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/* Select reference clock freqnuency for both PLL blocks:
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* 0x27 = REF_CLK_SEL is 0x0 or 0x1
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* 0x07 = REF_CLK_SEL is 0x2 or 0x3
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*/
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-
# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32)
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+
# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32)
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/* Controller clock enable. */
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-
# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30)
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+
# define USBDRD_UCTL_CTL_H_CLK_EN BIT_ULL(30)
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/* Select bypass input to controller clock divider:
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* 0x0 = Use divided coprocessor clock from H_CLKDIV
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* 0x1 = Use clock from GPIO pins
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*/
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-
# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29)
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+
# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT_ULL(29)
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/* Reset controller clock divider. */
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-
# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28)
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+
# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT_ULL(28)
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/* Clock divider select:
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* 0x0 = divide by 1
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* 0x1 = divide by 2
···
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* 0x6 = divide by 24
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* 0x7 = divide by 32
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*/
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-
# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24)
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+
# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24)
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/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21)
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+
# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT_ULL(21)
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/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20)
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+
# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT_ULL(20)
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/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18)
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+
# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT_ULL(18)
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/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16)
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+
# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT_ULL(16)
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/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14)
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+
# define USBDRD_UCTL_CTL_SS_POWER_EN BIT_ULL(14)
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/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12)
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+
# define USBDRD_UCTL_CTL_HS_POWER_EN BIT_ULL(12)
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/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
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-
# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4)
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+
# define USBDRD_UCTL_CTL_CSCLK_EN BIT_ULL(4)
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/* Controller mode: 0x0 = Host, 0x1 = Device */
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-
# define USBDRD_UCTL_CTL_DRD_MODE BIT(3)
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+
# define USBDRD_UCTL_CTL_DRD_MODE BIT_ULL(3)
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/* PHY reset */
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-
# define USBDRD_UCTL_CTL_UPHY_RST BIT(2)
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+
# define USBDRD_UCTL_CTL_UPHY_RST BIT_ULL(2)
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/* Software reset UAHC */
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-
# define USBDRD_UCTL_CTL_UAHC_RST BIT(1)
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+
# define USBDRD_UCTL_CTL_UAHC_RST BIT_ULL(1)
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/* Software resets UCTL */
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-
# define USBDRD_UCTL_CTL_UCTL_RST BIT(0)
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+
# define USBDRD_UCTL_CTL_UCTL_RST BIT_ULL(0)
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#define USBDRD_UCTL_BIST_STATUS 0x08
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#define USBDRD_UCTL_SPARE0 0x10
···
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*/
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#define USBDRD_UCTL_HOST_CFG 0xe0
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/* Indicates minimum value of all received BELT values */
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-
# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48)
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+
# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK_ULL(59, 48)
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/* HS jitter adjustment */
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-
# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32)
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+
# define USBDRD_UCTL_HOST_CFG_FLA GENMASK_ULL(37, 32)
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/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
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-
# define USBDRD_UCTL_HOST_CFG_BME BIT(28)
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+
# define USBDRD_UCTL_HOST_CFG_BME BIT_ULL(28)
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/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
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-
# define USBDRD_UCTL_HOST_OCI_EN BIT(27)
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+
# define USBDRD_UCTL_HOST_OCI_EN BIT_ULL(27)
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/* Overcurrent sene selection:
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* 0x0 = Overcurrent indication from off-chip is active-low
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* 0x1 = Overcurrent indication from off-chip is active-high
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*/
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-
# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26)
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+
# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT_ULL(26)
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/* Port power control enable: 0x0 = unavailable, 0x1 = available */
146
-
# define USBDRD_UCTL_HOST_PPC_EN BIT(25)
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+
# define USBDRD_UCTL_HOST_PPC_EN BIT_ULL(25)
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/* Port power control sense selection:
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* 0x0 = Port power to off-chip is active-low
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* 0x1 = Port power to off-chip is active-high
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*/
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-
# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24)
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+
# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT_ULL(24)
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/*
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* UCTL Shim Features Register
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*/
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#define USBDRD_UCTL_SHIM_CFG 0xe8
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/* Out-of-bound UAHC register access: 0 = read, 1 = write */
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-
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63)
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+
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT_ULL(63)
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/* SRCID error log for out-of-bound UAHC register access:
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* [59:58] = chipID
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* [57] = Request source: 0 = core, 1 = NCB-device
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* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
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* [50:48] = SubID
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*/
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-
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48)
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+
# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK_ULL(59, 48)
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/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
167
-
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47)
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+
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT_ULL(47)
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168
/* Encoded error type for bad UAHC DMA */
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-
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40)
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+
# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK_ULL(43, 40)
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/* Select the IOI read command used by DMA accesses */
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-
# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12)
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+
# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT_ULL(12)
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/* Select endian format for DMA accesses to the L2C:
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* 0x0 = Little endian
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* 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
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-
# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8)
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+
# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8)
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/* Select endian format for IOI CSR access to UAHC:
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* 0x0 = Little endian
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* 0x1 = Big endian
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* 0x2 = Reserved
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* 0x3 = Reserved
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*/
185
-
# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0)
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+
# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0)
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8