Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: fix function scopes
This turns previously global functions into static, thus removing
compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltage_level'
[-Wmissing-prototypes]
742 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
warning: no previous prototype for 'rv1_vbios_smu_send_msg_with_param'
[-Wmissing-prototypes]
102 | int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Changes since v1:
- As suggested by Rodrigo Siqueira:
1. Rewrite function signatures to make them more readable.
2. Get rid of unused functions in order to remove 'defined but not
used' warnings.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Isabella Basso <isabbasso@riseup.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Isabella Basso
and committed by
Alex Deucher
240e6d25
33c3365e
+179
-517
+12
-6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+12
-6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
632
632
* Copies dmub notification to DM which is to be read by AUX command.
633
633
* issuing thread and also signals the event to wake up the thread.
634
634
*/
635
-
void dmub_aux_setconfig_callback(struct amdgpu_device *adev, struct dmub_notification *notify)
635
+
static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
636
+
struct dmub_notification *notify)
636
637
{
637
638
if (adev->dm.dmub_notify)
638
639
memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
···
649
648
* Dmub Hpd interrupt processing callback. Gets displayindex through the
650
649
* ink index and calls helper to do the processing.
651
650
*/
652
-
void dmub_hpd_callback(struct amdgpu_device *adev, struct dmub_notification *notify)
651
+
static void dmub_hpd_callback(struct amdgpu_device *adev,
652
+
struct dmub_notification *notify)
653
653
{
654
654
struct amdgpu_dm_connector *aconnector;
655
655
struct amdgpu_dm_connector *hpd_aconnector = NULL;
···
707
705
* to dmub interrupt handling thread
708
706
* Return: true if successfully registered, false if there is existing registration
709
707
*/
710
-
bool register_dmub_notify_callback(struct amdgpu_device *adev, enum dmub_notification_type type,
711
-
dmub_notify_interrupt_callback_t callback, bool dmub_int_thread_offload)
708
+
static bool register_dmub_notify_callback(struct amdgpu_device *adev,
709
+
enum dmub_notification_type type,
710
+
dmub_notify_interrupt_callback_t callback,
711
+
bool dmub_int_thread_offload)
712
712
{
713
713
if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
714
714
adev->dm.dmub_callback[type] = callback;
···
11625
11621
return value;
11626
11622
}
11627
11623
11628
-
int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux, struct dc_context *ctx,
11629
-
uint8_t status_type, uint32_t *operation_result)
11624
+
static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux,
11625
+
struct dc_context *ctx,
11626
+
uint8_t status_type,
11627
+
uint32_t *operation_result)
11630
11628
{
11631
11629
struct amdgpu_device *adev = ctx->driver_context;
11632
11630
int return_status = -1;
+3
-1
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+3
-1
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
···
739
739
hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
740
740
}
741
741
742
-
unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)
742
+
static unsigned int get_highest_allowed_voltage_level(uint32_t chip_family,
743
+
uint32_t hw_internal_rev,
744
+
uint32_t pci_revision_id)
743
745
{
744
746
/* for low power RV2 variants, the highest voltage level we want is 0 */
745
747
if ((chip_family == FAMILY_RV) &&
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
···
409
409
clk_mgr->clks.prev_p_state_change_support = true;
410
410
}
411
411
412
-
void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
412
+
static void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
413
413
{
414
414
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
415
415
struct pp_smu_funcs_nv *pp_smu = NULL;
-36
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
-36
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c
···
74
74
CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK)
75
75
};
76
76
77
-
void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr,
78
-
struct dc_state *context,
79
-
bool safe_to_lower)
80
-
{
81
-
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
82
-
83
-
bool update_dppclk = false;
84
-
bool update_dispclk = false;
85
-
86
-
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
87
-
clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
88
-
update_dppclk = true;
89
-
}
90
-
91
-
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
92
-
clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
93
-
update_dispclk = true;
94
-
}
95
-
96
-
if (update_dppclk || update_dispclk) {
97
-
struct bp_set_dce_clock_parameters dce_clk_params;
98
-
struct dc_bios *bp = clk_mgr->ctx->dc_bios;
99
-
100
-
if (update_dispclk) {
101
-
memset(&dce_clk_params, 0, sizeof(dce_clk_params));
102
-
dce_clk_params.target_clock_frequency = new_clocks->dispclk_khz;
103
-
dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
104
-
dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
105
-
bp->funcs->set_dce_clock(bp, &dce_clk_params);
106
-
}
107
-
/* currently there is no DCECLOCK_TYPE_DPPCLK type defined in VBIOS interface.
108
-
* vbios program DPPCLK to the same DispCLK limitation
109
-
*/
110
-
}
111
-
}
112
-
113
77
static void dcn201_init_clocks(struct clk_mgr *clk_mgr)
114
78
{
115
79
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+5
-18
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+5
-18
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
···
56
56
57
57
58
58
/* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
59
-
int rn_get_active_display_cnt_wa(
60
-
struct dc *dc,
61
-
struct dc_state *context)
59
+
static int rn_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context)
62
60
{
63
61
int i, display_count;
64
62
bool tmds_present = false;
···
87
89
return display_count;
88
90
}
89
91
90
-
void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
92
+
static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
91
93
{
92
94
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
93
95
···
121
123
}
122
124
123
125
124
-
void rn_update_clocks(struct clk_mgr *clk_mgr_base,
126
+
static void rn_update_clocks(struct clk_mgr *clk_mgr_base,
125
127
struct dc_state *context,
126
128
bool safe_to_lower)
127
129
{
···
436
438
}
437
439
}
438
440
439
-
/* This function produce translated logical clk state values*/
440
-
void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
441
-
{
442
-
struct clk_state_registers_and_bypass sb = { 0 };
443
-
struct clk_log_info log_info = { 0 };
444
-
445
-
rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
446
-
447
-
s->dprefclk_khz = sb.dprefclk * 1000;
448
-
}
449
-
450
-
void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
441
+
static void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
451
442
{
452
443
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
453
444
454
445
rn_vbios_smu_enable_pme_wa(clk_mgr);
455
446
}
456
447
457
-
void rn_init_clocks(struct clk_mgr *clk_mgr)
448
+
static void rn_init_clocks(struct clk_mgr *clk_mgr)
458
449
{
459
450
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
460
451
// Assumption is that boot state always supports pstate
+3
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+3
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
···
88
88
}
89
89
90
90
91
-
int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
91
+
static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
92
+
unsigned int msg_id,
93
+
unsigned int param)
92
94
{
93
95
uint32_t result;
94
96
+3
-3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+3
-3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
···
88
88
return res_val;
89
89
}
90
90
91
-
int dcn301_smu_send_msg_with_param(
92
-
struct clk_mgr_internal *clk_mgr,
93
-
unsigned int msg_id, unsigned int param)
91
+
static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
92
+
unsigned int msg_id,
93
+
unsigned int param)
94
94
{
95
95
uint32_t result;
96
96
+4
-16
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+4
-16
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
···
89
89
return display_count;
90
90
}
91
91
92
-
void vg_update_clocks(struct clk_mgr *clk_mgr_base,
93
-
struct dc_state *context,
94
-
bool safe_to_lower)
92
+
static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
93
+
struct dc_state *context,
94
+
bool safe_to_lower)
95
95
{
96
96
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
97
97
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
···
367
367
}
368
368
}
369
369
370
-
/* This function produce translated logical clk state values*/
371
-
void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
372
-
{
373
-
374
-
struct clk_state_registers_and_bypass sb = { 0 };
375
-
struct clk_log_info log_info = { 0 };
376
-
377
-
vg_dump_clk_registers(&sb, clk_mgr_base, &log_info);
378
-
379
-
s->dprefclk_khz = sb.dprefclk * 1000;
380
-
}
381
-
382
370
static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
383
371
{
384
372
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
···
374
386
dcn301_smu_enable_pme_wa(clk_mgr);
375
387
}
376
388
377
-
void vg_init_clocks(struct clk_mgr *clk_mgr)
389
+
static void vg_init_clocks(struct clk_mgr *clk_mgr)
378
390
{
379
391
memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
380
392
// Assumption is that boot state always supports pstate
+3
-4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+3
-4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
···
540
540
return clock;
541
541
}
542
542
543
-
void dcn31_clk_mgr_helper_populate_bw_params(
544
-
struct clk_mgr_internal *clk_mgr,
545
-
struct integrated_info *bios_info,
546
-
const DpmClocks_t *clock_table)
543
+
static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
544
+
struct integrated_info *bios_info,
545
+
const DpmClocks_t *clock_table)
547
546
{
548
547
int i, j;
549
548
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
+3
-3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+3
-3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
···
95
95
return res_val;
96
96
}
97
97
98
-
int dcn31_smu_send_msg_with_param(
99
-
struct clk_mgr_internal *clk_mgr,
100
-
unsigned int msg_id, unsigned int param)
98
+
static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
99
+
unsigned int msg_id,
100
+
unsigned int param)
101
101
{
102
102
uint32_t result;
103
103
+2
-1
drivers/gpu/drm/amd/display/dc/core/dc_link.c
+2
-1
drivers/gpu/drm/amd/display/dc/core/dc_link.c
···
3416
3416
/*
3417
3417
* Payload allocation/deallocation for SST introduced in DP2.0
3418
3418
*/
3419
-
enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool allocate)
3419
+
static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3420
+
bool allocate)
3420
3421
{
3421
3422
struct dc_stream_state *stream = pipe_ctx->stream;
3422
3423
struct dc_link *link = stream->link;
-8
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
-8
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
···
119
119
}
120
120
}
121
121
122
-
/* Program gamut remap in bypass mode */
123
-
void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
124
-
{
125
-
REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
126
-
CM_GAMUT_REMAP_MODE, 0);
127
-
/* Gamut remap in bypass */
128
-
}
129
-
130
122
#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
131
123
132
124
bool dpp1_get_optimal_number_of_taps(
-97
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
-97
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
···
89
89
DSCL_MODE_DSCL_BYPASS = 6
90
90
};
91
91
92
-
static void dpp1_dscl_set_overscan(
93
-
struct dcn10_dpp *dpp,
94
-
const struct scaler_data *data)
95
-
{
96
-
uint32_t left = data->recout.x;
97
-
uint32_t top = data->recout.y;
98
-
99
-
int right = data->h_active - data->recout.x - data->recout.width;
100
-
int bottom = data->v_active - data->recout.y - data->recout.height;
101
-
102
-
if (right < 0) {
103
-
BREAK_TO_DEBUGGER();
104
-
right = 0;
105
-
}
106
-
if (bottom < 0) {
107
-
BREAK_TO_DEBUGGER();
108
-
bottom = 0;
109
-
}
110
-
111
-
REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
112
-
EXT_OVERSCAN_LEFT, left,
113
-
EXT_OVERSCAN_RIGHT, right);
114
-
115
-
REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
116
-
EXT_OVERSCAN_BOTTOM, bottom,
117
-
EXT_OVERSCAN_TOP, top);
118
-
}
119
-
120
-
static void dpp1_dscl_set_otg_blank(
121
-
struct dcn10_dpp *dpp, const struct scaler_data *data)
122
-
{
123
-
uint32_t h_blank_start = data->h_active;
124
-
uint32_t h_blank_end = 0;
125
-
uint32_t v_blank_start = data->v_active;
126
-
uint32_t v_blank_end = 0;
127
-
128
-
REG_SET_2(OTG_H_BLANK, 0,
129
-
OTG_H_BLANK_START, h_blank_start,
130
-
OTG_H_BLANK_END, h_blank_end);
131
-
132
-
REG_SET_2(OTG_V_BLANK, 0,
133
-
OTG_V_BLANK_START, v_blank_start,
134
-
OTG_V_BLANK_END, v_blank_end);
135
-
}
136
-
137
92
static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
138
93
{
139
94
if (depth == LB_PIXEL_DEPTH_30BPP)
···
508
553
&& dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
509
554
510
555
return LB_MEMORY_CONFIG_0;
511
-
}
512
-
513
-
void dpp1_dscl_set_scaler_auto_scale(
514
-
struct dpp *dpp_base,
515
-
const struct scaler_data *scl_data)
516
-
{
517
-
enum lb_memory_config lb_config;
518
-
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
519
-
enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
520
-
dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
521
-
bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
522
-
&& scl_data->format <= PIXEL_FORMAT_VIDEO_END;
523
-
524
-
dpp1_dscl_set_overscan(dpp, scl_data);
525
-
526
-
dpp1_dscl_set_otg_blank(dpp, scl_data);
527
-
528
-
REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
529
-
530
-
if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
531
-
return;
532
-
533
-
lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
534
-
dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
535
-
536
-
if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
537
-
return;
538
-
539
-
/* TODO: v_min */
540
-
REG_SET_3(DSCL_AUTOCAL, 0,
541
-
AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
542
-
AUTOCAL_NUM_PIPE, 0,
543
-
AUTOCAL_PIPE_ID, 0);
544
-
545
-
/* Black offsets */
546
-
if (ycbcr)
547
-
REG_SET_2(SCL_BLACK_OFFSET, 0,
548
-
SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
549
-
SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
550
-
else
551
-
552
-
REG_SET_2(SCL_BLACK_OFFSET, 0,
553
-
SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
554
-
SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
555
-
556
-
REG_SET_4(SCL_TAP_CONTROL, 0,
557
-
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
558
-
SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
559
-
SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
560
-
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
561
-
562
-
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
563
556
}
564
557
565
558
+14
-15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+14
-15
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
···
77
77
#define PGFSM_POWER_ON 0
78
78
#define PGFSM_POWER_OFF 2
79
79
80
-
void print_microsec(struct dc_context *dc_ctx,
81
-
struct dc_log_buffer_ctx *log_ctx,
82
-
uint32_t ref_cycle)
80
+
static void print_microsec(struct dc_context *dc_ctx,
81
+
struct dc_log_buffer_ctx *log_ctx,
82
+
uint32_t ref_cycle)
83
83
{
84
84
const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
85
85
static const unsigned int frac = 1000;
···
132
132
REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
133
133
}
134
134
135
-
void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
135
+
static void dcn10_log_hubbub_state(struct dc *dc,
136
+
struct dc_log_buffer_ctx *log_ctx)
136
137
{
137
138
struct dc_context *dc_ctx = dc->ctx;
138
139
struct dcn_hubbub_wm wm;
···
1973
1972
return rc;
1974
1973
}
1975
1974
1976
-
uint64_t reduceSizeAndFraction(
1977
-
uint64_t *numerator,
1978
-
uint64_t *denominator,
1979
-
bool checkUint32Bounary)
1975
+
static uint64_t reduceSizeAndFraction(uint64_t *numerator,
1976
+
uint64_t *denominator,
1977
+
bool checkUint32Bounary)
1980
1978
{
1981
1979
int i;
1982
1980
bool ret = checkUint32Bounary == false;
···
2023
2023
return ret;
2024
2024
}
2025
2025
2026
-
bool is_low_refresh_rate(struct pipe_ctx *pipe)
2026
+
static bool is_low_refresh_rate(struct pipe_ctx *pipe)
2027
2027
{
2028
2028
uint32_t master_pipe_refresh_rate =
2029
2029
pipe->stream->timing.pix_clk_100hz * 100 /
···
2032
2032
return master_pipe_refresh_rate <= 30;
2033
2033
}
2034
2034
2035
-
uint8_t get_clock_divider(struct pipe_ctx *pipe, bool account_low_refresh_rate)
2035
+
static uint8_t get_clock_divider(struct pipe_ctx *pipe,
2036
+
bool account_low_refresh_rate)
2036
2037
{
2037
2038
uint32_t clock_divider = 1;
2038
2039
uint32_t numpipes = 1;
···
2053
2052
return clock_divider;
2054
2053
}
2055
2054
2056
-
int dcn10_align_pixel_clocks(
2057
-
struct dc *dc,
2058
-
int group_size,
2059
-
struct pipe_ctx *grouped_pipes[])
2055
+
static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
2056
+
struct pipe_ctx *grouped_pipes[])
2060
2057
{
2061
2058
struct dc_context *dc_ctx = dc->ctx;
2062
2059
int i, master = -1, embedded = -1;
···
2343
2344
}
2344
2345
2345
2346
2346
-
void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
2347
+
static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
2347
2348
{
2348
2349
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
2349
2350
struct vm_system_aperture_param apt = {0};
-30
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
-30
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
···
348
348
*/
349
349
}
350
350
351
-
void opp1_program_oppbuf(
352
-
struct output_pixel_processor *opp,
353
-
struct oppbuf_params *oppbuf)
354
-
{
355
-
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
356
-
357
-
/* Program the oppbuf active width to be the frame width from mpc */
358
-
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width);
359
-
360
-
/* Specifies the number of segments in multi-segment mode (DP-MSO operation)
361
-
* description "In 1/2/4 segment mode, specifies the horizontal active width in pixels of the display panel.
362
-
* In 4 segment split left/right mode, specifies the horizontal 1/2 active width in pixels of the display panel.
363
-
* Used to determine segment boundaries in multi-segment mode. Used to determine the width of the vertical active space in 3D frame packed modes.
364
-
* OPPBUF_ACTIVE_WIDTH must be integer divisible by the total number of segments."
365
-
*/
366
-
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation);
367
-
368
-
/* description "Specifies the number of overlap pixels (1-8 overlapping pixels supported), used in multi-segment mode (DP-MSO operation)" */
369
-
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num);
370
-
371
-
/* description "Specifies the number of times a pixel is replicated (0-15 pixel replications supported).
372
-
* A value of 0 disables replication. The total number of times a pixel is output is OPPBUF_PIXEL_REPETITION + 1."
373
-
*/
374
-
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
375
-
376
-
/* Controls the number of padded pixels at the end of a segment */
377
-
if (REG(OPPBUF_CONTROL1))
378
-
REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS, oppbuf->num_segment_padded_pixels);
379
-
}
380
-
381
351
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
382
352
{
383
353
struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+2
-18
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+2
-18
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
···
132
132
}
133
133
134
134
/**
135
-
* Vupdate keepout can be set to a window to block the update lock for that pipe from changing.
136
-
* Start offset begins with vstartup and goes for x number of clocks,
137
-
* end offset starts from end of vupdate to x number of clocks.
138
-
*/
139
-
void optc1_set_vupdate_keepout(struct timing_generator *optc,
140
-
struct vupdate_keepout_params *params)
141
-
{
142
-
struct optc *optc1 = DCN10TG_FROM_TG(optc);
143
-
144
-
REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
145
-
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, params->start_offset,
146
-
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, params->end_offset,
147
-
OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, params->enable);
148
-
}
149
-
150
-
/**
151
135
* program_timing_generator used by mode timing set
152
136
* Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
153
137
* Including SYNC. Call BIOS command table to program Timings.
···
860
876
OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
861
877
}
862
878
863
-
void optc1_setup_manual_trigger(struct timing_generator *optc)
879
+
static void optc1_setup_manual_trigger(struct timing_generator *optc)
864
880
{
865
881
struct optc *optc1 = DCN10TG_FROM_TG(optc);
866
882
···
878
894
OTG_TRIGA_CLEAR, 1);
879
895
}
880
896
881
-
void optc1_program_manual_trigger(struct timing_generator *optc)
897
+
static void optc1_program_manual_trigger(struct timing_generator *optc)
882
898
{
883
899
struct optc *optc1 = DCN10TG_FROM_TG(optc);
884
900
+8
-10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+8
-10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
···
686
686
return &opp->base;
687
687
}
688
688
689
-
struct dce_aux *dcn10_aux_engine_create(
690
-
struct dc_context *ctx,
691
-
uint32_t inst)
689
+
static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
690
+
uint32_t inst)
692
691
{
693
692
struct aux_engine_dce110 *aux_engine =
694
693
kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
···
723
724
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
724
725
};
725
726
726
-
struct dce_i2c_hw *dcn10_i2c_hw_create(
727
-
struct dc_context *ctx,
728
-
uint32_t inst)
727
+
static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
728
+
uint32_t inst)
729
729
{
730
730
struct dce_i2c_hw *dce_i2c_hw =
731
731
kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
···
803
805
.flags.bits.IS_TPS4_CAPABLE = true
804
806
};
805
807
806
-
struct link_encoder *dcn10_link_encoder_create(
808
+
static struct link_encoder *dcn10_link_encoder_create(
807
809
const struct encoder_init_data *enc_init_data)
808
810
{
809
811
struct dcn10_link_encoder *enc10 =
···
845
847
return &panel_cntl->base;
846
848
}
847
849
848
-
struct clock_source *dcn10_clock_source_create(
850
+
static struct clock_source *dcn10_clock_source_create(
849
851
struct dc_context *ctx,
850
852
struct dc_bios *bios,
851
853
enum clock_source_id id,
···
943
945
.create_hwseq = dcn10_hwseq_create,
944
946
};
945
947
946
-
void dcn10_clock_source_destroy(struct clock_source **clk_src)
948
+
static void dcn10_clock_source_destroy(struct clock_source **clk_src)
947
949
{
948
950
kfree(TO_DCE110_CLK_SRC(*clk_src));
949
951
*clk_src = NULL;
···
1120
1122
return DC_OK;
1121
1123
}
1122
1124
1123
-
enum dc_status dcn10_add_stream_to_ctx(
1125
+
static enum dc_status dcn10_add_stream_to_ctx(
1124
1126
struct dc *dc,
1125
1127
struct dc_state *new_ctx,
1126
1128
struct dc_stream_state *dc_stream)
-14
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
-14
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
···
251
251
252
252
}
253
253
254
-
void dpp2_cnv_set_bias_scale(
255
-
struct dpp *dpp_base,
256
-
struct dc_bias_and_scale *bias_and_scale)
257
-
{
258
-
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
259
-
260
-
REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
261
-
REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
262
-
REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
263
-
REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
264
-
REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
265
-
REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
266
-
}
267
-
268
254
/*compute the maximum number of lines that we can fit in the line buffer*/
269
255
void dscl2_calc_lb_num_partitions(
270
256
const struct scaler_data *scl_data,
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
···
527
527
0, 84, 16328, 16032, 416, 1944, 1944, 416, 16032, 16328, 84, 0,
528
528
};
529
529
530
-
const uint16_t *wbscl_get_filter_3tap_16p(struct fixed31_32 ratio)
530
+
static const uint16_t *wbscl_get_filter_3tap_16p(struct fixed31_32 ratio)
531
531
{
532
532
if (ratio.value < dc_fixpt_one.value)
533
533
return filter_3tap_16p_upscale;
···
539
539
return filter_3tap_16p_183;
540
540
}
541
541
542
-
const uint16_t *wbscl_get_filter_4tap_16p(struct fixed31_32 ratio)
542
+
static const uint16_t *wbscl_get_filter_4tap_16p(struct fixed31_32 ratio)
543
543
{
544
544
if (ratio.value < dc_fixpt_one.value)
545
545
return filter_4tap_16p_upscale;
+3
-4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+3
-4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
···
192
192
REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
193
193
}
194
194
195
-
void hubp2_program_requestor(
196
-
struct hubp *hubp,
197
-
struct _vcs_dpi_display_rq_regs_st *rq_regs)
195
+
static void hubp2_program_requestor(struct hubp *hubp,
196
+
struct _vcs_dpi_display_rq_regs_st *rq_regs)
198
197
{
199
198
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
200
199
···
1284
1285
1285
1286
}
1286
1287
1287
-
void hubp2_validate_dml_output(struct hubp *hubp,
1288
+
static void hubp2_validate_dml_output(struct hubp *hubp,
1288
1289
struct dc_context *ctx,
1289
1290
struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1290
1291
struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
+2
-4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+2
-4
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
···
1080
1080
}
1081
1081
}
1082
1082
1083
-
void dcn20_enable_plane(
1084
-
struct dc *dc,
1085
-
struct pipe_ctx *pipe_ctx,
1086
-
struct dc_state *context)
1083
+
static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
1084
+
struct dc_state *context)
1087
1085
{
1088
1086
//if (dc->debug.sanity_checks) {
1089
1087
// dcn10_verify_allow_pstate_change_high(dc);
+4
-5
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+4
-5
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
···
400
400
401
401
}
402
402
403
-
void apply_DEDCN20_305_wa(
404
-
struct mpc *mpc,
405
-
int mpcc_id, enum dc_lut_mode current_mode,
406
-
enum dc_lut_mode next_mode)
403
+
static void apply_DEDCN20_305_wa(struct mpc *mpc, int mpcc_id,
404
+
enum dc_lut_mode current_mode,
405
+
enum dc_lut_mode next_mode)
407
406
{
408
407
struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
409
408
···
524
525
mpcc->sm_cfg.enable = false;
525
526
}
526
527
527
-
struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
528
+
static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
528
529
{
529
530
struct mpcc *tmp_mpcc = tree->opp_list;
530
531
+3
-54
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+3
-54
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
···
73
73
}
74
74
75
75
/**
76
-
* DRR double buffering control to select buffer point
77
-
* for V_TOTAL, H_TOTAL, VTOTAL_MIN, VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers
78
-
* Options: anytime, start of frame, dp start of frame (range timing)
79
-
*/
80
-
void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
81
-
{
82
-
struct optc *optc1 = DCN10TG_FROM_TG(optc);
83
-
84
-
uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
85
-
86
-
REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
87
-
OTG_RANGE_TIMING_DBUF_UPDATE_MODE, blank_data_double_buffer_enable);
88
-
}
89
-
90
-
/**
91
76
*For the below, I'm not sure how your GSL parameters are stored in your env,
92
77
* so I will assume a gsl_params struct for now
93
78
*/
···
95
110
}
96
111
97
112
98
-
/* Use the gsl allow flip as the master update lock */
99
-
void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
100
-
const struct gsl_params *params)
101
-
{
102
-
struct optc *optc1 = DCN10TG_FROM_TG(optc);
103
-
104
-
REG_UPDATE(OTG_GSL_CONTROL,
105
-
OTG_MASTER_UPDATE_LOCK_GSL_EN, params->master_update_lock_gsl_en);
106
-
}
107
-
108
-
/* You can control the GSL timing by limiting GSL to a window (X,Y) */
109
-
void optc2_set_gsl_window(struct timing_generator *optc,
110
-
const struct gsl_params *params)
111
-
{
112
-
struct optc *optc1 = DCN10TG_FROM_TG(optc);
113
-
114
-
REG_SET_2(OTG_GSL_WINDOW_X, 0,
115
-
OTG_GSL_WINDOW_START_X, params->gsl_window_start_x,
116
-
OTG_GSL_WINDOW_END_X, params->gsl_window_end_x);
117
-
REG_SET_2(OTG_GSL_WINDOW_Y, 0,
118
-
OTG_GSL_WINDOW_START_Y, params->gsl_window_start_y,
119
-
OTG_GSL_WINDOW_END_Y, params->gsl_window_end_y);
120
-
}
121
-
122
113
void optc2_set_gsl_source_select(
123
114
struct timing_generator *optc,
124
115
int group_idx,
···
115
154
default:
116
155
break;
117
156
}
118
-
}
119
-
120
-
/* DSC encoder frame start controls: x = h position, line_num = # of lines from vstartup */
121
-
void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
122
-
int x_position,
123
-
int line_num)
124
-
{
125
-
struct optc *optc1 = DCN10TG_FROM_TG(optc);
126
-
127
-
REG_SET_2(OTG_DSC_START_POSITION, 0,
128
-
OTG_DSC_START_POSITION_X, x_position,
129
-
OTG_DSC_START_POSITION_LINE_NUM, line_num);
130
157
}
131
158
132
159
/* Set DSC-related configuration.
···
242
293
*num_of_src_opp = 1;
243
294
}
244
295
245
-
void optc2_set_dwb_source(struct timing_generator *optc,
246
-
uint32_t dwb_pipe_inst)
296
+
static void optc2_set_dwb_source(struct timing_generator *optc,
297
+
uint32_t dwb_pipe_inst)
247
298
{
248
299
struct optc *optc1 = DCN10TG_FROM_TG(optc);
249
300
···
255
306
OPTC_DWB1_SOURCE_SELECT, optc->inst);
256
307
}
257
308
258
-
void optc2_align_vblanks(
309
+
static void optc2_align_vblanks(
259
310
struct timing_generator *optc_master,
260
311
struct timing_generator *optc_slave,
261
312
uint32_t master_pixel_clock_100Hz,
+2
-1
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c
+2
-1
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c
+3
-4
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
+3
-4
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c
···
55
55
hubp1_program_pixel_format(hubp, format);
56
56
}
57
57
58
-
void hubp201_program_deadline(
58
+
static void hubp201_program_deadline(
59
59
struct hubp *hubp,
60
60
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
61
61
struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
···
63
63
hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
64
64
}
65
65
66
-
void hubp201_program_requestor(
67
-
struct hubp *hubp,
68
-
struct _vcs_dpi_display_rq_regs_st *rq_regs)
66
+
static void hubp201_program_requestor(struct hubp *hubp,
67
+
struct _vcs_dpi_display_rq_regs_st *rq_regs)
69
68
{
70
69
struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp);
71
70
+3
-3
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
+3
-3
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c
···
50
50
#define IND_REG(index) \
51
51
(enc10->link_regs->index)
52
52
53
-
void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,
54
-
struct dc_link_settings *link_settings)
53
+
static void dcn201_link_encoder_get_max_link_cap(struct link_encoder *enc,
54
+
struct dc_link_settings *link_settings)
55
55
{
56
56
uint32_t value1, value2;
57
57
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
···
66
66
}
67
67
}
68
68
69
-
bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
69
+
static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc)
70
70
{
71
71
uint32_t value;
72
72
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+7
-9
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+7
-9
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
···
672
672
return &opp->base;
673
673
}
674
674
675
-
struct dce_aux *dcn201_aux_engine_create(
676
-
struct dc_context *ctx,
677
-
uint32_t inst)
675
+
static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
676
+
uint32_t inst)
678
677
{
679
678
struct aux_engine_dce110 *aux_engine =
680
679
kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
···
705
706
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
706
707
};
707
708
708
-
struct dce_i2c_hw *dcn201_i2c_hw_create(
709
-
struct dc_context *ctx,
710
-
uint32_t inst)
709
+
static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
710
+
uint32_t inst)
711
711
{
712
712
struct dce_i2c_hw *dce_i2c_hw =
713
713
kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
···
787
789
.flags.bits.IS_TPS4_CAPABLE = true
788
790
};
789
791
790
-
struct link_encoder *dcn201_link_encoder_create(
792
+
static struct link_encoder *dcn201_link_encoder_create(
791
793
const struct encoder_init_data *enc_init_data)
792
794
{
793
795
struct dcn20_link_encoder *enc20 =
···
809
811
return &enc10->base;
810
812
}
811
813
812
-
struct clock_source *dcn201_clock_source_create(
814
+
static struct clock_source *dcn201_clock_source_create(
813
815
struct dc_context *ctx,
814
816
struct dc_bios *bios,
815
817
enum clock_source_id id,
···
904
906
.create_hwseq = dcn201_hwseq_create,
905
907
};
906
908
907
-
void dcn201_clock_source_destroy(struct clock_source **clk_src)
909
+
static void dcn201_clock_source_destroy(struct clock_source **clk_src)
908
910
{
909
911
kfree(TO_DCE110_CLK_SRC(*clk_src));
910
912
*clk_src = NULL;
+1
-1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
···
680
680
DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
681
681
}
682
682
683
-
void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
683
+
static void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
684
684
{
685
685
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
686
686
uint32_t prog_wm_value;
+8
-7
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+8
-7
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
···
183
183
184
184
}
185
185
186
-
void hubp21_set_viewport(
186
+
static void hubp21_set_viewport(
187
187
struct hubp *hubp,
188
188
const struct rect *viewport,
189
189
const struct rect *viewport_c)
···
225
225
SEC_VIEWPORT_Y_START_C, viewport_c->y);
226
226
}
227
227
228
-
void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
229
-
struct vm_system_aperture_param *apt)
228
+
static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
229
+
struct vm_system_aperture_param *apt)
230
230
{
231
231
struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
232
232
···
248
248
SYSTEM_ACCESS_MODE, 0x3);
249
249
}
250
250
251
-
void hubp21_validate_dml_output(struct hubp *hubp,
251
+
static void hubp21_validate_dml_output(struct hubp *hubp,
252
252
struct dc_context *ctx,
253
253
struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
254
254
struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
···
664
664
flip_regs->DCSURF_PRIMARY_SURFACE_ADDRESS);
665
665
}
666
666
667
-
void dmcub_PLAT_54186_wa(struct hubp *hubp, struct surface_flip_registers *flip_regs)
667
+
static void dmcub_PLAT_54186_wa(struct hubp *hubp,
668
+
struct surface_flip_registers *flip_regs)
668
669
{
669
670
struct dc_dmub_srv *dmcub = hubp->ctx->dmub_srv;
670
671
struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
···
698
697
PERF_TRACE(); // TODO: remove after performance is stable.
699
698
}
700
699
701
-
bool hubp21_program_surface_flip_and_addr(
700
+
static bool hubp21_program_surface_flip_and_addr(
702
701
struct hubp *hubp,
703
702
const struct dc_plane_address *address,
704
703
bool flip_immediate)
···
806
805
return true;
807
806
}
808
807
809
-
void hubp21_init(struct hubp *hubp)
808
+
static void hubp21_init(struct hubp *hubp)
810
809
{
811
810
// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
812
811
// This is a chicken bit to enable the ECO fix.
+4
-5
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+4
-5
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
···
203
203
return true;
204
204
}
205
205
206
-
bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
206
+
static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
207
207
{
208
208
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
209
209
int value;
···
277
277
278
278
}
279
279
280
-
void dcn21_link_encoder_enable_dp_mst_output(
280
+
static void dcn21_link_encoder_enable_dp_mst_output(
281
281
struct link_encoder *enc,
282
282
const struct dc_link_settings *link_settings,
283
283
enum clock_source_id clock_source)
···
288
288
dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
289
289
}
290
290
291
-
void dcn21_link_encoder_disable_output(
292
-
struct link_encoder *enc,
293
-
enum signal_type signal)
291
+
static void dcn21_link_encoder_disable_output(struct link_encoder *enc,
292
+
enum signal_type signal)
294
293
{
295
294
dcn10_link_encoder_disable_output(enc, signal);
296
295
+14
-17
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+14
-17
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
···
784
784
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
785
785
};
786
786
787
-
struct dce_i2c_hw *dcn21_i2c_hw_create(
788
-
struct dc_context *ctx,
789
-
uint32_t inst)
787
+
static struct dce_i2c_hw *dcn21_i2c_hw_create(struct dc_context *ctx,
788
+
uint32_t inst)
790
789
{
791
790
struct dce_i2c_hw *dce_i2c_hw =
792
791
kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
···
1092
1093
}
1093
1094
}
1094
1095
1095
-
void dcn21_calculate_wm(
1096
+
static void dcn21_calculate_wm(
1096
1097
struct dc *dc, struct dc_state *context,
1097
1098
display_e2e_pipe_params_st *pipes,
1098
1099
int *out_pipe_cnt,
···
1389
1390
* with DC_FP_START()/DC_FP_END(). Use the same approach as for
1390
1391
* dcn20_validate_bandwidth in dcn20_resource.c.
1391
1392
*/
1392
-
bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1393
+
static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1393
1394
bool fast_validate)
1394
1395
{
1395
1396
bool voltage_supported;
···
1479
1480
return &hubbub->base;
1480
1481
}
1481
1482
1482
-
struct output_pixel_processor *dcn21_opp_create(
1483
-
struct dc_context *ctx, uint32_t inst)
1483
+
static struct output_pixel_processor *dcn21_opp_create(struct dc_context *ctx,
1484
+
uint32_t inst)
1484
1485
{
1485
1486
struct dcn20_opp *opp =
1486
1487
kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
···
1495
1496
return &opp->base;
1496
1497
}
1497
1498
1498
-
struct timing_generator *dcn21_timing_generator_create(
1499
-
struct dc_context *ctx,
1500
-
uint32_t instance)
1499
+
static struct timing_generator *dcn21_timing_generator_create(struct dc_context *ctx,
1500
+
uint32_t instance)
1501
1501
{
1502
1502
struct optc *tgn10 =
1503
1503
kzalloc(sizeof(struct optc), GFP_KERNEL);
···
1516
1518
return &tgn10->base;
1517
1519
}
1518
1520
1519
-
struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1521
+
static struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1520
1522
{
1521
1523
struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1522
1524
GFP_KERNEL);
···
1543
1545
}
1544
1546
1545
1547
1546
-
struct display_stream_compressor *dcn21_dsc_create(
1547
-
struct dc_context *ctx, uint32_t inst)
1548
+
static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx,
1549
+
uint32_t inst)
1548
1550
{
1549
1551
struct dcn20_dsc *dsc =
1550
1552
kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
···
1681
1683
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1682
1684
};
1683
1685
1684
-
struct stream_encoder *dcn21_stream_encoder_create(
1685
-
enum engine_id eng_id,
1686
-
struct dc_context *ctx)
1686
+
static struct stream_encoder *dcn21_stream_encoder_create(enum engine_id eng_id,
1687
+
struct dc_context *ctx)
1687
1688
{
1688
1689
struct dcn10_stream_encoder *enc1 =
1689
1690
kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
···
1914
1917
return pipe_cnt;
1915
1918
}
1916
1919
1917
-
enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1920
+
static enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1918
1921
{
1919
1922
enum dc_status result = DC_OK;
1920
1923
+1
-17
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
+1
-17
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
···
50
50
enc1->base.ctx
51
51
52
52
53
-
void convert_dc_info_packet_to_128(
54
-
const struct dc_info_packet *info_packet,
55
-
struct dc_info_packet_128 *info_packet_128)
56
-
{
57
-
unsigned int i;
58
-
59
-
info_packet_128->hb0 = info_packet->hb0;
60
-
info_packet_128->hb1 = info_packet->hb1;
61
-
info_packet_128->hb2 = info_packet->hb2;
62
-
info_packet_128->hb3 = info_packet->hb3;
63
-
64
-
for (i = 0; i < 32; i++) {
65
-
info_packet_128->sb[i] = info_packet->sb[i];
66
-
}
67
-
68
-
}
69
53
static void enc3_update_hdmi_info_packet(
70
54
struct dcn10_stream_encoder *enc1,
71
55
uint32_t packet_index,
···
473
489
}
474
490
475
491
/* setup stream encoder in dvi mode */
476
-
void enc3_stream_encoder_dvi_set_stream_attribute(
492
+
static void enc3_stream_encoder_dvi_set_stream_attribute(
477
493
struct stream_encoder *enc,
478
494
struct dc_crtc_timing *crtc_timing,
479
495
bool is_dual_link)
+9
-27
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+9
-27
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
···
41
41
dpp->tf_shift->field_name, dpp->tf_mask->field_name
42
42
43
43
44
-
void dpp30_read_state(struct dpp *dpp_base,
45
-
struct dcn_dpp_state *s)
44
+
static void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
46
45
{
47
46
struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
48
47
···
372
373
}
373
374
374
375
375
-
bool dpp3_get_optimal_number_of_taps(
376
+
static bool dpp3_get_optimal_number_of_taps(
376
377
struct dpp *dpp,
377
378
struct scaler_data *scl_data,
378
379
const struct scaling_taps *in_taps)
···
473
474
return true;
474
475
}
475
476
476
-
void dpp3_cnv_set_bias_scale(
477
-
struct dpp *dpp_base,
478
-
struct dc_bias_and_scale *bias_and_scale)
479
-
{
480
-
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
481
-
482
-
REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red);
483
-
REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green);
484
-
REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue);
485
-
REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red);
486
-
REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green);
487
-
REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue);
488
-
}
489
-
490
-
void dpp3_deferred_update(
491
-
struct dpp *dpp_base)
477
+
static void dpp3_deferred_update(struct dpp *dpp_base)
492
478
{
493
479
int bypass_state;
494
480
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
···
735
751
return mode;
736
752
}
737
753
738
-
bool dpp3_program_blnd_lut(
739
-
struct dpp *dpp_base, const struct pwl_params *params)
754
+
static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
755
+
const struct pwl_params *params)
740
756
{
741
757
enum dc_lut_mode current_mode;
742
758
enum dc_lut_mode next_mode;
···
1148
1164
}
1149
1165
1150
1166
1151
-
bool dpp3_program_shaper(
1152
-
struct dpp *dpp_base,
1153
-
const struct pwl_params *params)
1167
+
static bool dpp3_program_shaper(struct dpp *dpp_base,
1168
+
const struct pwl_params *params)
1154
1169
{
1155
1170
enum dc_lut_mode current_mode;
1156
1171
enum dc_lut_mode next_mode;
···
1338
1355
REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);
1339
1356
}
1340
1357
1341
-
bool dpp3_program_3dlut(
1342
-
struct dpp *dpp_base,
1343
-
struct tetrahedral_params *params)
1358
+
static bool dpp3_program_3dlut(struct dpp *dpp_base,
1359
+
struct tetrahedral_params *params)
1344
1360
{
1345
1361
enum dc_lut_mode mode;
1346
1362
bool is_17x17x17;
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
···
100
100
REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);
101
101
}
102
102
103
-
void mmhubbub3_config_mcif_buf(struct mcif_wb *mcif_wb,
103
+
static void mmhubbub3_config_mcif_buf(struct mcif_wb *mcif_wb,
104
104
struct mcif_buf_params *params,
105
105
unsigned int dest_height)
106
106
{
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+5
-7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+5
-7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
···
875
875
.use_max_lb = true
876
876
};
877
877
878
-
void dcn30_dpp_destroy(struct dpp **dpp)
878
+
static void dcn30_dpp_destroy(struct dpp **dpp)
879
879
{
880
880
kfree(TO_DCN20_DPP(*dpp));
881
881
*dpp = NULL;
···
992
992
return &mpc30->base;
993
993
}
994
994
995
-
struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
995
+
static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
996
996
{
997
997
int i;
998
998
···
1143
1143
return &afmt3->base;
1144
1144
}
1145
1145
1146
-
struct stream_encoder *dcn30_stream_encoder_create(
1147
-
enum engine_id eng_id,
1148
-
struct dc_context *ctx)
1146
+
static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1147
+
struct dc_context *ctx)
1149
1148
{
1150
1149
struct dcn10_stream_encoder *enc1;
1151
1150
struct vpg *vpg;
···
1178
1179
return &enc1->base;
1179
1180
}
1180
1181
1181
-
struct dce_hwseq *dcn30_hwseq_create(
1182
-
struct dc_context *ctx)
1182
+
static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1183
1183
{
1184
1184
struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1185
1185
+5
-5
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
+5
-5
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
···
93
93
return (uint32_t)(current_backlight);
94
94
}
95
95
96
-
uint32_t dcn301_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
96
+
static uint32_t dcn301_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
97
97
{
98
98
struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
99
99
uint32_t value;
···
147
147
return current_backlight;
148
148
}
149
149
150
-
void dcn301_panel_cntl_destroy(struct panel_cntl **panel_cntl)
150
+
static void dcn301_panel_cntl_destroy(struct panel_cntl **panel_cntl)
151
151
{
152
152
struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(*panel_cntl);
153
153
···
155
155
*panel_cntl = NULL;
156
156
}
157
157
158
-
bool dcn301_is_panel_backlight_on(struct panel_cntl *panel_cntl)
158
+
static bool dcn301_is_panel_backlight_on(struct panel_cntl *panel_cntl)
159
159
{
160
160
struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
161
161
uint32_t value;
···
165
165
return value;
166
166
}
167
167
168
-
bool dcn301_is_panel_powered_on(struct panel_cntl *panel_cntl)
168
+
static bool dcn301_is_panel_powered_on(struct panel_cntl *panel_cntl)
169
169
{
170
170
struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
171
171
uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
···
177
177
return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
178
178
}
179
179
180
-
void dcn301_store_backlight_level(struct panel_cntl *panel_cntl)
180
+
static void dcn301_store_backlight_level(struct panel_cntl *panel_cntl)
181
181
{
182
182
struct dcn301_panel_cntl *dcn301_panel_cntl = TO_DCN301_PANEL_CNTL(panel_cntl);
183
183
+17
-28
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+17
-28
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
···
717
717
.use_max_lb = false,
718
718
};
719
719
720
-
void dcn301_dpp_destroy(struct dpp **dpp)
720
+
static void dcn301_dpp_destroy(struct dpp **dpp)
721
721
{
722
722
kfree(TO_DCN20_DPP(*dpp));
723
723
*dpp = NULL;
724
724
}
725
725
726
-
struct dpp *dcn301_dpp_create(
727
-
struct dc_context *ctx,
728
-
uint32_t inst)
726
+
static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
729
727
{
730
728
struct dcn3_dpp *dpp =
731
729
kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
···
739
741
kfree(dpp);
740
742
return NULL;
741
743
}
742
-
struct output_pixel_processor *dcn301_opp_create(
743
-
struct dc_context *ctx, uint32_t inst)
744
+
static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
745
+
uint32_t inst)
744
746
{
745
747
struct dcn20_opp *opp =
746
748
kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
···
755
757
return &opp->base;
756
758
}
757
759
758
-
struct dce_aux *dcn301_aux_engine_create(
759
-
struct dc_context *ctx,
760
-
uint32_t inst)
760
+
static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
761
761
{
762
762
struct aux_engine_dce110 *aux_engine =
763
763
kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
···
789
793
I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
790
794
};
791
795
792
-
struct dce_i2c_hw *dcn301_i2c_hw_create(
793
-
struct dc_context *ctx,
794
-
uint32_t inst)
796
+
static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
795
797
{
796
798
struct dce_i2c_hw *dce_i2c_hw =
797
799
kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
···
823
829
return &mpc30->base;
824
830
}
825
831
826
-
struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
832
+
static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
827
833
{
828
834
int i;
829
835
···
854
860
return &hubbub3->base;
855
861
}
856
862
857
-
struct timing_generator *dcn301_timing_generator_create(
858
-
struct dc_context *ctx,
859
-
uint32_t instance)
863
+
static struct timing_generator *dcn301_timing_generator_create(
864
+
struct dc_context *ctx, uint32_t instance)
860
865
{
861
866
struct optc *tgn10 =
862
867
kzalloc(sizeof(struct optc), GFP_KERNEL);
···
887
894
.flags.bits.IS_TPS4_CAPABLE = true
888
895
};
889
896
890
-
struct link_encoder *dcn301_link_encoder_create(
897
+
static struct link_encoder *dcn301_link_encoder_create(
891
898
const struct encoder_init_data *enc_init_data)
892
899
{
893
900
struct dcn20_link_encoder *enc20 =
···
908
915
return &enc20->enc10.base;
909
916
}
910
917
911
-
struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
918
+
static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
912
919
{
913
920
struct dcn301_panel_cntl *panel_cntl =
914
921
kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
···
990
997
return &afmt3->base;
991
998
}
992
999
993
-
struct stream_encoder *dcn301_stream_encoder_create(
994
-
enum engine_id eng_id,
995
-
struct dc_context *ctx)
1000
+
static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
1001
+
struct dc_context *ctx)
996
1002
{
997
1003
struct dcn10_stream_encoder *enc1;
998
1004
struct vpg *vpg;
···
1025
1033
return &enc1->base;
1026
1034
}
1027
1035
1028
-
struct dce_hwseq *dcn301_hwseq_create(
1029
-
struct dc_context *ctx)
1036
+
static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1030
1037
{
1031
1038
struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1032
1039
···
1173
1182
dcn_dccg_destroy(&pool->base.dccg);
1174
1183
}
1175
1184
1176
-
struct hubp *dcn301_hubp_create(
1177
-
struct dc_context *ctx,
1178
-
uint32_t inst)
1185
+
static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1179
1186
{
1180
1187
struct dcn20_hubp *hubp2 =
1181
1188
kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
···
1190
1201
return NULL;
1191
1202
}
1192
1203
1193
-
bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1204
+
static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1194
1205
{
1195
1206
int i;
1196
1207
uint32_t pipe_count = pool->res_cap->num_dwb;
···
1215
1226
return true;
1216
1227
}
1217
1228
1218
-
bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1229
+
static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1219
1230
{
1220
1231
int i;
1221
1232
uint32_t pipe_count = pool->res_cap->num_dwb;
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+5
-5
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+5
-5
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
···
65
65
return cmd.panel_cntl.data.current_backlight;
66
66
}
67
67
68
-
uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
68
+
static uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
69
69
{
70
70
struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
71
71
struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
···
96
96
return cmd.panel_cntl.data.current_backlight;
97
97
}
98
98
99
-
void dcn31_panel_cntl_destroy(struct panel_cntl **panel_cntl)
99
+
static void dcn31_panel_cntl_destroy(struct panel_cntl **panel_cntl)
100
100
{
101
101
struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(*panel_cntl);
102
102
···
104
104
*panel_cntl = NULL;
105
105
}
106
106
107
-
bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl)
107
+
static bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl)
108
108
{
109
109
union dmub_rb_cmd cmd;
110
110
···
114
114
return cmd.panel_cntl.data.is_backlight_on;
115
115
}
116
116
117
-
bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl)
117
+
static bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl)
118
118
{
119
119
union dmub_rb_cmd cmd;
120
120
···
124
124
return cmd.panel_cntl.data.is_powered_on;
125
125
}
126
126
127
-
void dcn31_store_backlight_level(struct panel_cntl *panel_cntl)
127
+
static void dcn31_store_backlight_level(struct panel_cntl *panel_cntl)
128
128
{
129
129
union dmub_rb_cmd cmd;
130
130
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
···
1272
1272
return &enc20->enc10.base;
1273
1273
}
1274
1274
1275
-
struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1275
+
static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1276
1276
{
1277
1277
struct dcn31_panel_cntl *panel_cntl =
1278
1278
kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
-8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
-8
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
···
1711
1711
dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1712
1712
}
1713
1713
1714
-
void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
1715
-
{
1716
-
memset(arb_param, 0, sizeof(*arb_param));
1717
-
arb_param->max_req_outstanding = 256;
1718
-
arb_param->min_req_outstanding = 68;
1719
-
arb_param->sat_level_us = 60;
1720
-
}
1721
-
1722
1714
static void calculate_ttu_cursor(
1723
1715
struct display_mode_lib *mode_lib,
1724
1716
double *refcyc_per_req_delivery_pre_cur,
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
···
40
40
41
41
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
42
43
-
enum dc_irq_source to_dal_irq_source_dcn10(
44
-
struct irq_service *irq_service,
45
-
uint32_t src_id,
46
-
uint32_t ext_id)
43
+
static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_service,
44
+
uint32_t src_id,
45
+
uint32_t ext_id)
47
46
{
48
47
switch (src_id) {
49
48
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
···
39
39
40
40
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
41
41
42
-
enum dc_irq_source to_dal_irq_source_dcn201(
43
-
struct irq_service *irq_service,
44
-
uint32_t src_id,
45
-
uint32_t ext_id)
42
+
static enum dc_irq_source to_dal_irq_source_dcn201(struct irq_service *irq_service,
43
+
uint32_t src_id,
44
+
uint32_t ext_id)
46
45
{
47
46
switch (src_id) {
48
47
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
···
40
40
41
41
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
42
43
-
enum dc_irq_source to_dal_irq_source_dcn21(
44
-
struct irq_service *irq_service,
45
-
uint32_t src_id,
46
-
uint32_t ext_id)
43
+
static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_service,
44
+
uint32_t src_id,
45
+
uint32_t ext_id)
47
46
{
48
47
switch (src_id) {
49
48
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
+3
-4
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
···
36
36
37
37
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
38
38
39
-
enum dc_irq_source to_dal_irq_source_dcn31(
40
-
struct irq_service *irq_service,
41
-
uint32_t src_id,
42
-
uint32_t ext_id)
39
+
static enum dc_irq_source to_dal_irq_source_dcn31(struct irq_service *irq_service,
40
+
uint32_t src_id,
41
+
uint32_t ext_id)
43
42
{
44
43
switch (src_id) {
45
44
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: