drm/amd/display: Reduce stack size for dml31 UseMinimumDCFCLK

+69 -235

1 changed file

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drivers

gpu

drm

amd

display

dml

dcn31

display_mode_vba_31.c

+69 -235

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c

··· 422 422 423 423 static void UseMinimumDCFCLK( 424 424 struct display_mode_lib *mode_lib, 425 - int MaxInterDCNTileRepeaters, 426 425 int MaxPrefetchMode, 427 - double FinalDRAMClockChangeLatency, 428 - double SREnterPlusExitTime, 429 - int ReturnBusWidth, 430 - int RoundTripPingLatencyCycles, 431 - int ReorderingBytes, 432 - int PixelChunkSizeInKByte, 433 - int MetaChunkSize, 434 - bool GPUVMEnable, 435 - int GPUVMMaxPageTableLevels, 436 - bool HostVMEnable, 437 - int NumberOfActivePlanes, 438 - double HostVMMinPageSize, 439 - int HostVMMaxNonCachedPageTableLevels, 440 - bool DynamicMetadataVMEnabled, 441 - enum immediate_flip_requirement ImmediateFlipRequirement, 442 - bool ProgressiveToInterlaceUnitInOPP, 443 - double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, 444 - double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, 445 - int VTotal[], 446 - int VActive[], 447 - int DynamicMetadataTransmittedBytes[], 448 - int DynamicMetadataLinesBeforeActiveRequired[], 449 - bool Interlace[], 450 - double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], 451 - double RequiredDISPCLK[][2], 452 - double UrgLatency[], 453 - unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], 454 - double ProjectedDCFCLKDeepSleep[][2], 455 - double MaximumVStartup[][2][DC__NUM_DPP__MAX], 456 - double TotalVActivePixelBandwidth[][2], 457 - double TotalVActiveCursorBandwidth[][2], 458 - double TotalMetaRowBandwidth[][2], 459 - double TotalDPTERowBandwidth[][2], 460 - unsigned int TotalNumberOfActiveDPP[][2], 461 - unsigned int TotalNumberOfDCCActiveDPP[][2], 462 - int dpte_group_bytes[], 463 - double PrefetchLinesY[][2][DC__NUM_DPP__MAX], 464 - double PrefetchLinesC[][2][DC__NUM_DPP__MAX], 465 - int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], 466 - int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], 467 - int BytePerPixelY[], 468 - int BytePerPixelC[], 469 - int HTotal[], 470 - double PixelClock[], 471 - double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], 472 - double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], 473 - double MetaRowBytes[][2][DC__NUM_DPP__MAX], 474 - bool DynamicMetadataEnable[], 475 - double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], 476 - double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], 477 - double ReadBandwidthLuma[], 478 - double ReadBandwidthChroma[], 479 - double DCFCLKPerState[], 480 - double DCFCLKState[][2]); 426 + int ReorderingBytes); 481 427 482 428 static void CalculatePixelDeliveryTimes( 483 429 unsigned int NumberOfActivePlanes, ··· 5121 5175 } 5122 5176 } 5123 5177 5124 - if (v->UseMinimumRequiredDCFCLK == true) { 5125 - UseMinimumDCFCLK( 5126 - mode_lib, 5127 - v->MaxInterDCNTileRepeaters, 5128 - MaxPrefetchMode, 5129 - v->DRAMClockChangeLatency, 5130 - v->SREnterPlusExitTime, 5131 - v->ReturnBusWidth, 5132 - v->RoundTripPingLatencyCycles, 5133 - ReorderingBytes, 5134 - v->PixelChunkSizeInKByte, 5135 - v->MetaChunkSize, 5136 - v->GPUVMEnable, 5137 - v->GPUVMMaxPageTableLevels, 5138 - v->HostVMEnable, 5139 - v->NumberOfActivePlanes, 5140 - v->HostVMMinPageSize, 5141 - v->HostVMMaxNonCachedPageTableLevels, 5142 - v->DynamicMetadataVMEnabled, 5143 - v->ImmediateFlipRequirement[0], 5144 - v->ProgressiveToInterlaceUnitInOPP, 5145 - v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, 5146 - v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, 5147 - v->VTotal, 5148 - v->VActive, 5149 - v->DynamicMetadataTransmittedBytes, 5150 - v->DynamicMetadataLinesBeforeActiveRequired, 5151 - v->Interlace, 5152 - v->RequiredDPPCLK, 5153 - v->RequiredDISPCLK, 5154 - v->UrgLatency, 5155 - v->NoOfDPP, 5156 - v->ProjectedDCFCLKDeepSleep, 5157 - v->MaximumVStartup, 5158 - v->TotalVActivePixelBandwidth, 5159 - v->TotalVActiveCursorBandwidth, 5160 - v->TotalMetaRowBandwidth, 5161 - v->TotalDPTERowBandwidth, 5162 - v->TotalNumberOfActiveDPP, 5163 - v->TotalNumberOfDCCActiveDPP, 5164 - v->dpte_group_bytes, 5165 - v->PrefetchLinesY, 5166 - v->PrefetchLinesC, 5167 - v->swath_width_luma_ub_all_states, 5168 - v->swath_width_chroma_ub_all_states, 5169 - v->BytePerPixelY, 5170 - v->BytePerPixelC, 5171 - v->HTotal, 5172 - v->PixelClock, 5173 - v->PDEAndMetaPTEBytesPerFrame, 5174 - v->DPTEBytesPerRow, 5175 - v->MetaRowBytes, 5176 - v->DynamicMetadataEnable, 5177 - v->VActivePixelBandwidth, 5178 - v->VActiveCursorBandwidth, 5179 - v->ReadBandwidthLuma, 5180 - v->ReadBandwidthChroma, 5181 - v->DCFCLKPerState, 5182 - v->DCFCLKState); 5183 - } 5178 + if (v->UseMinimumRequiredDCFCLK == true) 5179 + UseMinimumDCFCLK(mode_lib, MaxPrefetchMode, ReorderingBytes); 5184 5180 5185 5181 for (i = 0; i < v->soc.num_states; ++i) { 5186 5182 for (j = 0; j <= 1; ++j) { ··· 7150 7262 7151 7263 static void UseMinimumDCFCLK( 7152 7264 struct display_mode_lib *mode_lib, 7153 - int MaxInterDCNTileRepeaters, 7154 7265 int MaxPrefetchMode, 7155 - double FinalDRAMClockChangeLatency, 7156 - double SREnterPlusExitTime, 7157 - int ReturnBusWidth, 7158 - int RoundTripPingLatencyCycles, 7159 - int ReorderingBytes, 7160 - int PixelChunkSizeInKByte, 7161 - int MetaChunkSize, 7162 - bool GPUVMEnable, 7163 - int GPUVMMaxPageTableLevels, 7164 - bool HostVMEnable, 7165 - int NumberOfActivePlanes, 7166 - double HostVMMinPageSize, 7167 - int HostVMMaxNonCachedPageTableLevels, 7168 - bool DynamicMetadataVMEnabled, 7169 - enum immediate_flip_requirement ImmediateFlipRequirement, 7170 - bool ProgressiveToInterlaceUnitInOPP, 7171 - double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation, 7172 - double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency, 7173 - int VTotal[], 7174 - int VActive[], 7175 - int DynamicMetadataTransmittedBytes[], 7176 - int DynamicMetadataLinesBeforeActiveRequired[], 7177 - bool Interlace[], 7178 - double RequiredDPPCLK[][2][DC__NUM_DPP__MAX], 7179 - double RequiredDISPCLK[][2], 7180 - double UrgLatency[], 7181 - unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], 7182 - double ProjectedDCFCLKDeepSleep[][2], 7183 - double MaximumVStartup[][2][DC__NUM_DPP__MAX], 7184 - double TotalVActivePixelBandwidth[][2], 7185 - double TotalVActiveCursorBandwidth[][2], 7186 - double TotalMetaRowBandwidth[][2], 7187 - double TotalDPTERowBandwidth[][2], 7188 - unsigned int TotalNumberOfActiveDPP[][2], 7189 - unsigned int TotalNumberOfDCCActiveDPP[][2], 7190 - int dpte_group_bytes[], 7191 - double PrefetchLinesY[][2][DC__NUM_DPP__MAX], 7192 - double PrefetchLinesC[][2][DC__NUM_DPP__MAX], 7193 - int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], 7194 - int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], 7195 - int BytePerPixelY[], 7196 - int BytePerPixelC[], 7197 - int HTotal[], 7198 - double PixelClock[], 7199 - double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], 7200 - double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], 7201 - double MetaRowBytes[][2][DC__NUM_DPP__MAX], 7202 - bool DynamicMetadataEnable[], 7203 - double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX], 7204 - double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX], 7205 - double ReadBandwidthLuma[], 7206 - double ReadBandwidthChroma[], 7207 - double DCFCLKPerState[], 7208 - double DCFCLKState[][2]) 7266 + int ReorderingBytes) 7209 7267 { 7210 7268 struct vba_vars_st *v = &mode_lib->vba; 7211 7269 int dummy1, i, j, k; 7212 7270 double NormalEfficiency, dummy2, dummy3; 7213 7271 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; 7214 7272 7215 - NormalEfficiency = PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; 7273 + NormalEfficiency = v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0; 7216 7274 for (i = 0; i < v->soc.num_states; ++i) { 7217 7275 for (j = 0; j <= 1; ++j) { 7218 7276 double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; ··· 7176 7342 double MinimumTvmPlus2Tr0; 7177 7343 7178 7344 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; 7179 - for (k = 0; k < NumberOfActivePlanes; ++k) { 7345 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 7180 7346 TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j] 7181 - + NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]); 7347 + + v->NoOfDPP[i][j][k] * v->DPTEBytesPerRow[i][j][k] / (15.75 * v->HTotal[k] / v->PixelClock[k]); 7182 7348 } 7183 7349 7184 - for (k = 0; k <= NumberOfActivePlanes - 1; ++k) { 7185 - NoOfDPPState[k] = NoOfDPP[i][j][k]; 7350 + for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { 7351 + NoOfDPPState[k] = v->NoOfDPP[i][j][k]; 7186 7352 } 7187 7353 7188 - MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime); 7189 - NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j]; 7190 - DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ? 7191 - TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j]; 7354 + MinimumTWait = CalculateTWait(MaxPrefetchMode, v->FinalDRAMClockChangeLatency, v->UrgLatency[i], v->SREnterPlusExitTime); 7355 + NonDPTEBandwidth = v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]; 7356 + DPTEBandwidth = (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) ? 7357 + TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : v->TotalDPTERowBandwidth[i][j]; 7192 7358 DCFCLKRequiredForAverageBandwidth = dml_max3( 7193 - ProjectedDCFCLKDeepSleep[i][j], 7194 - (NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth 7195 - / (MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100), 7196 - (NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / ReturnBusWidth); 7359 + v->ProjectedDCFCLKDeepSleep[i][j], 7360 + (NonDPTEBandwidth + v->TotalDPTERowBandwidth[i][j]) / v->ReturnBusWidth 7361 + / (v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100), 7362 + (NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / v->ReturnBusWidth); 7197 7363 7198 7364 ExtraLatencyBytes = CalculateExtraLatencyBytes( 7199 7365 ReorderingBytes, 7200 - TotalNumberOfActiveDPP[i][j], 7201 - PixelChunkSizeInKByte, 7202 - TotalNumberOfDCCActiveDPP[i][j], 7203 - MetaChunkSize, 7204 - GPUVMEnable, 7205 - HostVMEnable, 7206 - NumberOfActivePlanes, 7366 + v->TotalNumberOfActiveDPP[i][j], 7367 + v->PixelChunkSizeInKByte, 7368 + v->TotalNumberOfDCCActiveDPP[i][j], 7369 + v->MetaChunkSize, 7370 + v->GPUVMEnable, 7371 + v->HostVMEnable, 7372 + v->NumberOfActivePlanes, 7207 7373 NoOfDPPState, 7208 - dpte_group_bytes, 7374 + v->dpte_group_bytes, 7209 7375 1, 7210 - HostVMMinPageSize, 7211 - HostVMMaxNonCachedPageTableLevels); 7212 - ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth; 7213 - for (k = 0; k < NumberOfActivePlanes; ++k) { 7376 + v->HostVMMinPageSize, 7377 + v->HostVMMaxNonCachedPageTableLevels); 7378 + ExtraLatencyCycles = v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / v->ReturnBusWidth; 7379 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 7214 7380 double DCFCLKCyclesRequiredInPrefetch; 7215 7381 double ExpectedPrefetchBWAcceleration; 7216 7382 double PrefetchTime; 7217 7383 7218 - PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k] 7219 - + PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth; 7384 + PixelDCFCLKCyclesRequiredInPrefetch[k] = (v->PrefetchLinesY[i][j][k] * v->swath_width_luma_ub_all_states[i][j][k] * v->BytePerPixelY[k] 7385 + + v->PrefetchLinesC[i][j][k] * v->swath_width_chroma_ub_all_states[i][j][k] * v->BytePerPixelC[k]) / NormalEfficiency / v->ReturnBusWidth; 7220 7386 DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k] 7221 - + PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0) 7222 - + 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth 7223 - + 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k]; 7224 - PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k]; 7225 - ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k]) 7226 - / (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]); 7387 + + v->PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth * (v->GPUVMMaxPageTableLevels > 2 ? 1 : 0) 7388 + + 2 * v->DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth 7389 + + 2 * v->MetaRowBytes[i][j][k] / NormalEfficiency / v->ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k]; 7390 + PrefetchPixelLinesTime[k] = dml_max(v->PrefetchLinesY[i][j][k], v->PrefetchLinesC[i][j][k]) * v->HTotal[k] / v->PixelClock[k]; 7391 + ExpectedPrefetchBWAcceleration = (v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k]) 7392 + / (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k]); 7227 7393 DynamicMetadataVMExtraLatency[k] = 7228 - (GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ? 7229 - UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; 7230 - PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait 7231 - - UrgLatency[i] 7232 - * ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels : GPUVMMaxPageTableLevels - 2) 7233 - * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) 7394 + (v->GPUVMEnable == true && v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true) ? 7395 + v->UrgLatency[i] * v->GPUVMMaxPageTableLevels * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0; 7396 + PrefetchTime = (v->MaximumVStartup[i][j][k] - 1) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait 7397 + - v->UrgLatency[i] 7398 + * ((v->GPUVMMaxPageTableLevels <= 2 ? v->GPUVMMaxPageTableLevels : v->GPUVMMaxPageTableLevels - 2) 7399 + * (v->HostVMEnable == true ? v->HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1) 7234 7400 - DynamicMetadataVMExtraLatency[k]; 7235 7401 7236 7402 if (PrefetchTime > 0) { ··· 7239 7405 / (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch); 7240 7406 DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k] 7241 7407 * dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration; 7242 - if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) { 7408 + if (v->HostVMEnable == true || v->ImmediateFlipRequirement[0] == dm_immediate_flip_required) { 7243 7409 DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k] 7244 - + NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / ReturnBusWidth; 7410 + + NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / v->ReturnBusWidth; 7245 7411 } 7246 7412 } else { 7247 - DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i]; 7413 + DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; 7248 7414 } 7249 - if (DynamicMetadataEnable[k] == true) { 7415 + if (v->DynamicMetadataEnable[k] == true) { 7250 7416 double TSetupPipe; 7251 7417 double TdmbfPipe; 7252 7418 double TdmsksPipe; ··· 7254 7420 double AllowedTimeForUrgentExtraLatency; 7255 7421 7256 7422 CalculateVupdateAndDynamicMetadataParameters( 7257 - MaxInterDCNTileRepeaters, 7258 - RequiredDPPCLK[i][j][k], 7259 - RequiredDISPCLK[i][j], 7260 - ProjectedDCFCLKDeepSleep[i][j], 7261 - PixelClock[k], 7262 - HTotal[k], 7263 - VTotal[k] - VActive[k], 7264 - DynamicMetadataTransmittedBytes[k], 7265 - DynamicMetadataLinesBeforeActiveRequired[k], 7266 - Interlace[k], 7267 - ProgressiveToInterlaceUnitInOPP, 7423 + v->MaxInterDCNTileRepeaters, 7424 + v->RequiredDPPCLK[i][j][k], 7425 + v->RequiredDISPCLK[i][j], 7426 + v->ProjectedDCFCLKDeepSleep[i][j], 7427 + v->PixelClock[k], 7428 + v->HTotal[k], 7429 + v->VTotal[k] - v->VActive[k], 7430 + v->DynamicMetadataTransmittedBytes[k], 7431 + v->DynamicMetadataLinesBeforeActiveRequired[k], 7432 + v->Interlace[k], 7433 + v->ProgressiveToInterlaceUnitInOPP, 7268 7434 &TSetupPipe, 7269 7435 &TdmbfPipe, 7270 7436 &TdmecPipe, ··· 7272 7438 &dummy1, 7273 7439 &dummy2, 7274 7440 &dummy3); 7275 - AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe 7441 + AllowedTimeForUrgentExtraLatency = v->MaximumVStartup[i][j][k] * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe 7276 7442 - TdmsksPipe - DynamicMetadataVMExtraLatency[k]; 7277 7443 if (AllowedTimeForUrgentExtraLatency > 0) { 7278 7444 DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max( 7279 7445 DCFCLKRequiredForPeakBandwidthPerPlane[k], 7280 7446 ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency); 7281 7447 } else { 7282 - DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i]; 7448 + DCFCLKRequiredForPeakBandwidthPerPlane[k] = v->DCFCLKPerState[i]; 7283 7449 } 7284 7450 } 7285 7451 } 7286 7452 DCFCLKRequiredForPeakBandwidth = 0; 7287 - for (k = 0; k <= NumberOfActivePlanes - 1; ++k) { 7453 + for (k = 0; k <= v->NumberOfActivePlanes - 1; ++k) { 7288 7454 DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k]; 7289 7455 } 7290 - MinimumTvmPlus2Tr0 = UrgLatency[i] 7291 - * (GPUVMEnable == true ? 7292 - (HostVMEnable == true ? 7293 - (GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) : 7456 + MinimumTvmPlus2Tr0 = v->UrgLatency[i] 7457 + * (v->GPUVMEnable == true ? 7458 + (v->HostVMEnable == true ? 7459 + (v->GPUVMMaxPageTableLevels + 2) * (v->HostVMMaxNonCachedPageTableLevels + 1) - 1 : v->GPUVMMaxPageTableLevels + 1) : 7294 7460 0); 7295 - for (k = 0; k < NumberOfActivePlanes; ++k) { 7461 + for (k = 0; k < v->NumberOfActivePlanes; ++k) { 7296 7462 double MaximumTvmPlus2Tr0PlusTsw; 7297 - MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; 7463 + MaximumTvmPlus2Tr0PlusTsw = (v->MaximumVStartup[i][j][k] - 2) * v->HTotal[k] / v->PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k]; 7298 7464 if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) { 7299 - DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i]; 7465 + DCFCLKRequiredForPeakBandwidth = v->DCFCLKPerState[i]; 7300 7466 } else { 7301 7467 DCFCLKRequiredForPeakBandwidth = dml_max3( 7302 7468 DCFCLKRequiredForPeakBandwidth, ··· 7304 7470 (2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0)); 7305 7471 } 7306 7472 } 7307 - DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth)); 7473 + v->DCFCLKState[i][j] = dml_min(v->DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth)); 7308 7474 } 7309 7475 } 7310 7476 }

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