Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/ltphy: Add function to calculate LT PHY port clock
Create a reverse algorithm which is used to find port clock
from the LT PHY state is provided which is used for
comparision & verification functions.
Bspec: 74667
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
+97
+2
drivers/gpu/drm/i915/display/intel_dpll.c
+2
drivers/gpu/drm/i915/display/intel_dpll.c
···
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return ret;
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/* TODO: Do the readback via intel_compute_shared_dplls() */
1250
+
crtc_state->port_clock =
1251
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intel_lt_phy_calc_port_clock(encoder, crtc_state);
1250
1252
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crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1252
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+92
drivers/gpu/drm/i915/display/intel_lt_phy.c
+92
drivers/gpu/drm/i915/display/intel_lt_phy.c
···
1235
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return false;
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}
1237
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+
static int
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+
intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
1240
+
{
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#define REF_CLK_KHZ 38400
1242
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#define REGVAL(i) ( \
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(lt_state->data[i][3]) | \
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(lt_state->data[i][2] << 8) | \
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(lt_state->data[i][1] << 16) | \
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(lt_state->data[i][0] << 24) \
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)
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+
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int clk = 0;
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u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
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+
u64 temp0, temp1;
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+
/*
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* The algorithm uses '+' to combine bitfields when
1254
+
* constructing PLL_reg3 and PLL_reg57:
1255
+
* PLL_reg57 = (D7 << 24) + (postdiv << 15) + (D8 << 7) + D6_new;
1256
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* PLL_reg3 = (D4 << 21) + (D3 << 18) + (D1 << 15) + (m2div_int << 5);
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*
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* However, this is likely intended to be a bitwise OR operation,
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* as each field occupies distinct, non-overlapping bits in the register.
1260
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*
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* PLL_reg57 is composed of following fields packed into a 32-bit value:
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* - D7: max value 10 -> fits in 4 bits -> placed at bits 24-27
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* - postdiv: max value 9 -> fits in 4 bits -> placed at bits 15-18
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* - D8: derived from loop_cnt / 2, max 127 -> fits in 7 bits
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* (though 8 bits are given to it) -> placed at bits 7-14
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* - D6_new: fits in lower 7 bits -> placed at bits 0-6
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* PLL_reg57 = (D7 << 24) | (postdiv << 15) | (D8 << 7) | D6_new;
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*
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* Similarly, PLL_reg3 is packed as:
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* - D4: max value 256 -> fits in 9 bits -> placed at bits 21-29
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* - D3: max value 9 -> fits in 4 bits -> placed at bits 18-21
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* - D1: max value 2 -> fits in 2 bits -> placed at bits 15-16
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* - m2div_int: max value 511 -> fits in 9 bits (10 bits allocated)
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* -> placed at bits 5-14
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* PLL_reg3 = (D4 << 21) | (D3 << 18) | (D1 << 15) | (m2div_int << 5);
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*/
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pll_reg_5 = REGVAL(2);
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pll_reg_3 = REGVAL(1);
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pll_reg_57 = REGVAL(3);
1280
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m2div_frac = pll_reg_5;
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+
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/*
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* From forward algorithm we know
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* m2div = 2 * m2
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* val = y * frequency * 5
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* So now,
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* frequency = (m2 * 2 * refclk_khz / (d8 * 10))
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* frequency = (m2div * refclk_khz / (d8 * 10))
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*/
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d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7;
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m2div_int = (pll_reg_3 & REG_GENMASK(14, 5)) >> 5;
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temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32;
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temp1 = (u64)m2div_int * REF_CLK_KHZ;
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if (d8 == 0)
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return 0;
1296
+
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clk = div_u64((temp1 + temp0), d8 * 10);
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+
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return clk;
1300
+
}
1301
+
1302
+
int
1303
+
intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
1304
+
const struct intel_crtc_state *crtc_state)
1305
+
{
1306
+
int clk;
1307
+
const struct intel_lt_phy_pll_state *lt_state =
1308
+
&crtc_state->dpll_hw_state.ltpll;
1309
+
u8 mode, rate;
1310
+
1311
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mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,
1312
+
lt_state->config[0]);
1313
+
/*
1314
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* For edp/dp read the clock value from the tables
1315
+
* and return the clock as the algorithm used for
1316
+
* calculating the port clock does not exactly matches
1317
+
* with edp/dp clock.
1318
+
*/
1319
+
if (mode == MODE_DP) {
1320
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rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
1321
+
lt_state->config[0]);
1322
+
clk = intel_lt_phy_get_dp_clock(rate);
1323
+
} else {
1324
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clk = intel_lt_phy_calc_hdmi_port_clock(lt_state);
1325
+
}
1326
+
1327
+
return clk;
1328
+
}
1329
+
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int
1239
1331
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
1240
1332
struct intel_encoder *encoder)
+3
drivers/gpu/drm/i915/display/intel_lt_phy.h
+3
drivers/gpu/drm/i915/display/intel_lt_phy.h
···
10
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struct intel_encoder;
12
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struct intel_crtc_state;
13
+
struct intel_lt_phy_pll_state;
13
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void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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int
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intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
18
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struct intel_encoder *encoder);
20
+
int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
21
+
const struct intel_crtc_state *crtc_state);
19
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#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
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