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phy: qcom: qmp-combo: Add polarity inversion support for SAR2130P

On SAR2130P QXR Platform, the CC Lines are inverted and the lane
programming is to be done reverse compared to other targets.

As per the HW specifics, Bit-2 of TYPEC_CTRL register indicates
port select polarity. This bit is to be set for SAR2130P.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20251017203438.744197-1-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Krishna Kurapati and committed by
Vinod Koul 24991bfb 3554ded4

+7
+7
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 69 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 70 #define SW_PORTSELECT_VAL BIT(0) 71 71 #define SW_PORTSELECT_MUX BIT(1) 72 + #define INVERT_CC_POLARITY BIT(2) 72 73 73 74 #define PHY_INIT_COMPLETE_TIMEOUT 10000 74 75 ··· 2261 2260 /* Offset from PCS to PCS_USB region */ 2262 2261 unsigned int pcs_usb_offset; 2263 2262 2263 + bool invert_cc_polarity; 2264 2264 }; 2265 2265 2266 2266 struct qmp_combo { ··· 2473 2471 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2474 2472 .vreg_list = qmp_phy_vreg_l, 2475 2473 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2474 + .invert_cc_polarity = true, 2476 2475 }; 2477 2476 2478 2477 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { ··· 3708 3705 val = SW_PORTSELECT_MUX; 3709 3706 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 3710 3707 val |= SW_PORTSELECT_VAL; 3708 + 3709 + if (cfg->invert_cc_polarity) 3710 + val |= INVERT_CC_POLARITY; 3711 + 3711 3712 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 3712 3713 3713 3714 switch (qmp->qmpphy_mode) {