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perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into INTEL_FIXED_BITS_MASK

ICL_FIXED_0_ADAPTIVE is missed to be added into INTEL_FIXED_BITS_MASK,
add it.

With help of this new INTEL_FIXED_BITS_MASK, intel_pmu_enable_fixed() can
be optimized. The old fixed counter control bits can be unconditionally
cleared with INTEL_FIXED_BITS_MASK and then set new control bits base on
new configuration.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-7-dapeng1.mi@linux.intel.com

authored by

Dapeng Mi and committed by
Peter Zijlstra 2676dbf9 9b3e1197

+9 -9
+3 -7
arch/x86/events/intel/core.c
··· 2845 2845 { 2846 2846 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 2847 2847 struct hw_perf_event *hwc = &event->hw; 2848 - u64 mask, bits = 0; 2849 2848 int idx = hwc->idx; 2849 + u64 bits = 0; 2850 2850 2851 2851 if (is_topdown_idx(idx)) { 2852 2852 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); ··· 2885 2885 2886 2886 idx -= INTEL_PMC_IDX_FIXED; 2887 2887 bits = intel_fixed_bits_by_idx(idx, bits); 2888 - mask = intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2889 - 2890 - if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) { 2888 + if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) 2891 2889 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2892 - mask |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE); 2893 - } 2894 2890 2895 - cpuc->fixed_ctrl_val &= ~mask; 2891 + cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK); 2896 2892 cpuc->fixed_ctrl_val |= bits; 2897 2893 } 2898 2894
+5 -1
arch/x86/include/asm/perf_event.h
··· 35 35 #define ARCH_PERFMON_EVENTSEL_EQ (1ULL << 36) 36 36 #define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40) 37 37 38 - #define INTEL_FIXED_BITS_MASK 0xFULL 39 38 #define INTEL_FIXED_BITS_STRIDE 4 40 39 #define INTEL_FIXED_0_KERNEL (1ULL << 0) 41 40 #define INTEL_FIXED_0_USER (1ULL << 1) ··· 46 47 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33) 47 48 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) 48 49 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32) 50 + 51 + #define INTEL_FIXED_BITS_MASK \ 52 + (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | \ 53 + INTEL_FIXED_0_ANYTHREAD | INTEL_FIXED_0_ENABLE_PMI | \ 54 + ICL_FIXED_0_ADAPTIVE) 49 55 50 56 #define intel_fixed_bits_by_idx(_idx, _bits) \ 51 57 ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))
+1 -1
arch/x86/kvm/pmu.h
··· 13 13 #define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | \ 14 14 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL) 15 15 16 - /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */ 16 + /* retrieve a fixed counter bits out of IA32_FIXED_CTR_CTRL */ 17 17 #define fixed_ctrl_field(ctrl_reg, idx) \ 18 18 (((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK) 19 19