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drm/msm/dsi_phy_28nm_8960: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series. The change to use clamp_t() was
done manually.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/667870/
Link: https://lore.kernel.org/r/20250810-drm-msm-phy-clk-round-rate-v2-3-0fd1f7979c83@redhat.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Brian Masney and committed by
Dmitry Baryshkov 267c0a2d cc41f29a

+16 -16
+16 -16
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
··· 231 231 pll_28nm->phy->pll_on = false; 232 232 } 233 233 234 - static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, 235 - unsigned long rate, unsigned long *parent_rate) 234 + static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, 235 + struct clk_rate_request *req) 236 236 { 237 237 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); 238 238 239 - if (rate < pll_28nm->phy->cfg->min_pll_rate) 240 - return pll_28nm->phy->cfg->min_pll_rate; 241 - else if (rate > pll_28nm->phy->cfg->max_pll_rate) 242 - return pll_28nm->phy->cfg->max_pll_rate; 243 - else 244 - return rate; 239 + req->rate = clamp_t(unsigned long, req->rate, 240 + pll_28nm->phy->cfg->min_pll_rate, pll_28nm->phy->cfg->max_pll_rate); 241 + 242 + return 0; 245 243 } 246 244 247 245 static const struct clk_ops clk_ops_dsi_pll_28nm_vco = { 248 - .round_rate = dsi_pll_28nm_clk_round_rate, 246 + .determine_rate = dsi_pll_28nm_clk_determine_rate, 249 247 .set_rate = dsi_pll_28nm_clk_set_rate, 250 248 .recalc_rate = dsi_pll_28nm_clk_recalc_rate, 251 249 .prepare = dsi_pll_28nm_vco_prepare, ··· 294 296 return 8; 295 297 } 296 298 297 - static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, 298 - unsigned long *prate) 299 + static int clk_bytediv_determine_rate(struct clk_hw *hw, 300 + struct clk_rate_request *req) 299 301 { 300 302 unsigned long best_parent; 301 303 unsigned int factor; 302 304 303 - factor = get_vco_mul_factor(rate); 305 + factor = get_vco_mul_factor(req->rate); 304 306 305 - best_parent = rate * factor; 306 - *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); 307 + best_parent = req->rate * factor; 308 + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); 307 309 308 - return *prate / factor; 310 + req->rate = req->best_parent_rate / factor; 311 + 312 + return 0; 309 313 } 310 314 311 315 static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, ··· 328 328 329 329 /* Our special byte clock divider ops */ 330 330 static const struct clk_ops clk_bytediv_ops = { 331 - .round_rate = clk_bytediv_round_rate, 331 + .determine_rate = clk_bytediv_determine_rate, 332 332 .set_rate = clk_bytediv_set_rate, 333 333 .recalc_rate = clk_bytediv_recalc_rate, 334 334 };