drm/amdgpu: clarify MEC_HPD_SIZE is specific to a gfx generation

+5 -6

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

··· 49 49 50 50 #define GFX7_NUM_GFX_RINGS 1 51 51 #define GFX7_NUM_COMPUTE_RINGS 8 52 + #define GFX7_MEC_HPD_SIZE 2048 52 53 53 54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 54 55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); ··· 2822 2821 } 2823 2822 } 2824 2823 2825 - #define MEC_HPD_SIZE 2048 2826 - 2827 2824 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2828 2825 { 2829 2826 int r; ··· 2839 2840 2840 2841 if (adev->gfx.mec.hpd_eop_obj == NULL) { 2841 2842 r = amdgpu_bo_create(adev, 2842 - adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 2843 + adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2, 2843 2844 PAGE_SIZE, true, 2844 2845 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2845 2846 &adev->gfx.mec.hpd_eop_obj); ··· 2869 2870 } 2870 2871 2871 2872 /* clear memory. Not sure if this is required or not */ 2872 - memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 2873 + memset(hpd, 0, adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * GFX7_MEC_HPD_SIZE * 2); 2873 2874 2874 2875 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2875 2876 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); ··· 2977 2978 int me = (i < 4) ? 1 : 2; 2978 2979 int pipe = (i < 4) ? i : (i - 4); 2979 2980 2980 - eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); 2981 + eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * GFX7_MEC_HPD_SIZE * 2); 2981 2982 2982 2983 cik_srbm_select(adev, me, pipe, 0, 0); 2983 2984 ··· 2991 2992 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2992 2993 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2993 2994 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2994 - tmp |= order_base_2(MEC_HPD_SIZE / 8); 2995 + tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2995 2996 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2996 2997 } 2997 2998 cik_srbm_select(adev, 0, 0, 0, 0);

+7 -8

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

··· 53 53 54 54 #define GFX8_NUM_GFX_RINGS 1 55 55 #define GFX8_NUM_COMPUTE_RINGS 8 56 + #define GFX8_MEC_HPD_SIZE 2048 56 57 57 58 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 58 59 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 ··· 1422 1421 amdgpu_ring_fini(ring); 1423 1422 } 1424 1423 1425 - #define MEC_HPD_SIZE 2048 1426 - 1427 1424 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 1428 1425 { 1429 1426 int r; ··· 1437 1438 1438 1439 if (adev->gfx.mec.hpd_eop_obj == NULL) { 1439 1440 r = amdgpu_bo_create(adev, 1440 - adev->gfx.mec.num_queue * MEC_HPD_SIZE, 1441 + adev->gfx.mec.num_queue * GFX8_MEC_HPD_SIZE, 1441 1442 PAGE_SIZE, true, 1442 1443 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 1443 1444 &adev->gfx.mec.hpd_eop_obj); ··· 1466 1467 return r; 1467 1468 } 1468 1469 1469 - memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE); 1470 + memset(hpd, 0, adev->gfx.mec.num_queue * GFX8_MEC_HPD_SIZE); 1470 1471 1471 1472 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1472 1473 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); ··· 1487 1488 u32 *hpd; 1488 1489 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 1489 1490 1490 - r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, 1491 + r = amdgpu_bo_create_kernel(adev, GFX8_MEC_HPD_SIZE, PAGE_SIZE, 1491 1492 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 1492 1493 &kiq->eop_gpu_addr, (void **)&hpd); 1493 1494 if (r) { ··· 1495 1496 return r; 1496 1497 } 1497 1498 1498 - memset(hpd, 0, MEC_HPD_SIZE); 1499 + memset(hpd, 0, GFX8_MEC_HPD_SIZE); 1499 1500 1500 1501 r = amdgpu_bo_reserve(kiq->eop_obj, true); 1501 1502 if (unlikely(r != 0)) ··· 2174 2175 ring->me = 1; /* first MEC */ 2175 2176 ring->pipe = i / 8; 2176 2177 ring->queue = i % 8; 2177 - ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 2178 + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * GFX8_MEC_HPD_SIZE); 2178 2179 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2179 2180 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 2180 2181 /* type-2 packets are deprecated on MEC, use type-3 instead */ ··· 4794 4795 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4795 4796 tmp = RREG32(mmCP_HQD_EOP_CONTROL); 4796 4797 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4797 - (order_base_2(MEC_HPD_SIZE / 4) - 1)); 4798 + (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1)); 4798 4799 4799 4800 mqd->cp_hqd_eop_control = tmp; 4800 4801

+6 -7

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

··· 39 39 40 40 #define GFX9_NUM_GFX_RINGS 1 41 41 #define GFX9_NUM_COMPUTE_RINGS 8 42 + #define GFX9_MEC_HPD_SIZE 2048 42 43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 43 44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 44 45 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34 ··· 858 857 } 859 858 } 860 859 861 - #define MEC_HPD_SIZE 2048 862 - 863 860 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 864 861 { 865 862 int r; ··· 878 879 879 880 if (adev->gfx.mec.hpd_eop_obj == NULL) { 880 881 r = amdgpu_bo_create(adev, 881 - adev->gfx.mec.num_queue * MEC_HPD_SIZE, 882 + adev->gfx.mec.num_queue * GFX9_MEC_HPD_SIZE, 882 883 PAGE_SIZE, true, 883 884 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 884 885 &adev->gfx.mec.hpd_eop_obj); ··· 971 972 u32 *hpd; 972 973 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 973 974 974 - r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, 975 + r = amdgpu_bo_create_kernel(adev, GFX9_MEC_HPD_SIZE, PAGE_SIZE, 975 976 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 976 977 &kiq->eop_gpu_addr, (void **)&hpd); 977 978 if (r) { ··· 979 980 return r; 980 981 } 981 982 982 - memset(hpd, 0, MEC_HPD_SIZE); 983 + memset(hpd, 0, GFX9_MEC_HPD_SIZE); 983 984 984 985 r = amdgpu_bo_reserve(kiq->eop_obj, true); 985 986 if (unlikely(r != 0)) ··· 1494 1495 ring->me = 1; /* first MEC */ 1495 1496 ring->pipe = i / 8; 1496 1497 ring->queue = i % 8; 1497 - ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 1498 + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * GFX9_MEC_HPD_SIZE); 1498 1499 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1499 1500 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 1500 1501 /* type-2 packets are deprecated on MEC, use type-3 instead */ ··· 2671 2672 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2672 2673 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2673 2674 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2674 - (order_base_2(MEC_HPD_SIZE / 4) - 1)); 2675 + (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2675 2676 2676 2677 mqd->cp_hqd_eop_control = tmp; 2677 2678

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