Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: replace fast_validate with enum dc_validate_mode
[Why]
The boolean fast_validate is used as an
input parameter in multiple functions. To
support more scenarios, we are
replacing it with enum dc_validate_mode.
[How]
The enum dc_validate_mode introduces three
possible values:
1) DC_VALIDATE_MODE_AND_PROGRAMMING:
Apply the mode to hardware
2) DC_VALIDATE_MODE_ONLY:
Check whether the mode can be supported
3) DC_VALIDATE_MODE_AND_STATE_INDEX:
Check if the mode can be supported, and
determine the optimal voltage level
needed to support it.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Yan Li <yan.li@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Yan Li
and committed by
Alex Deucher
269c1d14
d42b2331
+198
-182
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
7520
7520
dc_result = DC_FAIL_ATTACH_SURFACES;
7521
7521
7522
7522
if (dc_result == DC_OK)
7523
-
dc_result = dc_validate_global_state(dc, dc_state, true);
7523
+
dc_result = dc_validate_global_state(dc, dc_state, DC_VALIDATE_MODE_ONLY);
7524
7524
7525
7525
cleanup:
7526
7526
if (dc_state)
···
12142
12142
drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n");
12143
12143
goto fail;
12144
12144
}
12145
-
status = dc_validate_global_state(dc, dm_state->context, true);
12145
+
status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY);
12146
12146
if (status != DC_OK) {
12147
12147
drm_dbg_atomic(dev, "DC global validation failure: %s (%d)",
12148
12148
dc_status_to_str(status), status);
+7
-5
drivers/gpu/drm/amd/display/dc/core/dc.c
+7
-5
drivers/gpu/drm/amd/display/dc/core/dc.c
···
2377
2377
2378
2378
context->power_source = params->power_source;
2379
2379
2380
-
res = dc_validate_with_context(dc, set, params->stream_count, context, false);
2380
+
res = dc_validate_with_context(dc, set, params->stream_count, context, DC_VALIDATE_MODE_AND_PROGRAMMING);
2381
2381
2382
2382
/*
2383
2383
* Only update link encoder to stream assignment after bandwidth validation passed.
···
3300
3300
if (dsc_validate_context) {
3301
3301
stream->timing.dsc_cfg = *update->dsc_config;
3302
3302
stream->timing.flags.DSC = enable_dsc;
3303
-
if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true) != DC_OK) {
3303
+
if (dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context,
3304
+
DC_VALIDATE_MODE_ONLY) != DC_OK) {
3304
3305
stream->timing.dsc_cfg = old_dsc_cfg;
3305
3306
stream->timing.flags.DSC = old_dsc_enabled;
3306
3307
update->dsc_config = NULL;
···
3523
3522
}
3524
3523
3525
3524
if (update_type == UPDATE_TYPE_FULL) {
3526
-
if (dc->res_pool->funcs->validate_bandwidth(dc, context, false) != DC_OK) {
3525
+
if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {
3527
3526
BREAK_TO_DEBUGGER();
3528
3527
goto fail;
3529
3528
}
···
4629
4628
4630
4629
backup_and_set_minimal_pipe_split_policy(dc, base_context, policy);
4631
4630
/* commit minimal state */
4632
-
if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context, false) == DC_OK) {
4631
+
if (dc->res_pool->funcs->validate_bandwidth(dc, minimal_transition_context,
4632
+
DC_VALIDATE_MODE_AND_PROGRAMMING) == DC_OK) {
4633
4633
/* prevent underflow and corruption when reconfiguring pipes */
4634
4634
force_vsync_flip_in_minimal_transition_context(minimal_transition_context);
4635
4635
} else {
···
5153
5151
copy_stream_update_to_stream(dc, context, stream, stream_update);
5154
5152
5155
5153
if (update_type >= UPDATE_TYPE_FULL) {
5156
-
if (dc->res_pool->funcs->validate_bandwidth(dc, context, false) != DC_OK) {
5154
+
if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) {
5157
5155
DC_ERROR("Mode validation failed for stream update!\n");
5158
5156
dc_state_release(context);
5159
5157
return false;
+6
-6
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+6
-6
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
···
4053
4053
* @set: An array of dc_validation_set with all the current streams reference
4054
4054
* @set_count: Total of streams
4055
4055
* @context: New context
4056
-
* @fast_validate: Enable or disable fast validation
4056
+
* @validate_mode: identify the validation mode
4057
4057
*
4058
4058
* This function updates the potential new stream in the context object. It
4059
4059
* creates multiple lists for the add, remove, and unchanged streams. In
···
4068
4068
const struct dc_validation_set set[],
4069
4069
int set_count,
4070
4070
struct dc_state *context,
4071
-
bool fast_validate)
4071
+
enum dc_validate_mode validate_mode)
4072
4072
{
4073
4073
struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
4074
4074
struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
···
4242
4242
dc_state_set_stream_subvp_cursor_limit(context->streams[i], context, false);
4243
4243
}
4244
4244
4245
-
res = dc_validate_global_state(dc, context, fast_validate);
4245
+
res = dc_validate_global_state(dc, context, validate_mode);
4246
4246
4247
4247
/* calculate pixel rate divider after deciding pxiel clock & odm combine */
4248
4248
if ((dc->hwss.calculate_pix_rate_divider) && (res == DC_OK)) {
···
4299
4299
*
4300
4300
* @dc: dc struct for this driver
4301
4301
* @new_ctx: state to be validated
4302
-
* @fast_validate: set to true if only yes/no to support matters
4302
+
* @validate_mode: identify the validation mode
4303
4303
*
4304
4304
* Checks hardware resource availability and bandwidth requirement.
4305
4305
*
···
4309
4309
enum dc_status dc_validate_global_state(
4310
4310
struct dc *dc,
4311
4311
struct dc_state *new_ctx,
4312
-
bool fast_validate)
4312
+
enum dc_validate_mode validate_mode)
4313
4313
{
4314
4314
enum dc_status result = DC_ERROR_UNEXPECTED;
4315
4315
int i, j;
···
4368
4368
result = resource_build_scaling_params_for_context(dc, new_ctx);
4369
4369
4370
4370
if (result == DC_OK)
4371
-
result = dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate);
4371
+
result = dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, validate_mode);
4372
4372
4373
4373
return result;
4374
4374
}
+2
-6
drivers/gpu/drm/amd/display/dc/dc.h
+2
-6
drivers/gpu/drm/amd/display/dc/dc.h
···
1804
1804
const struct dc_validation_set set[],
1805
1805
int set_count,
1806
1806
struct dc_state *context,
1807
-
bool fast_validate);
1807
+
enum dc_validate_mode validate_mode);
1808
1808
1809
1809
bool dc_set_generic_gpio_for_stereo(bool enable,
1810
1810
struct gpio_service *gpio_service);
1811
1811
1812
-
/*
1813
-
* fast_validate: we return after determining if we can support the new state,
1814
-
* but before we populate the programming info
1815
-
*/
1816
1812
enum dc_status dc_validate_global_state(
1817
1813
struct dc *dc,
1818
1814
struct dc_state *new_ctx,
1819
-
bool fast_validate);
1815
+
enum dc_validate_mode validate_mode);
1820
1816
1821
1817
bool dc_acquire_release_mpc_3dlut(
1822
1818
struct dc *dc, bool acquire,
+8
drivers/gpu/drm/amd/display/dc/dc_types.h
+8
drivers/gpu/drm/amd/display/dc/dc_types.h
···
1370
1370
uint8_t aux_inst;
1371
1371
};
1372
1372
1373
+
enum dc_validate_mode {
1374
+
/* validate the mode and program HW */
1375
+
DC_VALIDATE_MODE_AND_PROGRAMMING = 0,
1376
+
/* only validate the mode */
1377
+
DC_VALIDATE_MODE_ONLY = 1,
1378
+
/* validate the mode and get the max state (voltage level) */
1379
+
DC_VALIDATE_MODE_AND_STATE_INDEX = 2,
1380
+
};
1373
1381
#endif /* DC_TYPES_H_ */
+3
-3
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+3
-3
drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
···
748
748
bool dcn_validate_bandwidth(
749
749
struct dc *dc,
750
750
struct dc_state *context,
751
-
bool fast_validate)
751
+
enum dc_validate_mode validate_mode)
752
752
{
753
753
/*
754
754
* we want a breakdown of the various stages of validation, which the
···
1119
1119
1120
1120
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1121
1121
1122
-
if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1122
+
if (v->voltage_level != number_of_states_plus_one && validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
1123
1123
float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1124
1124
1125
1125
if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
···
1286
1286
}
1287
1287
} else if (v->voltage_level == number_of_states_plus_one) {
1288
1288
BW_VAL_TRACE_SKIP(fail);
1289
-
} else if (fast_validate) {
1289
+
} else if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1290
1290
BW_VAL_TRACE_SKIP(fast);
1291
1291
}
1292
1292
+22
-23
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+22
-23
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
···
1315
1315
int dcn20_populate_dml_pipes_from_context(struct dc *dc,
1316
1316
struct dc_state *context,
1317
1317
display_e2e_pipe_params_st *pipes,
1318
-
bool fast_validate)
1318
+
enum dc_validate_mode validate_mode)
1319
1319
{
1320
1320
int pipe_cnt, i;
1321
1321
bool synchronized_vblank = true;
···
1733
1733
int *out_pipe_cnt,
1734
1734
int *pipe_split_from,
1735
1735
int vlevel,
1736
-
bool fast_validate)
1736
+
enum dc_validate_mode validate_mode)
1737
1737
{
1738
1738
int pipe_cnt, i, pipe_idx;
1739
1739
···
1780
1780
if (pipe_cnt != pipe_idx) {
1781
1781
if (dc->res_pool->funcs->populate_dml_pipes)
1782
1782
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1783
-
context, pipes, fast_validate);
1783
+
context, pipes, validate_mode);
1784
1784
else
1785
1785
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
1786
-
context, pipes, fast_validate);
1786
+
context, pipes, validate_mode);
1787
1787
}
1788
1788
1789
1789
*out_pipe_cnt = pipe_cnt;
···
2027
2027
}
2028
2028
2029
2029
static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2030
-
bool fast_validate, display_e2e_pipe_params_st *pipes)
2030
+
enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)
2031
2031
{
2032
2032
bool out = false;
2033
2033
···
2040
2040
2041
2041
BW_VAL_TRACE_COUNT();
2042
2042
2043
-
out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2043
+
out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);
2044
2044
2045
2045
if (pipe_cnt == 0)
2046
2046
goto validate_out;
···
2050
2050
2051
2051
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2052
2052
2053
-
if (fast_validate) {
2053
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
2054
2054
BW_VAL_TRACE_SKIP(fast);
2055
2055
goto validate_out;
2056
2056
}
2057
2057
2058
-
dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2058
+
dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);
2059
2059
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2060
2060
2061
2061
BW_VAL_TRACE_END_WATERMARKS();
···
2077
2077
}
2078
2078
2079
2079
bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
2080
-
bool fast_validate, display_e2e_pipe_params_st *pipes)
2080
+
enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)
2081
2081
{
2082
2082
bool voltage_supported = false;
2083
2083
bool full_pstate_supported = false;
···
2095
2095
/*Unsafe due to current pipe merge and split logic*/
2096
2096
ASSERT(context != dc->current_state);
2097
2097
2098
-
if (fast_validate) {
2099
-
return dcn20_validate_bandwidth_internal(dc, context, true, pipes);
2100
-
}
2098
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
2099
+
return dcn20_validate_bandwidth_internal(dc, context, validate_mode, pipes);
2101
2100
2102
2101
// Best case, we support full UCLK switch latency
2103
-
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
2102
+
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);
2104
2103
full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2105
2104
2106
2105
if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
···
2112
2113
context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
2113
2114
2114
2115
memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));
2115
-
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
2116
+
voltage_supported = dcn20_validate_bandwidth_internal(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING, pipes);
2116
2117
dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
2117
2118
2118
2119
if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
···
2155
2156
int dcn21_populate_dml_pipes_from_context(struct dc *dc,
2156
2157
struct dc_state *context,
2157
2158
display_e2e_pipe_params_st *pipes,
2158
-
bool fast_validate)
2159
+
enum dc_validate_mode validate_mode)
2159
2160
{
2160
2161
uint32_t pipe_cnt;
2161
2162
int i;
2162
2163
2163
2164
dc_assert_fp_enabled();
2164
2165
2165
-
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
2166
+
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
2166
2167
2167
2168
for (i = 0; i < pipe_cnt; i++) {
2168
2169
···
2238
2239
int *out_pipe_cnt,
2239
2240
int *pipe_split_from,
2240
2241
int vlevel_req,
2241
-
bool fast_validate)
2242
+
enum dc_validate_mode validate_mode)
2242
2243
{
2243
2244
int pipe_cnt, i, pipe_idx;
2244
2245
int vlevel, vlevel_max;
···
2280
2281
if (pipe_cnt != pipe_idx) {
2281
2282
if (dc->res_pool->funcs->populate_dml_pipes)
2282
2283
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2283
-
context, pipes, fast_validate);
2284
+
context, pipes, validate_mode);
2284
2285
else
2285
2286
pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
2286
-
context, pipes, fast_validate);
2287
+
context, pipes, validate_mode);
2287
2288
}
2288
2289
2289
2290
*out_pipe_cnt = pipe_cnt;
···
2318
2319
}
2319
2320
2320
2321
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
2321
-
bool fast_validate, display_e2e_pipe_params_st *pipes)
2322
+
enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes)
2322
2323
{
2323
2324
bool out = false;
2324
2325
···
2336
2337
/*Unsafe due to current pipe merge and split logic*/
2337
2338
ASSERT(context != dc->current_state);
2338
2339
2339
-
out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2340
+
out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, validate_mode);
2340
2341
2341
2342
if (pipe_cnt == 0)
2342
2343
goto validate_out;
···
2346
2347
2347
2348
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2348
2349
2349
-
if (fast_validate) {
2350
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
2350
2351
BW_VAL_TRACE_SKIP(fast);
2351
2352
goto validate_out;
2352
2353
}
2353
2354
2354
-
dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2355
+
dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, validate_mode);
2355
2356
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2356
2357
2357
2358
BW_VAL_TRACE_END_WATERMARKS();
+6
-6
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
+6
-6
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
···
44
44
int dcn20_populate_dml_pipes_from_context(struct dc *dc,
45
45
struct dc_state *context,
46
46
display_e2e_pipe_params_st *pipes,
47
-
bool fast_validate);
47
+
enum dc_validate_mode validate_mode);
48
48
void dcn20_calculate_wm(struct dc *dc,
49
49
struct dc_state *context,
50
50
display_e2e_pipe_params_st *pipes,
51
51
int *out_pipe_cnt,
52
52
int *pipe_split_from,
53
53
int vlevel,
54
-
bool fast_validate);
54
+
enum dc_validate_mode validate_mode);
55
55
void dcn20_cap_soc_clocks(struct _vcs_dpi_soc_bounding_box_st *bb,
56
56
struct pp_smu_nv_clock_table max_clocks);
57
57
void dcn20_update_bounding_box(struct dc *dc,
···
62
62
void dcn20_patch_bounding_box(struct dc *dc,
63
63
struct _vcs_dpi_soc_bounding_box_st *bb);
64
64
bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
65
-
bool fast_validate, display_e2e_pipe_params_st *pipes);
65
+
enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes);
66
66
void dcn20_fpu_set_wm_ranges(int i,
67
67
struct pp_smu_wm_range_sets *ranges,
68
68
struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
···
75
75
int dcn21_populate_dml_pipes_from_context(struct dc *dc,
76
76
struct dc_state *context,
77
77
display_e2e_pipe_params_st *pipes,
78
-
bool fast_validate);
79
-
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool
80
-
fast_validate, display_e2e_pipe_params_st *pipes);
78
+
enum dc_validate_mode validate_mode);
79
+
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, enum
80
+
dc_validate_mode, display_e2e_pipe_params_st *pipes);
81
81
void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
82
82
83
83
void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);
+4
-2
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+4
-2
drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
···
339
339
* newly found dummy_latency_index
340
340
*/
341
341
context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
342
-
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
342
+
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,
343
+
DC_VALIDATE_MODE_AND_PROGRAMMING, true);
343
344
maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
344
345
dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
345
346
pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
···
631
630
while (dummy_latency_index < max_latency_table_entries) {
632
631
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
633
632
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
634
-
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
633
+
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,
634
+
DC_VALIDATE_MODE_AND_PROGRAMMING, true);
635
635
636
636
if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==
637
637
dm_allow_self_refresh_and_mclk_switch)
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
···
306
306
307
307
int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,
308
308
display_e2e_pipe_params_st *pipes,
309
-
bool fast_validate)
309
+
enum dc_validate_mode validate_mode)
310
310
{
311
311
int i, pipe_cnt;
312
312
struct resource_context *res_ctx = &context->res_ctx;
···
316
316
317
317
dc_assert_fp_enabled();
318
318
319
-
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
319
+
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
320
320
321
321
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
322
322
struct dc_crtc_timing *timing;
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.h
···
35
35
void dcn314_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);
36
36
int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context,
37
37
display_e2e_pipe_params_st *pipes,
38
-
bool fast_validate);
38
+
enum dc_validate_mode validate_mode);
39
39
40
40
#endif
+17
-13
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+17
-13
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
···
290
290
vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
291
291
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
292
292
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
293
-
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
293
+
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);
294
294
295
295
/* for subvp + DRR case, if subvp pipes are still present we support pstate */
296
296
if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
···
1479
1479
1480
1480
/* Conditions for setting up phantom pipes for SubVP:
1481
1481
* 1. Not force disable SubVP
1482
-
* 2. Full update (i.e. !fast_validate)
1482
+
* 2. Full update (i.e. DC_VALIDATE_MODE_AND_PROGRAMMING)
1483
1483
* 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1484
1484
* 4. Display configuration passes validation
1485
1485
* 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
···
1517
1517
1518
1518
dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1519
1519
1520
-
*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1520
+
*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,
1521
+
DC_VALIDATE_MODE_AND_PROGRAMMING);
1521
1522
// Populate dppclk to trigger a recalculate in dml_get_voltage_level
1522
1523
// so the phantom pipe DLG params can be assigned correctly.
1523
1524
pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
···
1561
1560
dc_state_remove_phantom_streams_and_planes(dc, context);
1562
1561
dc_state_release_phantom_streams_and_planes(dc, context);
1563
1562
vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1564
-
*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1563
+
*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes,
1564
+
DC_VALIDATE_MODE_AND_PROGRAMMING);
1565
1565
1566
1566
*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1567
1567
/* This may adjust vlevel and maxMpcComb */
···
2140
2138
display_e2e_pipe_params_st *pipes,
2141
2139
int *pipe_cnt_out,
2142
2140
int *vlevel_out,
2143
-
bool fast_validate)
2141
+
enum dc_validate_mode validate_mode)
2144
2142
{
2145
2143
bool out = false;
2146
2144
bool repopulate_pipes = false;
···
2164
2162
2165
2163
for (i = 0; i < context->stream_count; i++)
2166
2164
resource_update_pipes_for_stream_with_slice_count(context, dc->current_state, dc->res_pool, context->streams[i], 1);
2167
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2165
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
2168
2166
2169
2167
if (!pipe_cnt) {
2170
2168
out = true;
···
2174
2172
dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
2175
2173
context->bw_ctx.dml.soc.max_vratio_pre = dcn32_determine_max_vratio_prefetch(dc, context);
2176
2174
2177
-
if (!fast_validate) {
2175
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
2178
2176
if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,
2179
2177
&pipe_cnt, &repopulate_pipes))
2180
2178
goto validate_fail;
2181
2179
}
2182
2180
2183
-
if (fast_validate ||
2181
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING ||
2184
2182
(dc->debug.dml_disallow_alternate_prefetch_modes &&
2185
2183
(vlevel == context->bw_ctx.dml.soc.num_states ||
2186
2184
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
···
2197
2195
context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final =
2198
2196
dm_prefetch_support_none;
2199
2197
2200
-
context->bw_ctx.dml.validate_max_state = fast_validate;
2198
+
context->bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);
2201
2199
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2202
2200
2203
2201
context->bw_ctx.dml.validate_max_state = false;
···
2249
2247
int flag_vlevel = vlevel;
2250
2248
int i;
2251
2249
2252
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2250
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
2253
2251
if (!dc->config.enable_windowed_mpo_odm)
2254
2252
dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);
2255
2253
···
2345
2343
}
2346
2344
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2347
2345
dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2348
-
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2346
+
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMING);
2349
2347
maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2350
2348
if (is_subvp_p_drr) {
2351
2349
context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
···
2391
2389
context->bw_ctx.dml.soc.fclk_change_latency_us =
2392
2390
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2393
2391
}
2394
-
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2392
+
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp,
2393
+
DC_VALIDATE_MODE_AND_PROGRAMMING);
2395
2394
if (vlevel_temp < vlevel) {
2396
2395
vlevel = vlevel_temp;
2397
2396
maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
···
2413
2410
stream_status->fpo_in_use = false;
2414
2411
}
2415
2412
context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
2416
-
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2413
+
dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel,
2414
+
DC_VALIDATE_MODE_AND_PROGRAMMING);
2417
2415
}
2418
2416
}
2419
2417
}
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
···
437
437
int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
438
438
struct dc_state *context,
439
439
display_e2e_pipe_params_st *pipes,
440
-
bool fast_validate)
440
+
enum dc_validate_mode validate_mode)
441
441
{
442
442
int i, pipe_cnt;
443
443
struct resource_context *res_ctx = &context->res_ctx;
···
446
446
const unsigned int max_allowed_vblank_nom = 1023;
447
447
448
448
dcn31_populate_dml_pipes_from_context(dc, context, pipes,
449
-
fast_validate);
449
+
validate_mode);
450
450
451
451
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
452
452
struct dc_crtc_timing *timing;
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.h
···
37
37
int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
38
38
struct dc_state *context,
39
39
display_e2e_pipe_params_st *pipes,
40
-
bool fast_validate);
40
+
enum dc_validate_mode validate_mode);
41
41
42
42
void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context);
43
43
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
···
470
470
int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,
471
471
struct dc_state *context,
472
472
display_e2e_pipe_params_st *pipes,
473
-
bool fast_validate)
473
+
enum dc_validate_mode validate_mode)
474
474
{
475
475
int i, pipe_cnt;
476
476
struct resource_context *res_ctx = &context->res_ctx;
···
479
479
const unsigned int max_allowed_vblank_nom = 1023;
480
480
481
481
dcn31_populate_dml_pipes_from_context(dc, context, pipes,
482
-
fast_validate);
482
+
validate_mode);
483
483
484
484
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
485
485
struct dc_crtc_timing *timing;
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.h
···
12
12
int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc,
13
13
struct dc_state *context,
14
14
display_e2e_pipe_params_st *pipes,
15
-
bool fast_validate);
15
+
enum dc_validate_mode validate_mode);
16
16
17
17
void dcn351_decide_zstate_support(struct dc *dc, struct dc_state *context);
18
18
+4
-3
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+4
-3
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
···
326
326
return true;
327
327
}
328
328
329
-
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate)
329
+
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
330
+
enum dc_validate_mode validate_mode)
330
331
{
331
332
bool out = false;
332
333
333
-
/* Use dml_validate_only for fast_validate path */
334
-
if (fast_validate)
334
+
/* Use dml21_check_mode_support for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
335
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
335
336
out = dml21_check_mode_support(in_dc, context, dml_ctx);
336
337
else
337
338
out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);
+7
-4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
+7
-4
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h
···
14
14
struct dc_state;
15
15
struct dml2_configuration_options;
16
16
struct dml2_context;
17
+
enum dc_validate_mode;
17
18
18
19
/**
19
20
* dml2_create - Creates dml21_context.
···
40
39
* dml21_validate - Determines if a display configuration is supported or not.
41
40
* @in_dc: dc.
42
41
* @context: dc_state to be validated.
43
-
* @fast_validate: Fast validate will not populate context.res_ctx.
42
+
* @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX
43
+
* will not populate context.res_ctx.
44
44
*
45
45
* Based on fast_validate option internally would call:
46
46
*
47
-
* -dml21_mode_check_and_programming - for non fast_validate option
47
+
* -dml21_mode_check_and_programming - for DC_VALIDATE_MODE_AND_PROGRAMMING option
48
48
* Calculates if dc_state can be supported on the input display
49
49
* configuration. If supported, generates the necessary HW
50
50
* programming for the new dc_state.
51
51
*
52
-
* -dml21_check_mode_support - for fast_validate option
52
+
* -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option
53
53
* Calculates if dc_state can be supported for the input display
54
54
* config.
55
55
···
58
56
* separate dc_states for validation.
59
57
* Return: True if mode is supported, false otherwise.
60
58
*/
61
-
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx, bool fast_validate);
59
+
bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx,
60
+
enum dc_validate_mode validate_mode);
62
61
63
62
/* Prepare hubp mcache_regs for hubp mcache ID and split coordinate programming */
64
63
void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c
···
868
868
869
869
/* Conditions for setting up phantom pipes for SubVP:
870
870
* 1. Not force disable SubVP
871
-
* 2. Full update (i.e. !fast_validate)
871
+
* 2. Full update (i.e. DC_VALIDATE_MODE_AND_PROGRAMMING)
872
872
* 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
873
873
* 4. Display configuration passes validation
874
874
* 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch)
+5
-4
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+5
-4
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
···
721
721
}
722
722
}
723
723
724
-
bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, bool fast_validate)
724
+
bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,
725
+
enum dc_validate_mode validate_mode)
725
726
{
726
727
bool out = false;
727
728
···
732
731
733
732
/* DML2.1 validation path */
734
733
if (dml2->architecture == dml2_architecture_21) {
735
-
out = dml21_validate(in_dc, context, dml2, fast_validate);
734
+
out = dml21_validate(in_dc, context, dml2, validate_mode);
736
735
return out;
737
736
}
738
737
739
738
DC_FP_START();
740
739
741
-
/* Use dml_validate_only for fast_validate path */
742
-
if (fast_validate)
740
+
/* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
741
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
743
742
out = dml2_validate_only(context);
744
743
else
745
744
out = dml2_validate_and_build_resource(in_dc, context);
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
···
272
272
* dml2_validate - Determines if a display configuration is supported or not.
273
273
* @in_dc: dc.
274
274
* @context: dc_state to be validated.
275
-
* @fast_validate: Fast validate will not populate context.res_ctx.
275
+
* @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX will not populate context.res_ctx.
276
276
*
277
277
* DML1.0 compatible interface for validation.
278
278
*
···
295
295
bool dml2_validate(const struct dc *in_dc,
296
296
struct dc_state *context,
297
297
struct dml2_context *dml2,
298
-
bool fast_validate);
298
+
enum dc_validate_mode validate_mode);
299
299
300
300
/*
301
301
* dml2_extract_dram_and_fclk_change_support - Extracts the FCLK and UCLK change support info.
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
···
2484
2484
struct dce_hwseq *hws = dc->hwseq;
2485
2485
2486
2486
/* recalculate DML parameters */
2487
-
if (dc->res_pool->funcs->validate_bandwidth(dc, context, false) != DC_OK)
2487
+
if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)
2488
2488
return false;
2489
2489
2490
2490
/* apply updated bandwidth parameters */
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+1
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
···
2383
2383
struct dce_hwseq *hws = dc->hwseq;
2384
2384
2385
2385
/* recalculate DML parameters */
2386
-
if (dc->res_pool->funcs->validate_bandwidth(dc, context, false) != DC_OK)
2386
+
if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK)
2387
2387
return false;
2388
2388
2389
2389
/* apply updated bandwidth parameters */
+2
-2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
+2
-2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
···
82
82
enum dc_status (*validate_bandwidth)(
83
83
struct dc *dc,
84
84
struct dc_state *context,
85
-
bool fast_validate);
85
+
enum dc_validate_mode validate_mode);
86
86
void (*calculate_wm_and_dlg)(
87
87
struct dc *dc, struct dc_state *context,
88
88
display_e2e_pipe_params_st *pipes,
···
107
107
struct dc *dc,
108
108
struct dc_state *context,
109
109
display_e2e_pipe_params_st *pipes,
110
-
bool fast_validate);
110
+
enum dc_validate_mode validate_mode);
111
111
112
112
/*
113
113
* Algorithm for assigning available link encoders to links.
+1
-1
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+1
-1
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
···
1129
1129
static enum dc_status dcn10_validate_bandwidth(
1130
1130
struct dc *dc,
1131
1131
struct dc_state *context,
1132
-
bool fast_validate)
1132
+
enum dc_validate_mode validate_mode)
1133
1133
{
1134
1134
bool voltage_supported;
1135
1135
1136
1136
DC_FP_START();
1137
-
voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1137
+
voltage_supported = dcn_validate_bandwidth(dc, context, validate_mode);
1138
1138
DC_FP_END();
1139
1139
1140
1140
return voltage_supported ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
+4
-4
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+4
-4
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
···
2007
2007
int *pipe_cnt_out,
2008
2008
int *pipe_split_from,
2009
2009
int *vlevel_out,
2010
-
bool fast_validate)
2010
+
enum dc_validate_mode validate_mode)
2011
2011
{
2012
2012
bool out = false;
2013
2013
int split[MAX_PIPES] = { 0 };
···
2021
2021
dcn20_merge_pipes_for_validate(dc, context);
2022
2022
2023
2023
DC_FP_START();
2024
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2024
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
2025
2025
DC_FP_END();
2026
2026
2027
2027
*pipe_cnt_out = pipe_cnt;
···
2125
2125
}
2126
2126
2127
2127
enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2128
-
bool fast_validate)
2128
+
enum dc_validate_mode validate_mode)
2129
2129
{
2130
2130
bool voltage_supported;
2131
2131
display_e2e_pipe_params_st *pipes;
···
2135
2135
return DC_FAIL_BANDWIDTH_VALIDATE;
2136
2136
2137
2137
DC_FP_START();
2138
-
voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
2138
+
voltage_supported = dcn20_validate_bandwidth_fp(dc, context, validate_mode, pipes);
2139
2139
DC_FP_END();
2140
2140
2141
2141
kfree(pipes);
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h
···
119
119
struct dc_state *context,
120
120
display_e2e_pipe_params_st *pipes,
121
121
int pipe_cnt);
122
-
enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
122
+
enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode);
123
123
void dcn20_merge_pipes_for_validate(
124
124
struct dc *dc,
125
125
struct dc_state *context);
···
158
158
int *pipe_cnt_out,
159
159
int *pipe_split_from,
160
160
int *vlevel_out,
161
-
bool fast_validate);
161
+
enum dc_validate_mode validate_mode);
162
162
163
163
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
164
164
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+4
-4
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+4
-4
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
···
769
769
int *pipe_cnt_out,
770
770
int *pipe_split_from,
771
771
int *vlevel_out,
772
-
bool fast_validate)
772
+
enum dc_validate_mode validate_mode)
773
773
{
774
774
bool out = false;
775
775
int split[MAX_PIPES] = { 0 };
···
783
783
dcn20_merge_pipes_for_validate(dc, context);
784
784
785
785
DC_FP_START();
786
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
786
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
787
787
DC_FP_END();
788
788
789
789
*pipe_cnt_out = pipe_cnt;
···
924
924
* dcn20_validate_bandwidth in dcn20_resource.c.
925
925
*/
926
926
static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
927
-
bool fast_validate)
927
+
enum dc_validate_mode validate_mode)
928
928
{
929
929
bool voltage_supported;
930
930
display_e2e_pipe_params_st *pipes;
···
934
934
return DC_FAIL_BANDWIDTH_VALIDATE;
935
935
936
936
DC_FP_START();
937
-
voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);
937
+
voltage_supported = dcn21_validate_bandwidth_fp(dc, context, validate_mode, pipes);
938
938
DC_FP_END();
939
939
940
940
kfree(pipes);
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.h
+11
-11
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+11
-11
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
···
1319
1319
int dcn30_populate_dml_pipes_from_context(
1320
1320
struct dc *dc, struct dc_state *context,
1321
1321
display_e2e_pipe_params_st *pipes,
1322
-
bool fast_validate)
1322
+
enum dc_validate_mode validate_mode)
1323
1323
{
1324
1324
int i, pipe_cnt;
1325
1325
struct resource_context *res_ctx = &context->res_ctx;
1326
1326
1327
1327
DC_FP_START();
1328
-
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1328
+
dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1329
1329
DC_FP_END();
1330
1330
1331
1331
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
···
1627
1627
display_e2e_pipe_params_st *pipes,
1628
1628
int *pipe_cnt_out,
1629
1629
int *vlevel_out,
1630
-
bool fast_validate,
1630
+
enum dc_validate_mode validate_mode,
1631
1631
bool allow_self_refresh_only)
1632
1632
{
1633
1633
bool out = false;
···
1646
1646
context->bw_ctx.dml.vba.VoltageLevel = 0;
1647
1647
context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1648
1648
dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1649
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1649
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
1650
1650
1651
1651
if (!pipe_cnt) {
1652
1652
out = true;
···
1655
1655
1656
1656
dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1657
1657
1658
-
if (!fast_validate || !allow_self_refresh_only) {
1658
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING || !allow_self_refresh_only) {
1659
1659
/*
1660
1660
* DML favors voltage over p-state, but we're more interested in
1661
1661
* supporting p-state over voltage. We can't support p-state in
···
1669
1669
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1670
1670
}
1671
1671
if (allow_self_refresh_only &&
1672
-
(fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1672
+
(validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING || vlevel == context->bw_ctx.dml.soc.num_states ||
1673
1673
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
1674
1674
/*
1675
1675
* If mode is unsupported or there's still no p-state support
···
1678
1678
* We don't actually support prefetch mode 2, so require that we
1679
1679
* at least support prefetch mode 1.
1680
1680
*/
1681
-
context->bw_ctx.dml.validate_max_state = fast_validate;
1681
+
context->bw_ctx.dml.validate_max_state = (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING);
1682
1682
context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1683
1683
dm_allow_self_refresh;
1684
1684
···
1865
1865
}
1866
1866
1867
1867
if (repopulate_pipes)
1868
-
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1868
+
pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode);
1869
1869
context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1870
1870
*vlevel_out = vlevel;
1871
1871
*pipe_cnt_out = pipe_cnt;
···
2037
2037
2038
2038
enum dc_status dcn30_validate_bandwidth(struct dc *dc,
2039
2039
struct dc_state *context,
2040
-
bool fast_validate)
2040
+
enum dc_validate_mode validate_mode)
2041
2041
{
2042
2042
bool out = false;
2043
2043
···
2055
2055
goto validate_fail;
2056
2056
2057
2057
DC_FP_START();
2058
-
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
2058
+
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);
2059
2059
DC_FP_END();
2060
2060
2061
2061
if (pipe_cnt == 0)
···
2066
2066
2067
2067
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2068
2068
2069
-
if (fast_validate) {
2069
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
2070
2070
BW_VAL_TRACE_SKIP(fast);
2071
2071
goto validate_out;
2072
2072
}
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h
···
57
57
unsigned int urgent_watermark);
58
58
59
59
enum dc_status dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context,
60
-
bool fast_validate);
60
+
enum dc_validate_mode validate_mode);
61
61
bool dcn30_internal_validate_bw(
62
62
struct dc *dc,
63
63
struct dc_state *context,
64
64
display_e2e_pipe_params_st *pipes,
65
65
int *pipe_cnt_out,
66
66
int *vlevel_out,
67
-
bool fast_validate,
67
+
enum dc_validate_mode validate_mode,
68
68
bool allow_self_refresh_only);
69
69
void dcn30_calculate_wm_and_dlg(
70
70
struct dc *dc, struct dc_state *context,
···
78
78
int dcn30_populate_dml_pipes_from_context(
79
79
struct dc *dc, struct dc_state *context,
80
80
display_e2e_pipe_params_st *pipes,
81
-
bool fast_validate);
81
+
enum dc_validate_mode validate_mode);
82
82
83
83
bool dcn30_acquire_post_bldn_3dlut(
84
84
struct resource_context *res_ctx,
+9
-9
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+9
-9
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
···
1616
1616
int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1617
1617
struct dc_state *context,
1618
1618
display_e2e_pipe_params_st *pipes,
1619
-
bool fast_validate)
1619
+
enum dc_validate_mode validate_mode)
1620
1620
{
1621
1621
uint32_t pipe_cnt;
1622
1622
int i;
1623
1623
1624
1624
dc_assert_fp_enabled();
1625
1625
1626
-
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1626
+
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1627
1627
1628
1628
for (i = 0; i < pipe_cnt; i++) {
1629
1629
pipes[i].pipe.src.gpuvm = 1;
···
1641
1641
int dcn31_populate_dml_pipes_from_context(
1642
1642
struct dc *dc, struct dc_state *context,
1643
1643
display_e2e_pipe_params_st *pipes,
1644
-
bool fast_validate)
1644
+
enum dc_validate_mode validate_mode)
1645
1645
{
1646
1646
int i, pipe_cnt;
1647
1647
struct resource_context *res_ctx = &context->res_ctx;
···
1649
1649
bool upscaled = false;
1650
1650
1651
1651
DC_FP_START();
1652
-
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1652
+
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1653
1653
DC_FP_END();
1654
1654
1655
1655
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
···
1760
1760
1761
1761
enum dc_status dcn31_validate_bandwidth(struct dc *dc,
1762
1762
struct dc_state *context,
1763
-
bool fast_validate)
1763
+
enum dc_validate_mode validate_mode)
1764
1764
{
1765
1765
bool out = false;
1766
1766
···
1778
1778
goto validate_fail;
1779
1779
1780
1780
DC_FP_START();
1781
-
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
1781
+
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, true);
1782
1782
DC_FP_END();
1783
1783
1784
-
// Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1784
+
// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1785
1785
if (pipe_cnt == 0)
1786
-
fast_validate = false;
1786
+
validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1787
1787
1788
1788
if (!out)
1789
1789
goto validate_fail;
1790
1790
1791
1791
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1792
1792
1793
-
if (fast_validate) {
1793
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1794
1794
BW_VAL_TRACE_SKIP(fast);
1795
1795
goto validate_out;
1796
1796
}
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h
···
39
39
40
40
enum dc_status dcn31_validate_bandwidth(struct dc *dc,
41
41
struct dc_state *context,
42
-
bool fast_validate);
42
+
enum dc_validate_mode validate_mode);
43
43
void dcn31_calculate_wm_and_dlg(
44
44
struct dc *dc, struct dc_state *context,
45
45
display_e2e_pipe_params_st *pipes,
···
48
48
int dcn31_populate_dml_pipes_from_context(
49
49
struct dc *dc, struct dc_state *context,
50
50
display_e2e_pipe_params_st *pipes,
51
-
bool fast_validate);
51
+
enum dc_validate_mode validate_mode);
52
52
void
53
53
dcn31_populate_dml_writeback_from_context(struct dc *dc,
54
54
struct resource_context *res_ctx,
+7
-7
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+7
-7
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
···
1667
1667
static int dcn314_populate_dml_pipes_from_context(
1668
1668
struct dc *dc, struct dc_state *context,
1669
1669
display_e2e_pipe_params_st *pipes,
1670
-
bool fast_validate)
1670
+
enum dc_validate_mode validate_mode)
1671
1671
{
1672
1672
int pipe_cnt;
1673
1673
1674
1674
DC_FP_START();
1675
-
pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1675
+
pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1676
1676
DC_FP_END();
1677
1677
1678
1678
return pipe_cnt;
···
1696
1696
1697
1697
enum dc_status dcn314_validate_bandwidth(struct dc *dc,
1698
1698
struct dc_state *context,
1699
-
bool fast_validate)
1699
+
enum dc_validate_mode validate_mode)
1700
1700
{
1701
1701
bool out = false;
1702
1702
···
1715
1715
1716
1716
DC_FP_START();
1717
1717
// do not support self refresh only
1718
-
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
1718
+
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode, false);
1719
1719
DC_FP_END();
1720
1720
1721
-
// Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1721
+
// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calculate_wm_and_dlg
1722
1722
if (pipe_cnt == 0)
1723
-
fast_validate = false;
1723
+
validate_mode = DC_VALIDATE_MODE_AND_PROGRAMMING;
1724
1724
1725
1725
if (!out)
1726
1726
goto validate_fail;
1727
1727
1728
1728
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1729
1729
1730
-
if (fast_validate) {
1730
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1731
1731
BW_VAL_TRACE_SKIP(fast);
1732
1732
goto validate_out;
1733
1733
}
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
···
1664
1664
static int dcn315_populate_dml_pipes_from_context(
1665
1665
struct dc *dc, struct dc_state *context,
1666
1666
display_e2e_pipe_params_st *pipes,
1667
-
bool fast_validate)
1667
+
enum dc_validate_mode validate_mode)
1668
1668
{
1669
1669
int i, pipe_cnt, crb_idx, crb_pipes;
1670
1670
struct resource_context *res_ctx = &context->res_ctx;
···
1674
1674
bool pixel_rate_crb = allow_pixel_rate_crb(dc, context);
1675
1675
1676
1676
DC_FP_START();
1677
-
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1677
+
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1678
1678
DC_FP_END();
1679
1679
1680
1680
for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) {
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
···
1610
1610
static int dcn316_populate_dml_pipes_from_context(
1611
1611
struct dc *dc, struct dc_state *context,
1612
1612
display_e2e_pipe_params_st *pipes,
1613
-
bool fast_validate)
1613
+
enum dc_validate_mode validate_mode)
1614
1614
{
1615
1615
int i, pipe_cnt;
1616
1616
struct resource_context *res_ctx = &context->res_ctx;
···
1618
1618
const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1619
1619
1620
1620
DC_FP_START();
1621
-
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1621
+
dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1622
1622
DC_FP_END();
1623
1623
1624
1624
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+13
-13
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+13
-13
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
···
1742
1742
}
1743
1743
}
1744
1744
1745
-
static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)
1745
+
static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode)
1746
1746
{
1747
1747
bool out = false;
1748
1748
···
1767
1767
goto validate_fail;
1768
1768
1769
1769
DC_FP_START();
1770
-
out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1770
+
out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, validate_mode);
1771
1771
DC_FP_END();
1772
1772
1773
1773
if (pipe_cnt == 0)
···
1778
1778
1779
1779
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1780
1780
1781
-
if (fast_validate) {
1781
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING) {
1782
1782
BW_VAL_TRACE_SKIP(fast);
1783
1783
goto validate_out;
1784
1784
}
···
1809
1809
1810
1810
enum dc_status dcn32_validate_bandwidth(struct dc *dc,
1811
1811
struct dc_state *context,
1812
-
bool fast_validate)
1812
+
enum dc_validate_mode validate_mode)
1813
1813
{
1814
1814
unsigned int i;
1815
1815
enum dc_status status;
···
1827
1827
if (dc->debug.using_dml2)
1828
1828
status = dml2_validate(dc, context,
1829
1829
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1830
-
fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1830
+
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1831
1831
else
1832
-
status = dml1_validate(dc, context, fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1832
+
status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1833
1833
1834
-
if (!fast_validate && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1834
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1835
1835
/* check new stream configuration still supports cursor if subvp used */
1836
1836
for (i = 0; i < context->stream_count; i++) {
1837
1837
stream = context->streams[i];
···
1846
1846
};
1847
1847
}
1848
1848
1849
-
if (!fast_validate && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1849
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1850
1850
/* attempt to validate again with subvp disabled due to cursor */
1851
1851
if (dc->debug.using_dml2)
1852
1852
status = dml2_validate(dc, context,
1853
1853
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1854
-
fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1854
+
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1855
1855
else
1856
-
status = dml1_validate(dc, context, fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1856
+
status = dml1_validate(dc, context, validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1857
1857
}
1858
1858
1859
1859
return status;
···
1862
1862
int dcn32_populate_dml_pipes_from_context(
1863
1863
struct dc *dc, struct dc_state *context,
1864
1864
display_e2e_pipe_params_st *pipes,
1865
-
bool fast_validate)
1865
+
enum dc_validate_mode validate_mode)
1866
1866
{
1867
1867
int i, pipe_cnt;
1868
1868
struct resource_context *res_ctx = &context->res_ctx;
···
1878
1878
int num_subvp_none = 0;
1879
1879
int odm_slice_count;
1880
1880
1881
-
dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1881
+
dcn20_populate_dml_pipes_from_context(dc, context, pipes, validate_mode);
1882
1882
1883
1883
/* For single display subvp, look for subvp main so if we have phantom
1884
1884
* pipe, we can set odm policy to match main pipe
···
1960
1960
/* Only populate DML input with subvp info for full updates.
1961
1961
* This is just a workaround -- needs a proper fix.
1962
1962
*/
1963
-
if (!fast_validate) {
1963
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) {
1964
1964
switch (dc_state_get_pipe_subvp_type(context, pipe)) {
1965
1965
case SUBVP_MAIN:
1966
1966
pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
···
100
100
101
101
enum dc_status dcn32_validate_bandwidth(struct dc *dc,
102
102
struct dc_state *context,
103
-
bool fast_validate);
103
+
enum dc_validate_mode validate_mode);
104
104
105
105
int dcn32_populate_dml_pipes_from_context(
106
106
struct dc *dc, struct dc_state *context,
107
107
display_e2e_pipe_params_st *pipes,
108
-
bool fast_validate);
108
+
enum dc_validate_mode validate_mode);
109
109
110
110
void dcn32_calculate_wm_and_dlg(
111
111
struct dc *dc, struct dc_state *context,
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
···
1734
1734
1735
1735
static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1736
1736
struct dc_state *context,
1737
-
bool fast_validate)
1737
+
enum dc_validate_mode validate_mode)
1738
1738
{
1739
1739
bool out = false;
1740
1740
1741
1741
out = dml2_validate(dc, context,
1742
1742
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1743
-
fast_validate);
1743
+
validate_mode);
1744
1744
1745
-
if (fast_validate)
1745
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1746
1746
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1747
1747
1748
1748
DC_FP_START();
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
···
1714
1714
1715
1715
static enum dc_status dcn351_validate_bandwidth(struct dc *dc,
1716
1716
struct dc_state *context,
1717
-
bool fast_validate)
1717
+
enum dc_validate_mode validate_mode)
1718
1718
{
1719
1719
bool out = false;
1720
1720
1721
1721
out = dml2_validate(dc, context,
1722
1722
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1723
-
fast_validate);
1723
+
validate_mode);
1724
1724
1725
-
if (fast_validate)
1725
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1726
1726
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1727
1727
1728
1728
DC_FP_START();
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
···
1715
1715
1716
1716
static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1717
1717
struct dc_state *context,
1718
-
bool fast_validate)
1718
+
enum dc_validate_mode validate_mode)
1719
1719
{
1720
1720
bool out = false;
1721
1721
1722
1722
out = dml2_validate(dc, context,
1723
1723
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1724
-
fast_validate);
1724
+
validate_mode);
1725
1725
1726
-
if (fast_validate)
1726
+
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1727
1727
return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1728
1728
1729
1729
DC_FP_START();
+5
-5
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+5
-5
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
···
1644
1644
1645
1645
enum dc_status dcn401_validate_bandwidth(struct dc *dc,
1646
1646
struct dc_state *context,
1647
-
bool fast_validate)
1647
+
enum dc_validate_mode validate_mode)
1648
1648
{
1649
1649
unsigned int i;
1650
1650
enum dc_status status = DC_OK;
···
1662
1662
if (dc->debug.using_dml2)
1663
1663
status = dml2_validate(dc, context,
1664
1664
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1665
-
fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1665
+
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1666
1666
1667
-
if (!fast_validate && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1667
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1668
1668
/* check new stream configuration still supports cursor if subvp used */
1669
1669
for (i = 0; i < context->stream_count; i++) {
1670
1670
stream = context->streams[i];
···
1679
1679
};
1680
1680
}
1681
1681
1682
-
if (!fast_validate && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1682
+
if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1683
1683
/* attempt to validate again with subvp disabled due to cursor */
1684
1684
if (dc->debug.using_dml2)
1685
1685
status = dml2_validate(dc, context,
1686
1686
context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1687
-
fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1687
+
validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1688
1688
}
1689
1689
1690
1690
return status;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h