Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Fix Silence signed/unsighed mismatch warning in dc
[Why]
Implicit signed-to-unsigned conversions caused compiler
warnings in DC paths.
[How]
Added explicit (unsigned int)/(uint32_t) casts for sentinel -1
assignments and IRQ ~MASK initializers, with small cast alignment
in logging/DPCD code.
Functionality and behavior is unchanged; only type intent is explicit.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gaghik Khachatrian
and committed by
Alex Deucher
26ebcac0
8424ee7d
+86
-86
+4
-4
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+4
-4
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
···
2010
2010
}
2011
2011
/*output link bit per pixel supported*/
2012
2012
for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
2013
-
data->output_bpphdmi[k] = bw_def_na;
2014
-
data->output_bppdp4_lane_hbr[k] = bw_def_na;
2015
-
data->output_bppdp4_lane_hbr2[k] = bw_def_na;
2016
-
data->output_bppdp4_lane_hbr3[k] = bw_def_na;
2013
+
data->output_bpphdmi[k] = (uint32_t)bw_def_na;
2014
+
data->output_bppdp4_lane_hbr[k] = (uint32_t)bw_def_na;
2015
+
data->output_bppdp4_lane_hbr2[k] = (uint32_t)bw_def_na;
2016
+
data->output_bppdp4_lane_hbr3[k] = (uint32_t)bw_def_na;
2017
2017
if (data->enable[k]) {
2018
2018
data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
2019
2019
if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+1
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
···
92
92
uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
93
93
{
94
94
uint8_t j;
95
-
uint32_t min_vertical_blank_time = -1;
95
+
uint32_t min_vertical_blank_time = (uint32_t)-1;
96
96
97
97
for (j = 0; j < context->stream_count; j++) {
98
98
struct dc_stream_state *stream = context->streams[j];
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+3
-3
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+3
-3
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
···
610
610
|| pix_clk_params->requested_pix_clk_100hz == 0) {
611
611
DC_LOG_ERROR(
612
612
"%s: Invalid parameters!!\n", __func__);
613
-
return -1;
613
+
return (uint32_t)-1;
614
614
}
615
615
616
616
memset(pll_settings, 0, sizeof(*pll_settings));
···
621
621
pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
622
622
pll_settings->actual_pix_clk_100hz =
623
623
pix_clk_params->requested_pix_clk_100hz;
624
-
return -1;
624
+
return (uint32_t)-1;
625
625
}
626
626
627
627
dce112_get_pix_clk_dividers_helper(clk_src,
···
1376
1376
|| pix_clk_params->requested_pix_clk_100hz == 0) {
1377
1377
DC_LOG_ERROR(
1378
1378
"%s: Invalid parameters!!\n", __func__);
1379
-
return -1;
1379
+
return UINT_MAX;
1380
1380
}
1381
1381
1382
1382
memset(pll_settings, 0, sizeof(*pll_settings));
+4
-4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+4
-4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
···
381
381
}
382
382
383
383
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
384
-
seg_distr[i] = -1;
384
+
seg_distr[i] = (uint32_t)-1;
385
385
386
386
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
387
-
if (seg_distr[k] != -1)
387
+
if (seg_distr[k] != (uint32_t)-1)
388
388
hw_points += (1 << seg_distr[k]);
389
389
}
390
390
···
565
565
566
566
567
567
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
568
-
seg_distr[i] = -1;
568
+
seg_distr[i] = (uint32_t)-1;
569
569
/* 12 segments
570
570
* segments are from 2^-12 to 0
571
571
*/
···
573
573
seg_distr[i] = 4;
574
574
575
575
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
576
-
if (seg_distr[k] != -1)
576
+
if (seg_distr[k] != (uint32_t)-1)
577
577
hw_points += (1 << seg_distr[k]);
578
578
}
579
579
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
···
746
746
src_width, dest_width);
747
747
748
748
if (dc_fixpt_floor(tmp_h_ratio_luma) == 8)
749
-
h_ratio_luma = -1;
749
+
h_ratio_luma = (uint32_t)-1;
750
750
else
751
751
h_ratio_luma = dc_fixpt_u3d19(tmp_h_ratio_luma) << 5;
752
752
···
824
824
src_height, dest_height);
825
825
826
826
if (dc_fixpt_floor(tmp_v_ratio_luma) == 8)
827
-
v_ratio_luma = -1;
827
+
v_ratio_luma = (uint32_t)-1;
828
828
else
829
829
v_ratio_luma = dc_fixpt_u3d19(tmp_v_ratio_luma) << 5;
830
830
+2
-2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
···
159
159
}
160
160
161
161
for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
162
-
seg_distr[i] = -1;
162
+
seg_distr[i] = (uint32_t)-1;
163
163
164
164
for (k = 0; k < MAX_REGIONS_NUMBER; k++) {
165
-
if (seg_distr[k] != -1)
165
+
if (seg_distr[k] != (uint32_t)-1)
166
166
hw_points += (1 << seg_distr[k]);
167
167
}
168
168
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
+1
-1
drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
···
76
76
.line_buffer_size_bits = 589824,
77
77
.max_line_buffer_lines = 12,
78
78
.IsLineBufferBppFixed = 0,
79
-
.LineBufferFixedBpp = -1,
79
+
.LineBufferFixedBpp = (unsigned int)-1,
80
80
.writeback_luma_buffer_size_kbytes = 12,
81
81
.writeback_chroma_buffer_size_kbytes = 8,
82
82
.max_num_dpp = 4,
+6
-6
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+6
-6
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
···
488
488
seg_distr[8] = 4;
489
489
seg_distr[9] = 4;
490
490
seg_distr[10] = 0;
491
-
seg_distr[11] = -1;
492
-
seg_distr[12] = -1;
493
-
seg_distr[13] = -1;
494
-
seg_distr[14] = -1;
495
-
seg_distr[15] = -1;
491
+
seg_distr[11] = (uint32_t)-1;
492
+
seg_distr[12] = (uint32_t)-1;
493
+
seg_distr[13] = (uint32_t)-1;
494
+
seg_distr[14] = (uint32_t)-1;
495
+
seg_distr[15] = (uint32_t)-1;
496
496
}
497
497
498
498
for (k = 0; k < 16; k++) {
499
-
if (seg_distr[k] != -1)
499
+
if (seg_distr[k] != (uint32_t)-1)
500
500
hw_points += (1 << seg_distr[k]);
501
501
}
502
502
+5
-5
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+5
-5
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
···
92
92
.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
93
93
.enable_value = {\
94
94
DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
95
-
~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
95
+
(uint32_t)~DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK\
96
96
},\
97
97
.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
98
98
.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
···
107
107
.enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
108
108
.enable_value = {\
109
109
DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
110
-
~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
110
+
(uint32_t)~DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK },\
111
111
.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
112
112
.ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
113
113
.ack_value = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
···
121
121
GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
122
122
.enable_value = {\
123
123
GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
124
-
~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
124
+
(uint32_t)~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
125
125
.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
126
126
.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
127
127
.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
···
136
136
CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
137
137
.enable_value = {\
138
138
CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
139
-
~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
139
+
(uint32_t)~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
140
140
.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
141
141
.ack_mask =\
142
142
CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
···
152
152
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
153
153
.enable_value = {\
154
154
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
155
-
~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
155
+
(uint32_t)~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
156
156
.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
157
157
.ack_mask =\
158
158
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
···
79
79
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
80
80
.enable_value = {\
81
81
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
82
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
82
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
83
83
},\
84
84
.ack_reg = SRI(reg2, block, reg_num),\
85
85
.ack_mask = \
+5
-5
drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
+5
-5
drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c
···
68
68
.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
69
69
.enable_value = {\
70
70
DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
71
-
~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
71
+
(uint32_t)~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\
72
72
},\
73
73
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
74
74
.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
···
83
83
.enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
84
84
.enable_value = {\
85
85
DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
86
-
~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
86
+
(uint32_t)~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\
87
87
.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
88
88
.ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
89
89
.ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
···
98
98
GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
99
99
.enable_value = {\
100
100
GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\
101
-
~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
101
+
(uint32_t)~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\
102
102
.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\
103
103
.ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
104
104
.ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
···
113
113
CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
114
114
.enable_value = {\
115
115
CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\
116
-
~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
116
+
(uint32_t)~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\
117
117
.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\
118
118
.ack_mask =\
119
119
CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\
···
129
129
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
130
130
.enable_value = {\
131
131
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\
132
-
~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
132
+
(uint32_t)~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\
133
133
.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
134
134
.ack_mask =\
135
135
CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
···
176
176
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177
177
.enable_value = {\
178
178
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
179
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
180
180
},\
181
181
.ack_reg = SRI(reg2, block, reg_num),\
182
182
.ack_mask = \
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
···
179
179
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
180
180
.enable_value = {\
181
181
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
182
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
182
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
183
183
},\
184
184
.ack_reg = SRI(reg2, block, reg_num),\
185
185
.ack_mask = \
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
···
189
189
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
190
190
.enable_value = {\
191
191
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
192
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
193
193
},\
194
194
.ack_reg = SRI(reg2, block, reg_num),\
195
195
.ack_mask = \
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
···
196
196
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197
197
.enable_value = {\
198
198
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200
200
},\
201
201
.ack_reg = SRI(reg2, block, reg_num),\
202
202
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c
···
180
180
.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
181
181
.enable_value = {\
182
182
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
183
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
183
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
184
184
},\
185
185
.ack_reg = SRI(reg2, block, reg_num),\
186
186
.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
···
199
199
reg1 ## __ ## mask1 ## _MASK,\
200
200
.enable_value = {\
201
201
reg1 ## __ ## mask1 ## _MASK,\
202
-
~reg1 ## __ ## mask1 ## _MASK \
202
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
203
203
},\
204
204
.ack_reg = SRI_DMUB(reg2),\
205
205
.ack_mask = \
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
+1
-1
drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c
···
123
123
.enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
124
124
.enable_value = {\
125
125
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
126
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
126
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
127
127
},\
128
128
.ack_reg = SRI(reg2, block, reg_num),\
129
129
.ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
···
184
184
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
185
185
.enable_value = {\
186
186
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
187
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
188
188
},\
189
189
.ack_reg = SRI(reg2, block, reg_num),\
190
190
.ack_mask = \
···
198
198
reg1 ## __ ## mask1 ## _MASK,\
199
199
.enable_value = {\
200
200
reg1 ## __ ## mask1 ## _MASK,\
201
-
~reg1 ## __ ## mask1 ## _MASK \
201
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
202
202
},\
203
203
.ack_reg = SRI_DMUB(reg2),\
204
204
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c
···
186
186
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
187
187
.enable_value = {\
188
188
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
189
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
189
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
190
190
},\
191
191
.ack_reg = SRI(reg2, block, reg_num),\
192
192
.ack_mask = \
···
200
200
reg1 ## __ ## mask1 ## _MASK,\
201
201
.enable_value = {\
202
202
reg1 ## __ ## mask1 ## _MASK,\
203
-
~reg1 ## __ ## mask1 ## _MASK \
203
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
204
204
},\
205
205
.ack_reg = SRI_DMUB(reg2),\
206
206
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
···
191
191
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
192
192
.enable_value = {\
193
193
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
194
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
195
195
},\
196
196
.ack_reg = SRI(reg2, block, reg_num),\
197
197
.ack_mask = \
···
205
205
reg1 ## __ ## mask1 ## _MASK,\
206
206
.enable_value = {\
207
207
reg1 ## __ ## mask1 ## _MASK,\
208
-
~reg1 ## __ ## mask1 ## _MASK \
208
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
209
209
},\
210
210
.ack_reg = SRI_DMUB(reg2),\
211
211
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c
···
195
195
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196
196
.enable_value = {\
197
197
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
198
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199
199
},\
200
200
.ack_reg = SRI(reg2, block, reg_num),\
201
201
.ack_mask = \
···
209
209
reg1 ## __ ## mask1 ## _MASK,\
210
210
.enable_value = {\
211
211
reg1 ## __ ## mask1 ## _MASK,\
212
-
~reg1 ## __ ## mask1 ## _MASK \
212
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
213
213
},\
214
214
.ack_reg = SRI_DMUB(reg2),\
215
215
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c
···
184
184
REG_STRUCT[base + reg_num].enable_value[0] = \
185
185
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
186
186
REG_STRUCT[base + reg_num].enable_value[1] = \
187
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
187
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
188
188
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
189
189
REG_STRUCT[base + reg_num].ack_mask = \
190
190
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
···
198
198
REG_STRUCT[base].enable_value[0] = \
199
199
reg1 ## __ ## mask1 ## _MASK,\
200
200
REG_STRUCT[base].enable_value[1] = \
201
-
~reg1 ## __ ## mask1 ## _MASK, \
201
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
202
202
REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
203
203
REG_STRUCT[base].ack_mask = \
204
204
reg2 ## __ ## mask2 ## _MASK,\
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c
···
163
163
REG_STRUCT[base + reg_num].enable_value[0] = \
164
164
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
165
165
REG_STRUCT[base + reg_num].enable_value[1] = \
166
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
166
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
167
167
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
168
168
REG_STRUCT[base + reg_num].ack_mask = \
169
169
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
···
177
177
REG_STRUCT[base].enable_value[0] = \
178
178
reg1 ## __ ## mask1 ## _MASK,\
179
179
REG_STRUCT[base].enable_value[1] = \
180
-
~reg1 ## __ ## mask1 ## _MASK, \
180
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
181
181
REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
182
182
REG_STRUCT[base].ack_mask = \
183
183
reg2 ## __ ## mask2 ## _MASK,\
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c
···
162
162
REG_STRUCT[base + reg_num].enable_value[0] = \
163
163
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
164
164
REG_STRUCT[base + reg_num].enable_value[1] = \
165
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
165
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
166
166
REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
167
167
REG_STRUCT[base + reg_num].ack_mask = \
168
168
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
···
176
176
REG_STRUCT[base].enable_value[0] = \
177
177
reg1 ## __ ## mask1 ## _MASK,\
178
178
REG_STRUCT[base].enable_value[1] = \
179
-
~reg1 ## __ ## mask1 ## _MASK, \
179
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK, \
180
180
REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
181
181
REG_STRUCT[base].ack_mask = \
182
182
reg2 ## __ ## mask2 ## _MASK,\
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c
···
175
175
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
176
176
.enable_value = {\
177
177
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
178
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
178
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
179
179
},\
180
180
.ack_reg = SRI(reg2, block, reg_num),\
181
181
.ack_mask = \
···
189
189
reg1 ## __ ## mask1 ## _MASK,\
190
190
.enable_value = {\
191
191
reg1 ## __ ## mask1 ## _MASK,\
192
-
~reg1 ## __ ## mask1 ## _MASK \
192
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
193
193
},\
194
194
.ack_reg = SRI_DMUB(reg2),\
195
195
.ack_mask = \
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
+2
-2
drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c
···
173
173
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
174
174
.enable_value = {\
175
175
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
176
-
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
176
+
(uint32_t)~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
177
177
},\
178
178
.ack_reg = SRI(reg2, block, reg_num),\
179
179
.ack_mask = \
···
187
187
reg1 ## __ ## mask1 ## _MASK,\
188
188
.enable_value = {\
189
189
reg1 ## __ ## mask1 ## _MASK,\
190
-
~reg1 ## __ ## mask1 ## _MASK \
190
+
(uint32_t)~reg1 ## __ ## mask1 ## _MASK \
191
191
},\
192
192
.ack_reg = SRI_DMUB(reg2),\
193
193
.ack_mask = \
+1
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+1
-1
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
+2
-2
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c
···
1039
1039
1040
1040
pool->base.res_cap = &res_cap;
1041
1041
pool->base.funcs = &dce100_res_pool_funcs;
1042
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1042
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1043
1043
1044
1044
bp = ctx->dc_bios;
1045
1045
···
1111
1111
/*************************************************
1112
1112
* Resource + asic cap harcoding *
1113
1113
*************************************************/
1114
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1114
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1115
1115
pool->base.pipe_count = res_cap.num_timing_generator;
1116
1116
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1117
1117
dc->caps.max_downscale_ratio = 200;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
···
1240
1240
/*************************************************
1241
1241
* Resource + asic cap harcoding *
1242
1242
*************************************************/
1243
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1243
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1244
1244
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1245
1245
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1246
1246
dc->caps.max_downscale_ratio = 200;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c
···
1081
1081
/* TODO: Fill more data from GreenlandAsicCapability.cpp */
1082
1082
pool->base.pipe_count = res_cap.num_timing_generator;
1083
1083
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1084
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1084
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1085
1085
1086
1086
dc->caps.max_downscale_ratio = 200;
1087
1087
dc->caps.i2c_speed_in_khz = 100;
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
+3
-3
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c
···
934
934
/*************************************************
935
935
* Resource + asic cap harcoding *
936
936
*************************************************/
937
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
937
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
938
938
pool->base.pipe_count = res_cap.num_timing_generator;
939
939
pool->base.timing_generator_count = res_cap.num_timing_generator;
940
940
dc->caps.max_downscale_ratio = 200;
···
1137
1137
/*************************************************
1138
1138
* Resource + asic cap harcoding *
1139
1139
*************************************************/
1140
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1140
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1141
1141
pool->base.pipe_count = res_cap_81.num_timing_generator;
1142
1142
pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1143
1143
dc->caps.max_downscale_ratio = 200;
···
1337
1337
/*************************************************
1338
1338
* Resource + asic cap harcoding *
1339
1339
*************************************************/
1340
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1340
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1341
1341
pool->base.pipe_count = res_cap_83.num_timing_generator;
1342
1342
pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1343
1343
dc->caps.max_downscale_ratio = 200;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
···
1346
1346
/*************************************************
1347
1347
* Resource + asic cap harcoding *
1348
1348
*************************************************/
1349
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1349
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1350
1350
1351
1351
/* max pipe num for ASIC before check pipe fuses */
1352
1352
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
···
2429
2429
/*************************************************
2430
2430
* Resource + asic cap harcoding *
2431
2431
*************************************************/
2432
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2432
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2433
2433
2434
2434
dc->caps.max_downscale_ratio = 200;
2435
2435
dc->caps.i2c_speed_in_khz = 100;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
···
1408
1408
/*************************************************
1409
1409
* Resource + asic cap harcoding *
1410
1410
*************************************************/
1411
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1411
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1412
1412
1413
1413
/* max pipe num for ASIC before check pipe fuses */
1414
1414
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
···
2297
2297
/*************************************************
2298
2298
* Resource + asic cap harcoding *
2299
2299
*************************************************/
2300
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2300
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2301
2301
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2302
2302
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2303
2303
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
···
1428
1428
/*************************************************
1429
1429
* Resource + asic cap harcoding *
1430
1430
*************************************************/
1431
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1431
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1432
1432
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1433
1433
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1434
1434
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
···
1218
1218
/*************************************************
1219
1219
* Resource + asic cap harcoding *
1220
1220
*************************************************/
1221
-
pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1221
+
pool->underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1222
1222
pool->pipe_count = pool->res_cap->num_timing_generator;
1223
1223
pool->mpcc_count = pool->res_cap->num_timing_generator;
1224
1224
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
···
1159
1159
/*************************************************
1160
1160
* Resource + asic cap harcoding *
1161
1161
*************************************************/
1162
-
pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1162
+
pool->underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1163
1163
pool->pipe_count = pool->res_cap->num_timing_generator;
1164
1164
pool->mpcc_count = pool->res_cap->num_timing_generator;
1165
1165
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
···
1894
1894
/*************************************************
1895
1895
* Resource + asic cap harcoding *
1896
1896
*************************************************/
1897
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1897
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1898
1898
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1899
1899
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1900
1900
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
···
1827
1827
/*************************************************
1828
1828
* Resource + asic cap harcoding *
1829
1829
*************************************************/
1830
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1830
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1831
1831
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1832
1832
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1833
1833
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
···
1866
1866
/*************************************************
1867
1867
* Resource + asic cap harcoding *
1868
1868
*************************************************/
1869
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1869
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1870
1870
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1871
1871
1872
1872
/* Enable 4to1MPC by default */
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
···
1741
1741
/*************************************************
1742
1742
* Resource + asic cap harcoding *
1743
1743
*************************************************/
1744
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1744
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1745
1745
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1746
1746
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1747
1747
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
···
2191
2191
/*************************************************
2192
2192
* Resource + asic cap harcoding *
2193
2193
*************************************************/
2194
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2194
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2195
2195
pool->base.timing_generator_count = num_pipes;
2196
2196
pool->base.pipe_count = num_pipes;
2197
2197
pool->base.mpcc_count = num_pipes;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
···
1695
1695
/*************************************************
1696
1696
* Resource + asic cap harcoding *
1697
1697
*************************************************/
1698
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1698
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1699
1699
pool->base.timing_generator_count = num_pipes;
1700
1700
pool->base.pipe_count = num_pipes;
1701
1701
pool->base.mpcc_count = num_pipes;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
···
1850
1850
/*************************************************
1851
1851
* Resource + asic cap harcoding *
1852
1852
*************************************************/
1853
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1853
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1854
1854
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1855
1855
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1856
1856
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
···
1823
1823
/*************************************************
1824
1824
* Resource + asic cap harcoding *
1825
1825
*************************************************/
1826
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1826
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1827
1827
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1828
1828
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1829
1829
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
···
1826
1826
/*************************************************
1827
1827
* Resource + asic cap harcoding *
1828
1828
*************************************************/
1829
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1829
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1830
1830
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1831
1831
pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1832
1832
dc->caps.max_downscale_ratio = 600;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
···
1915
1915
/*************************************************
1916
1916
* Resource + asic cap harcoding *
1917
1917
*************************************************/
1918
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1918
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1919
1919
pool->base.timing_generator_count = num_pipes;
1920
1920
pool->base.pipe_count = num_pipes;
1921
1921
pool->base.mpcc_count = num_pipes;
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+1
-1
drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
···
1864
1864
/*************************************************
1865
1865
* Resource + asic cap harcoding *
1866
1866
*************************************************/
1867
-
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1867
+
pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
1868
1868
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1869
1869
pool->base.pipe_count = num_pipes;
1870
1870
pool->base.mpcc_count = num_pipes;