Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: eliminate clock manager code duplication
[Why]
Clock manager contained significant duplicate code between
variants with identical logic for functions using only SMU
calls or shared registers. This increases maintenance overhead
and potential for bugs.
[How]
Expose clock constants and internal functions in header for
sharing. Remove duplicate implementations and update function
pointers to use shared functions. Refactor remaining
variant-specific functions to use shared constants and helper
functions. Add compatibility comments for hardware differences.
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Gabe Teeger <gabe.teeger@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Gabe Teeger
and committed by
Alex Deucher
8424ee7d
d77ff733
+21
-13
+14
-12
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+14
-12
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
···
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#define DC_LOGGER_INIT(logger) \
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struct dal_logger *dc_logger = logger
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-
#define DCN42_CLKIP_REFCLK 48000
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-
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
···
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dcn42_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
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clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
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}
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+
/* Only attempt to enable dtbclk if currently disabled AND new state requests it.
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* For dcn42b (no dtbclk hardware), init_clk_states sets dtbclk_en=false and
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* new_clocks->dtbclk_en should always be false, so this block never executes.
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*/
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if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
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int actual_dtbclk = 0;
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···
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}
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/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
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if (!dc->debug.disable_dtb_ref_clk_switch &&
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if (!dc->debug.disable_dtb_ref_clk_switch && new_clocks->dtbclk_en &&
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should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
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clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
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dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
···
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clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
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}
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-
static void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
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void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
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struct dcn42_smu_dpm_clks *smu_dpm_clks)
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{
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DpmClocks_t_dcn42 *table = smu_dpm_clks->dpm_clks;
···
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}
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-
static void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr,
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void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr,
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struct dc_state *context,
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bool safe_to_lower)
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{
···
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// Both fclk and ref_dppclk run on the same scemi clock.
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clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
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/* TODO: set dtbclk in correct place */
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clk_mgr->clks.dtbclk_en = true;
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-
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dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
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if (clk_mgr->clks.dtbclk_en) {
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dcn42_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
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} else {
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clk_mgr->clks.ref_dtbclk_khz = 0;
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}
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dcn42_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
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-
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-
dcn42_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
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}
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unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)
···
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return 0;
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}
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-
static int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
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int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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uint32_t dispclk_wdivider;
···
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return clk_mgr->smu_present;
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}
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-
static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int)
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+
void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int)
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{
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struct clk_mgr *clk_mgr_base = &clk_mgr_int->base;
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struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 };
+7
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h
+7
-1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h
···
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#include "clk_mgr_internal.h"
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#define NUM_CLOCK_SOURCES 5
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#define DCN42_CLKIP_REFCLK 48000
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struct dcn42_watermarks;
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···
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void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base);
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unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
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bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base);
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bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);
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int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps);
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void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower);
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void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz);
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bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);
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-
bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);
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struct dcn42_smu_dpm_clks; /* Forward declaration for pointer parameter below */
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void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn42_smu_dpm_clks *smu_dpm_clks);
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void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int);
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void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, struct dc_state *context, bool safe_to_lower);
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int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base);
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#endif //__DCN42_CLK_MGR_H__