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drm/i915: Extract DSPCLK_GATE_D from i915_reg to display

Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c not to include i915_reg.h.

v3: Update commit header and message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-5-uma.shankar@intel.com

Uma Shankar 27442c5f b425c278

+50 -51
+50
drivers/gpu/drm/i915/display/intel_display_regs.h
··· 160 160 161 161 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 162 162 163 + #define DSPCLK_GATE_D _MMIO(0x6200) 164 + #define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200) 165 + # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 166 + # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 167 + # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 168 + # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 169 + # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 170 + # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 171 + # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 172 + # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 173 + # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 174 + # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 175 + # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 176 + # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 177 + # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 178 + # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 179 + # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 180 + # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 181 + # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 182 + # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 183 + # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 184 + # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 185 + # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 186 + # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 187 + # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 188 + # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 189 + # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 190 + # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 191 + # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 192 + # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 193 + # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 194 + /* 195 + * This bit must be set on the 830 to prevent hangs when turning off the 196 + * overlay scaler. 197 + */ 198 + # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 199 + # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 200 + # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 201 + # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 202 + # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 203 + 163 204 /* Additional CHV pll/phy registers */ 164 205 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 165 206 #define DPLL_PORTD_READY_MASK (0xf) ··· 2971 2930 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 2972 2931 #define LPT_PWM_GRANULARITY (1 << 5) 2973 2932 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 2933 + 2934 + #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 2935 + #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 2936 + #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 2937 + #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 2938 + #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 2939 + #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 2940 + #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 2941 + #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 2974 2942 2975 2943 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 2976 2944 #define GEN4_TIMESTAMP _MMIO(0x2358)
-1
drivers/gpu/drm/i915/display/intel_gmbus.c
··· 35 35 #include <drm/drm_print.h> 36 36 #include <drm/display/drm_hdcp_helper.h> 37 37 38 - #include "i915_reg.h" 39 38 #include "intel_de.h" 40 39 #include "intel_display_regs.h" 41 40 #include "intel_display_types.h"
-50
drivers/gpu/drm/i915/i915_reg.h
··· 613 613 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 614 614 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 615 615 616 - #define DSPCLK_GATE_D _MMIO(0x6200) 617 - #define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200) 618 - # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 619 - # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 620 - # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 621 - # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 622 - # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 623 - # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 624 - # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 625 - # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 626 - # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 627 - # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 628 - # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 629 - # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 630 - # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 631 - # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 632 - # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 633 - # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 634 - # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 635 - # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 636 - # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 637 - # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 638 - # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 639 - # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 640 - # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 641 - # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 642 - # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 643 - # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 644 - # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 645 - # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 646 - # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 647 - /* 648 - * This bit must be set on the 830 to prevent hangs when turning off the 649 - * overlay scaler. 650 - */ 651 - # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 652 - # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 653 - # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 654 - # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 655 - # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 656 - 657 616 #define RENCLK_GATE_D1 _MMIO(0x6204) 658 617 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 659 618 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ ··· 948 989 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 949 990 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10) 950 991 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4) 951 - 952 - #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 953 - #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 954 - #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 955 - #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 956 - #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 957 - #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 958 - #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 959 - #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 960 992 961 993 #define VLV_PMWGICZ _MMIO(0x1300a4) 962 994