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phy: exynos5-usbdrd: convert udelay() to fsleep()

The timers-howto recommends using usleep_range() and friends anytime
waiting for >= ~10us is required. Doing so can help the timer subsystem
a lot to coalesce wakeups.

Additionally, fsleep() exists as a convenient wrapper so we do not have
to think about which exact sleeping function is required in which case.

Convert all udelay() calls in this driver to use fsleep() to follow the
recommendataion.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-2-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

André Draszik and committed by
Vinod Koul 27f3d3f6 2a0dc34b

+4 -4
+4 -4
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 448 448 449 449 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 450 450 451 - udelay(10); 451 + fsleep(10); 452 452 453 453 reg &= ~PHYCLKRST_PORTRESET; 454 454 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); ··· 779 779 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); 780 780 781 781 /* Finish PHY reset (POR=low) */ 782 - udelay(10); /* required before doing POR=low */ 782 + fsleep(10); /* required before doing POR=low */ 783 783 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 784 784 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); 785 785 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 786 - udelay(75); /* required after POR=low for guaranteed PHY clock */ 786 + fsleep(75); /* required after POR=low for guaranteed PHY clock */ 787 787 788 788 /* Disable single ended signal out */ 789 789 reg = readl(regs_base + EXYNOS850_DRD_HSP); ··· 836 836 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 837 837 reg |= CLKRST_LINK_SW_RST; 838 838 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 839 - udelay(10); /* required before doing POR=low */ 839 + fsleep(10); /* required before doing POR=low */ 840 840 reg &= ~CLKRST_LINK_SW_RST; 841 841 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 842 842