Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/lt_phy: Enable dpll framework for xe3plpd
xe3plpd platform is supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.
Finally, all required hooks are now in place so initialize
PLL manager for xe3plpd platform and remove the redirections
to the legacy code paths for clock enable/disable as well as
state mismatch checks that are no longer needed.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312101415.2669387-1-mika.kahola@intel.com
+6
-35
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
···
5285
5285
if (HAS_LT_PHY(display)) {
5286
5286
encoder->enable_clock = intel_mtl_pll_enable_clock;
5287
5287
encoder->disable_clock = intel_mtl_pll_disable_clock;
5288
-
encoder->port_pll_type = intel_mtl_port_pll_type;
5288
+
encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5289
5289
if (intel_encoder_is_tc(encoder))
5290
5290
encoder->get_config = mtl_ddi_tc_phy_get_config;
5291
5291
else
-31
drivers/gpu/drm/i915/display/intel_display.c
-31
drivers/gpu/drm/i915/display/intel_display.c
···
5063
5063
!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
5064
5064
}
5065
5065
5066
-
static void
5067
-
pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
5068
-
const struct intel_crtc *crtc,
5069
-
const char *name,
5070
-
const struct intel_lt_phy_pll_state *a,
5071
-
const struct intel_lt_phy_pll_state *b)
5072
-
{
5073
-
char *chipname = "LTPHY";
5074
-
5075
-
pipe_config_mismatch(p, fastset, crtc, name, chipname);
5076
-
5077
-
drm_printf(p, "expected:\n");
5078
-
intel_lt_phy_dump_hw_state(p, a);
5079
-
drm_printf(p, "found:\n");
5080
-
intel_lt_phy_dump_hw_state(p, b);
5081
-
}
5082
-
5083
5066
bool
5084
5067
intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5085
5068
const struct intel_crtc_state *pipe_config,
···
5173
5190
pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5174
5191
¤t_config->name, \
5175
5192
&pipe_config->name); \
5176
-
ret = false; \
5177
-
} \
5178
-
} while (0)
5179
-
5180
-
#define PIPE_CONF_CHECK_PLL_LT(name) do { \
5181
-
if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \
5182
-
&pipe_config->name)) { \
5183
-
pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5184
-
¤t_config->name, \
5185
-
&pipe_config->name); \
5186
5193
ret = false; \
5187
5194
} \
5188
5195
} while (0)
···
5402
5429
/* FIXME convert everything over the dpll_mgr */
5403
5430
if (display->dpll.mgr || HAS_GMCH(display))
5404
5431
PIPE_CONF_CHECK_PLL(dpll_hw_state);
5405
-
5406
-
/* FIXME convert MTL+ platforms over to dpll_mgr */
5407
-
if (HAS_LT_PHY(display))
5408
-
PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
5409
5432
5410
5433
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5411
5434
PIPE_CONF_CHECK_X(dsi_pll.div);
+4
-3
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+4
-3
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
4724
4724
return intel_lt_phy_pll_compare_hw_state(a, b);
4725
4725
}
4726
4726
4727
-
__maybe_unused
4728
4727
static const struct intel_dpll_mgr xe3plpd_pll_mgr = {
4729
4728
.dpll_info = xe3plpd_plls,
4730
4729
.compute_dplls = xe3plpd_compute_dplls,
···
4749
4750
4750
4751
mutex_init(&display->dpll.lock);
4751
4752
4752
-
if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
4753
-
/* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */
4753
+
if (display->platform.dg2)
4754
+
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
4754
4755
dpll_mgr = NULL;
4756
+
else if (DISPLAY_VER(display) >= 35)
4757
+
dpll_mgr = &xe3plpd_pll_mgr;
4755
4758
else if (DISPLAY_VER(display) >= 14)
4756
4759
dpll_mgr = &mtl_pll_mgr;
4757
4760
else if (display->platform.alderlake_p)