drm/msm/a6xx: Use packed structs for HFI

HFI related structs define the ABI between the KMD and the GMU firmware.
So, use packed structures to avoid unintended compiler inserted padding.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714669/
Message-ID: <20260327-a8xx-gpu-batch2-v2-9-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by

Rob Clark 2 months ago 29c1d7e5 61957ab9

+20 -20

1 changed file

expand all

drivers

gpu

drm

msm

adreno

a6xx_hfi.h

+20 -20

drivers/gpu/drm/msm/adreno/a6xx_hfi.h

··· 13 13 u32 qhdr_size; /* Size of the queue headers */ 14 14 u32 num_queues; /* Number of total queues */ 15 15 u32 active_queues; /* Number of active queues */ 16 - }; 16 + } __packed; 17 17 18 18 struct a6xx_hfi_queue_header { 19 19 u32 status; ··· 28 28 u32 tx_request; 29 29 u32 read_index; 30 30 u32 write_index; 31 - }; 31 + } __packed; 32 32 33 33 struct a6xx_hfi_queue { 34 34 struct a6xx_hfi_queue_header *header; ··· 74 74 u32 ret_header; 75 75 u32 error; 76 76 u32 payload[HFI_RESPONSE_PAYLOAD_SIZE]; 77 - }; 77 + } __packed; 78 78 79 79 #define HFI_F2H_MSG_ERROR 100 80 80 ··· 82 82 u32 header; 83 83 u32 code; 84 84 u32 payload[2]; 85 - }; 85 + } __packed; 86 86 87 87 #define HFI_H2F_MSG_INIT 0 88 88 ··· 92 92 u32 dbg_buffer_addr; 93 93 u32 dbg_buffer_size; 94 94 u32 boot_state; 95 - }; 95 + } __packed; 96 96 97 97 #define HFI_H2F_MSG_FW_VERSION 1 98 98 99 99 struct a6xx_hfi_msg_fw_version { 100 100 u32 header; 101 101 u32 supported_version; 102 - }; 102 + } __packed; 103 103 104 104 #define HFI_H2F_MSG_PERF_TABLE 4 105 105 106 106 struct perf_level { 107 107 u32 vote; 108 108 u32 freq; 109 - }; 109 + } __packed; 110 110 111 111 struct perf_gx_level { 112 112 u32 vote; 113 113 u32 acd; 114 114 u32 freq; 115 - }; 115 + } __packed; 116 116 117 117 struct a6xx_hfi_msg_perf_table_v1 { 118 118 u32 header; ··· 121 121 122 122 struct perf_level gx_votes[16]; 123 123 struct perf_level cx_votes[4]; 124 - }; 124 + } __packed; 125 125 126 126 struct a6xx_hfi_msg_perf_table { 127 127 u32 header; ··· 130 130 131 131 struct perf_gx_level gx_votes[16]; 132 132 struct perf_level cx_votes[4]; 133 - }; 133 + } __packed; 134 134 135 135 #define HFI_H2F_MSG_BW_TABLE 3 136 136 ··· 145 145 u32 cnoc_cmds_data[2][6]; 146 146 u32 ddr_cmds_addrs[8]; 147 147 u32 ddr_cmds_data[16][8]; 148 - }; 148 + } __packed; 149 149 150 150 #define HFI_H2F_MSG_TEST 5 151 151 152 152 struct a6xx_hfi_msg_test { 153 153 u32 header; 154 - }; 154 + } __packed; 155 155 156 156 #define HFI_H2F_MSG_ACD 7 157 157 #define MAX_ACD_STRIDE 2 ··· 163 163 u32 stride; 164 164 u32 num_levels; 165 165 u32 data[16 * MAX_ACD_STRIDE]; 166 - }; 166 + } __packed; 167 167 168 168 #define HFI_H2F_MSG_START 10 169 169 170 170 struct a6xx_hfi_msg_start { 171 171 u32 header; 172 - }; 172 + } __packed; 173 173 174 174 #define HFI_H2F_FEATURE_CTRL 11 175 175 ··· 178 178 u32 feature; 179 179 u32 enable; 180 180 u32 data; 181 - }; 181 + } __packed; 182 182 183 183 #define HFI_H2F_MSG_CORE_FW_START 14 184 184 185 185 struct a6xx_hfi_msg_core_fw_start { 186 186 u32 header; 187 187 u32 handle; 188 - }; 188 + } __packed; 189 189 190 190 #define HFI_H2F_MSG_TABLE 15 191 191 ··· 193 193 u32 count; 194 194 u32 stride; 195 195 u32 data[]; 196 - }; 196 + } __packed; 197 197 198 198 struct a6xx_hfi_table { 199 199 u32 header; ··· 202 202 #define HFI_TABLE_BW_VOTE 0 203 203 #define HFI_TABLE_GPU_PERF 1 204 204 struct a6xx_hfi_table_entry entry[]; 205 - }; 205 + } __packed; 206 206 207 207 #define HFI_H2F_MSG_GX_BW_PERF_VOTE 30 208 208 ··· 211 211 u32 ack_type; 212 212 u32 freq; 213 213 u32 bw; 214 - }; 214 + } __packed; 215 215 216 216 #define AB_VOTE_MASK GENMASK(31, 16) 217 217 #define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1) ··· 224 224 u32 header; 225 225 u32 bw; 226 226 u32 freq; 227 - }; 227 + } __packed; 228 228 229 229 #endif

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