tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: add ACA support for jpeg v4.0.3

Add ACA support for jpeg v4.0.3.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Yang Wang and committed by
Alex Deucher 2a50d94b 3748c439

+86
+86
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
··· 1231 1231 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1232 1232 }; 1233 1233 1234 + static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1235 + enum aca_smu_type type, void *data) 1236 + { 1237 + struct aca_bank_info info; 1238 + u64 misc0; 1239 + int ret; 1240 + 1241 + ret = aca_bank_info_decode(bank, &info); 1242 + if (ret) 1243 + return ret; 1244 + 1245 + misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1246 + switch (type) { 1247 + case ACA_SMU_TYPE_UE: 1248 + ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1249 + 1ULL); 1250 + break; 1251 + case ACA_SMU_TYPE_CE: 1252 + ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 1253 + ACA_REG__MISC0__ERRCNT(misc0)); 1254 + break; 1255 + default: 1256 + return -EINVAL; 1257 + } 1258 + 1259 + return ret; 1260 + } 1261 + 1262 + /* reference to smu driver if header file */ 1263 + static int jpeg_v4_0_3_err_codes[] = { 1264 + 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */ 1265 + 24, 25, 26, 27, 28, 29, 30, 31 1266 + }; 1267 + 1268 + static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1269 + enum aca_smu_type type, void *data) 1270 + { 1271 + u32 instlo; 1272 + 1273 + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1274 + instlo &= GENMASK(31, 1); 1275 + 1276 + if (instlo != mmSMNAID_AID0_MCA_SMU) 1277 + return false; 1278 + 1279 + if (aca_bank_check_error_codes(handle->adev, bank, 1280 + jpeg_v4_0_3_err_codes, 1281 + ARRAY_SIZE(jpeg_v4_0_3_err_codes))) 1282 + return false; 1283 + 1284 + return true; 1285 + } 1286 + 1287 + static const struct aca_bank_ops jpeg_v4_0_3_aca_bank_ops = { 1288 + .aca_bank_parser = jpeg_v4_0_3_aca_bank_parser, 1289 + .aca_bank_is_valid = jpeg_v4_0_3_aca_bank_is_valid, 1290 + }; 1291 + 1292 + static const struct aca_info jpeg_v4_0_3_aca_info = { 1293 + .hwip = ACA_HWIP_TYPE_SMU, 1294 + .mask = ACA_ERROR_UE_MASK, 1295 + .bank_ops = &jpeg_v4_0_3_aca_bank_ops, 1296 + }; 1297 + 1298 + static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1299 + { 1300 + int r; 1301 + 1302 + r = amdgpu_ras_block_late_init(adev, ras_block); 1303 + if (r) 1304 + return r; 1305 + 1306 + r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, 1307 + &jpeg_v4_0_3_aca_info, NULL); 1308 + if (r) 1309 + goto late_fini; 1310 + 1311 + return 0; 1312 + 1313 + late_fini: 1314 + amdgpu_ras_block_late_fini(adev, ras_block); 1315 + 1316 + return r; 1317 + } 1318 + 1234 1319 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1235 1320 .ras_block = { 1236 1321 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1322 + .ras_late_init = jpeg_v4_0_3_ras_late_init, 1237 1323 }, 1238 1324 }; 1239 1325