Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
For DDI initialization get encoder configuration for C10 and C20
chips.
v2: Get configuration either for a C10 or on the PTL port B
eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
case as "non_tc_phy" instead of "c10phy".
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-31-mika.kahola@intel.com
+75
-6
+75
-6
drivers/gpu/drm/i915/display/intel_ddi.c
+75
-6
drivers/gpu/drm/i915/display/intel_ddi.c
···
4270
4270
intel_ddi_get_config(encoder, crtc_state);
4271
4271
}
4272
4272
4273
+
static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4274
+
{
4275
+
return pll->info->id == DPLL_ID_ICL_TBTPLL;
4276
+
}
4277
+
4278
+
static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
4279
+
struct intel_crtc_state *crtc_state,
4280
+
enum icl_port_dpll_id port_dpll_id,
4281
+
enum intel_dpll_id pll_id)
4282
+
{
4283
+
struct intel_display *display = to_intel_display(encoder);
4284
+
struct icl_port_dpll *port_dpll;
4285
+
struct intel_dpll *pll;
4286
+
bool pll_active;
4287
+
4288
+
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4289
+
pll = intel_get_dpll_by_id(display, pll_id);
4290
+
4291
+
if (drm_WARN_ON(display->drm, !pll))
4292
+
return;
4293
+
4294
+
port_dpll->pll = pll;
4295
+
pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
4296
+
drm_WARN_ON(display->drm, !pll_active);
4297
+
4298
+
icl_set_active_port_dpll(crtc_state, port_dpll_id);
4299
+
4300
+
if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
4301
+
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4302
+
else
4303
+
crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
4304
+
&crtc_state->dpll_hw_state);
4305
+
4306
+
intel_ddi_get_config(encoder, crtc_state);
4307
+
}
4308
+
4309
+
/*
4310
+
* Get the configuration for either a port using a C10 PHY PLL, or in the case of
4311
+
* the PTL port B eDP on TypeC PHY case the configuration of a port using a C20
4312
+
* PHY PLL.
4313
+
*/
4314
+
static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
4315
+
struct intel_crtc_state *crtc_state)
4316
+
{
4317
+
struct intel_display *display = to_intel_display(encoder);
4318
+
4319
+
/* TODO: Remove when the PLL manager is in place. */
4320
+
mtl_ddi_get_config(encoder, crtc_state);
4321
+
return;
4322
+
4323
+
mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
4324
+
mtl_port_to_pll_id(display, encoder->port));
4325
+
}
4326
+
4327
+
static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
4328
+
struct intel_crtc_state *crtc_state)
4329
+
{
4330
+
struct intel_display *display = to_intel_display(encoder);
4331
+
4332
+
/* TODO: Remove when the PLL manager is in place. */
4333
+
mtl_ddi_get_config(encoder, crtc_state);
4334
+
return;
4335
+
4336
+
if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
4337
+
mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
4338
+
DPLL_ID_ICL_TBTPLL);
4339
+
else
4340
+
mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY,
4341
+
mtl_port_to_pll_id(display, encoder->port));
4342
+
}
4343
+
4273
4344
static void dg2_ddi_get_config(struct intel_encoder *encoder,
4274
4345
struct intel_crtc_state *crtc_state)
4275
4346
{
···
4376
4305
{
4377
4306
intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
4378
4307
intel_ddi_get_config(encoder, crtc_state);
4379
-
}
4380
-
4381
-
static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4382
-
{
4383
-
return pll->info->id == DPLL_ID_ICL_TBTPLL;
4384
4308
}
4385
4309
4386
4310
static enum icl_port_dpll_id
···
5323
5257
encoder->enable_clock = intel_mtl_pll_enable_clock;
5324
5258
encoder->disable_clock = intel_mtl_pll_disable_clock;
5325
5259
encoder->port_pll_type = intel_mtl_port_pll_type;
5326
-
encoder->get_config = mtl_ddi_get_config;
5260
+
if (intel_encoder_is_tc(encoder))
5261
+
encoder->get_config = mtl_ddi_tc_phy_get_config;
5262
+
else
5263
+
encoder->get_config = mtl_ddi_non_tc_phy_get_config;
5327
5264
} else if (display->platform.dg2) {
5328
5265
encoder->enable_clock = intel_mpllb_enable;
5329
5266
encoder->disable_clock = intel_mpllb_disable;