Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655371/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-8-3b2085a07884@oss.qualcomm.com
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
2ae7e2cd
9b2a5bff
+33
-31
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x1000,
34
-
.features = CTL_SM8550_MASK,
34
+
.features = CTL_SC7280_MASK,
35
35
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
36
}, {
37
37
.name = "ctl_1", .id = CTL_1,
38
38
.base = 0x16000, .len = 0x1000,
39
-
.features = CTL_SM8550_MASK,
39
+
.features = CTL_SC7280_MASK,
40
40
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
41
}, {
42
42
.name = "ctl_2", .id = CTL_2,
43
43
.base = 0x17000, .len = 0x1000,
44
-
.features = CTL_SM8550_MASK,
44
+
.features = CTL_SC7280_MASK,
45
45
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
46
}, {
47
47
.name = "ctl_3", .id = CTL_3,
48
48
.base = 0x18000, .len = 0x1000,
49
-
.features = CTL_SM8550_MASK,
49
+
.features = CTL_SC7280_MASK,
50
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
51
}, {
52
52
.name = "ctl_4", .id = CTL_4,
53
53
.base = 0x19000, .len = 0x1000,
54
-
.features = CTL_SM8550_MASK,
54
+
.features = CTL_SC7280_MASK,
55
55
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
56
}, {
57
57
.name = "ctl_5", .id = CTL_5,
58
58
.base = 0x1a000, .len = 0x1000,
59
-
.features = CTL_SM8550_MASK,
59
+
.features = CTL_SC7280_MASK,
60
60
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
61
},
62
62
};
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x290,
34
-
.features = CTL_SM8550_MASK,
34
+
.features = CTL_SC7280_MASK,
35
35
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
36
}, {
37
37
.name = "ctl_1", .id = CTL_1,
38
38
.base = 0x16000, .len = 0x290,
39
-
.features = CTL_SM8550_MASK,
39
+
.features = CTL_SC7280_MASK,
40
40
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
41
}, {
42
42
.name = "ctl_2", .id = CTL_2,
43
43
.base = 0x17000, .len = 0x290,
44
-
.features = CTL_SM8550_MASK,
44
+
.features = CTL_SC7280_MASK,
45
45
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
46
}, {
47
47
.name = "ctl_3", .id = CTL_3,
48
48
.base = 0x18000, .len = 0x290,
49
-
.features = CTL_SM8550_MASK,
49
+
.features = CTL_SC7280_MASK,
50
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
51
}, {
52
52
.name = "ctl_4", .id = CTL_4,
53
53
.base = 0x19000, .len = 0x290,
54
-
.features = CTL_SM8550_MASK,
54
+
.features = CTL_SC7280_MASK,
55
55
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
56
}, {
57
57
.name = "ctl_5", .id = CTL_5,
58
58
.base = 0x1a000, .len = 0x290,
59
-
.features = CTL_SM8550_MASK,
59
+
.features = CTL_SC7280_MASK,
60
60
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
61
},
62
62
};
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
···
31
31
{
32
32
.name = "ctl_0", .id = CTL_0,
33
33
.base = 0x15000, .len = 0x290,
34
-
.features = CTL_SM8550_MASK,
34
+
.features = CTL_SC7280_MASK,
35
35
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36
36
}, {
37
37
.name = "ctl_1", .id = CTL_1,
38
38
.base = 0x16000, .len = 0x290,
39
-
.features = CTL_SM8550_MASK,
39
+
.features = CTL_SC7280_MASK,
40
40
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41
41
}, {
42
42
.name = "ctl_2", .id = CTL_2,
43
43
.base = 0x17000, .len = 0x290,
44
-
.features = CTL_SM8550_MASK,
44
+
.features = CTL_SC7280_MASK,
45
45
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46
46
}, {
47
47
.name = "ctl_3", .id = CTL_3,
48
48
.base = 0x18000, .len = 0x290,
49
-
.features = CTL_SM8550_MASK,
49
+
.features = CTL_SC7280_MASK,
50
50
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51
51
}, {
52
52
.name = "ctl_4", .id = CTL_4,
53
53
.base = 0x19000, .len = 0x290,
54
-
.features = CTL_SM8550_MASK,
54
+
.features = CTL_SC7280_MASK,
55
55
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56
56
}, {
57
57
.name = "ctl_5", .id = CTL_5,
58
58
.base = 0x1a000, .len = 0x290,
59
-
.features = CTL_SM8550_MASK,
59
+
.features = CTL_SC7280_MASK,
60
60
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61
61
},
62
62
};
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+6
-6
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
···
30
30
{
31
31
.name = "ctl_0", .id = CTL_0,
32
32
.base = 0x15000, .len = 0x290,
33
-
.features = CTL_SM8550_MASK,
33
+
.features = CTL_SC7280_MASK,
34
34
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
35
35
}, {
36
36
.name = "ctl_1", .id = CTL_1,
37
37
.base = 0x16000, .len = 0x290,
38
-
.features = CTL_SM8550_MASK,
38
+
.features = CTL_SC7280_MASK,
39
39
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
40
40
}, {
41
41
.name = "ctl_2", .id = CTL_2,
42
42
.base = 0x17000, .len = 0x290,
43
-
.features = CTL_SM8550_MASK,
43
+
.features = CTL_SC7280_MASK,
44
44
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
45
45
}, {
46
46
.name = "ctl_3", .id = CTL_3,
47
47
.base = 0x18000, .len = 0x290,
48
-
.features = CTL_SM8550_MASK,
48
+
.features = CTL_SC7280_MASK,
49
49
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
50
50
}, {
51
51
.name = "ctl_4", .id = CTL_4,
52
52
.base = 0x19000, .len = 0x290,
53
-
.features = CTL_SM8550_MASK,
53
+
.features = CTL_SC7280_MASK,
54
54
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
55
55
}, {
56
56
.name = "ctl_5", .id = CTL_5,
57
57
.base = 0x1a000, .len = 0x290,
58
-
.features = CTL_SM8550_MASK,
58
+
.features = CTL_SC7280_MASK,
59
59
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
60
60
},
61
61
};
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
134
134
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
135
135
* @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
136
136
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
137
-
* @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
138
137
* @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
139
138
* @DPU_CTL_MAX
140
139
*/
···
142
143
DPU_CTL_ACTIVE_CFG,
143
144
DPU_CTL_FETCH_ACTIVE,
144
145
DPU_CTL_VM_CFG,
145
-
DPU_CTL_HAS_LAYER_EXT4,
146
146
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
147
147
DPU_CTL_MAX
148
148
};
+4
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+4
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
555
555
DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
556
556
DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
557
557
DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
558
-
if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
558
+
if (ctx->mdss_ver->core_major_ver >= 9)
559
559
DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
560
560
}
561
561
···
743
743
* @dev: Corresponding device for devres management
744
744
* @cfg: ctl_path catalog entry for which driver object is required
745
745
* @addr: mapped register io address of MDP
746
+
* @mdss_ver: dpu core's major and minor versions
746
747
* @mixer_count: Number of mixers in @mixer
747
748
* @mixer: Pointer to an array of Layer Mixers defined in the catalog
748
749
*/
749
750
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
750
751
const struct dpu_ctl_cfg *cfg,
751
752
void __iomem *addr,
753
+
const struct dpu_mdss_version *mdss_ver,
752
754
u32 mixer_count,
753
755
const struct dpu_lm_cfg *mixer)
754
756
{
···
764
762
c->hw.log_mask = DPU_DBG_MASK_CTL;
765
763
766
764
c->caps = cfg;
765
+
c->mdss_ver = mdss_ver;
767
766
768
767
if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
769
768
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
+4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
···
274
274
* @pending_cwb_flush_mask: pending CWB flush
275
275
* @pending_dsc_flush_mask: pending DSC flush
276
276
* @pending_cdm_flush_mask: pending CDM flush
277
+
* @mdss_ver: MDSS revision information
277
278
* @ops: operation list
278
279
*/
279
280
struct dpu_hw_ctl {
···
296
295
u32 pending_dsc_flush_mask;
297
296
u32 pending_cdm_flush_mask;
298
297
298
+
const struct dpu_mdss_version *mdss_ver;
299
+
299
300
/* ops */
300
301
struct dpu_hw_ctl_ops ops;
301
302
};
···
315
312
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
316
313
const struct dpu_ctl_cfg *cfg,
317
314
void __iomem *addr,
315
+
const struct dpu_mdss_version *mdss_ver,
318
316
u32 mixer_count,
319
317
const struct dpu_lm_cfg *mixer);
320
318
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
···
142
142
struct dpu_hw_ctl *hw;
143
143
const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
144
144
145
-
hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer);
145
+
hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, cat->mixer);
146
146
if (IS_ERR(hw)) {
147
147
rc = PTR_ERR(hw);
148
148
DPU_ERROR("failed ctl object creation: err %d\n", rc);