Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull two slave-dmaengine fixes from Vinod Koul:
"One fixes the correct use of clock API in imx driver and the other
enables clock for tegra driver, which is used for other tegra driver
conversion to dmanegine in -next."
* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
dma: tegra: enable/disable dma clock
dma: imx-dma: Fix kernel crash due to missing clock conversion
+42
-12
+25
-11
drivers/dma/imx-dma.c
+25
-11
drivers/dma/imx-dma.c
···
172
172
struct device_dma_parameters dma_parms;
173
173
struct dma_device dma_device;
174
174
void __iomem *base;
175
-
struct clk *dma_clk;
175
+
struct clk *dma_ahb;
176
+
struct clk *dma_ipg;
176
177
spinlock_t lock;
177
178
struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
178
179
struct imxdma_channel channel[IMX_DMA_CHANNELS];
···
977
976
return 0;
978
977
}
979
978
980
-
imxdma->dma_clk = clk_get(NULL, "dma");
981
-
if (IS_ERR(imxdma->dma_clk))
982
-
return PTR_ERR(imxdma->dma_clk);
983
-
clk_enable(imxdma->dma_clk);
979
+
imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
980
+
if (IS_ERR(imxdma->dma_ipg)) {
981
+
ret = PTR_ERR(imxdma->dma_ipg);
982
+
goto err_clk;
983
+
}
984
+
985
+
imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
986
+
if (IS_ERR(imxdma->dma_ahb)) {
987
+
ret = PTR_ERR(imxdma->dma_ahb);
988
+
goto err_clk;
989
+
}
990
+
991
+
clk_prepare_enable(imxdma->dma_ipg);
992
+
clk_prepare_enable(imxdma->dma_ahb);
984
993
985
994
/* reset DMA module */
986
995
imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
···
999
988
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
1000
989
if (ret) {
1001
990
dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1002
-
kfree(imxdma);
1003
-
return ret;
991
+
goto err_enable;
1004
992
}
1005
993
1006
994
ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
1007
995
if (ret) {
1008
996
dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1009
997
free_irq(MX1_DMA_INT, NULL);
1010
-
kfree(imxdma);
1011
-
return ret;
998
+
goto err_enable;
1012
999
}
1013
1000
}
1014
1001
···
1103
1094
free_irq(MX1_DMA_INT, NULL);
1104
1095
free_irq(MX1_DMA_ERR, NULL);
1105
1096
}
1106
-
1097
+
err_enable:
1098
+
clk_disable_unprepare(imxdma->dma_ipg);
1099
+
clk_disable_unprepare(imxdma->dma_ahb);
1100
+
err_clk:
1107
1101
kfree(imxdma);
1108
1102
return ret;
1109
1103
}
···
1126
1114
free_irq(MX1_DMA_ERR, NULL);
1127
1115
}
1128
1116
1129
-
kfree(imxdma);
1117
+
clk_disable_unprepare(imxdma->dma_ipg);
1118
+
clk_disable_unprepare(imxdma->dma_ahb);
1119
+
kfree(imxdma);
1130
1120
1131
1121
return 0;
1132
1122
}
+17
-1
drivers/dma/tegra20-apb-dma.c
+17
-1
drivers/dma/tegra20-apb-dma.c
···
1119
1119
static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1120
1120
{
1121
1121
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1122
+
struct tegra_dma *tdma = tdc->tdma;
1123
+
int ret;
1122
1124
1123
1125
dma_cookie_init(&tdc->dma_chan);
1124
1126
tdc->config_init = false;
1125
-
return 0;
1127
+
ret = clk_prepare_enable(tdma->dma_clk);
1128
+
if (ret < 0)
1129
+
dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1130
+
return ret;
1126
1131
}
1127
1132
1128
1133
static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1129
1134
{
1130
1135
struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1136
+
struct tegra_dma *tdma = tdc->tdma;
1131
1137
1132
1138
struct tegra_dma_desc *dma_desc;
1133
1139
struct tegra_dma_sg_req *sg_req;
···
1169
1163
list_del(&sg_req->node);
1170
1164
kfree(sg_req);
1171
1165
}
1166
+
clk_disable_unprepare(tdma->dma_clk);
1172
1167
}
1173
1168
1174
1169
/* Tegra20 specific DMA controller information */
···
1262
1255
}
1263
1256
}
1264
1257
1258
+
/* Enable clock before accessing registers */
1259
+
ret = clk_prepare_enable(tdma->dma_clk);
1260
+
if (ret < 0) {
1261
+
dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1262
+
goto err_pm_disable;
1263
+
}
1264
+
1265
1265
/* Reset DMA controller */
1266
1266
tegra_periph_reset_assert(tdma->dma_clk);
1267
1267
udelay(2);
···
1278
1264
tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1279
1265
tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1280
1266
tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1267
+
1268
+
clk_disable_unprepare(tdma->dma_clk);
1281
1269
1282
1270
INIT_LIST_HEAD(&tdma->dma_dev.channels);
1283
1271
for (i = 0; i < cdata->nr_channels; i++) {