Merge tag 'irq-core-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+5 -24

arch/alpha/kernel/irq_alpha.c

··· 213 213 * The special RTC interrupt type. The interrupt itself was 214 214 * processed by PALcode, and comes in via entInt vector 1. 215 215 */ 216 - 217 - struct irqaction timer_irqaction = { 218 - .handler = rtc_timer_interrupt, 219 - .name = "timer", 220 - }; 221 - 222 216 void __init 223 - init_rtc_irq(void) 217 + init_rtc_irq(irq_handler_t handler) 224 218 { 225 219 irq_set_chip_and_handler_name(RTC_IRQ, &dummy_irq_chip, 226 220 handle_percpu_irq, "RTC"); 227 - setup_irq(RTC_IRQ, &timer_irqaction); 221 + if (!handler) 222 + handler = rtc_timer_interrupt; 223 + if (request_irq(RTC_IRQ, handler, 0, "timer", NULL)) 224 + pr_err("Failed to register timer interrupt\n"); 228 225 } 229 - 230 - /* Dummy irqactions. */ 231 - struct irqaction isa_cascade_irqaction = { 232 - .handler = no_action, 233 - .name = "isa-cascade" 234 - }; 235 - 236 - struct irqaction timer_cascade_irqaction = { 237 - .handler = no_action, 238 - .name = "timer-cascade" 239 - }; 240 - 241 - struct irqaction halt_switch_irqaction = { 242 - .handler = no_action, 243 - .name = "halt-switch" 244 - };

+2 -6

arch/alpha/kernel/irq_i8259.c

··· 82 82 void __init 83 83 init_i8259a_irqs(void) 84 84 { 85 - static struct irqaction cascade = { 86 - .handler = no_action, 87 - .name = "cascade", 88 - }; 89 - 90 85 long i; 91 86 92 87 outb(0xff, 0x21); /* mask all of 8259A-1 */ ··· 91 96 irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); 92 97 } 93 98 94 - setup_irq(2, &cascade); 99 + if (request_irq(2, no_action, 0, "cascade", NULL)) 100 + pr_err("Failed to request irq 2 (cascade)\n"); 95 101 } 96 102 97 103

+1 -6

arch/alpha/kernel/irq_impl.h

··· 21 21 extern void srm_device_interrupt(unsigned long); 22 22 extern void pyxis_device_interrupt(unsigned long); 23 23 24 - extern struct irqaction timer_irqaction; 25 - extern struct irqaction isa_cascade_irqaction; 26 - extern struct irqaction timer_cascade_irqaction; 27 - extern struct irqaction halt_switch_irqaction; 28 - 29 24 extern void init_srm_irqs(long, unsigned long); 30 25 extern void init_pyxis_irqs(unsigned long); 31 - extern void init_rtc_irq(void); 26 + extern void init_rtc_irq(irq_handler_t handler); 32 27 33 28 extern void common_init_isa_dma(void); 34 29

+2 -1

arch/alpha/kernel/irq_pyxis.c

··· 107 107 irq_set_status_flags(i, IRQ_LEVEL); 108 108 } 109 109 110 - setup_irq(16+7, &isa_cascade_irqaction); 110 + if (request_irq(16 + 7, no_action, 0, "isa-cascade", NULL)) 111 + pr_err("Failed to register isa-cascade interrupt\n"); 111 112 }

+2 -1

arch/alpha/kernel/sys_alcor.c

··· 133 133 init_i8259a_irqs(); 134 134 common_init_isa_dma(); 135 135 136 - setup_irq(16+31, &isa_cascade_irqaction); 136 + if (request_irq(16 + 31, no_action, 0, "isa-cascade", NULL)) 137 + pr_err("Failed to register isa-cascade interrupt\n"); 137 138 } 138 139 139 140

+2 -1

arch/alpha/kernel/sys_cabriolet.c

··· 112 112 } 113 113 114 114 common_init_isa_dma(); 115 - setup_irq(16+4, &isa_cascade_irqaction); 115 + if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) 116 + pr_err("Failed to register isa-cascade interrupt\n"); 116 117 } 117 118 118 119 #ifndef CONFIG_ALPHA_PC164

+2 -1

arch/alpha/kernel/sys_eb64p.c

··· 123 123 } 124 124 125 125 common_init_isa_dma(); 126 - setup_irq(16+5, &isa_cascade_irqaction); 126 + if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL)) 127 + pr_err("Failed to register isa-cascade interrupt\n"); 127 128 } 128 129 129 130 /*

+1 -1

arch/alpha/kernel/sys_marvel.c

··· 397 397 static void __init 398 398 marvel_init_rtc(void) 399 399 { 400 - init_rtc_irq(); 400 + init_rtc_irq(NULL); 401 401 } 402 402 403 403 static void

+4 -2

arch/alpha/kernel/sys_miata.c

··· 81 81 init_pyxis_irqs(0x63b0000); 82 82 83 83 common_init_isa_dma(); 84 - setup_irq(16+2, &halt_switch_irqaction); /* SRM only? */ 85 - setup_irq(16+6, &timer_cascade_irqaction); 84 + if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL)) 85 + pr_err("Failed to register halt-switch interrupt\n"); 86 + if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) 87 + pr_err("Failed to register timer-cascade interrupt\n"); 86 88 } 87 89 88 90

+2 -1

arch/alpha/kernel/sys_ruffian.c

··· 82 82 outb(0x31, 0x42); 83 83 outb(0x13, 0x42); 84 84 85 - setup_irq(0, &timer_irqaction); 85 + if (request_irq(0, rtc_timer_interrupt, 0, "timer", NULL)) 86 + pr_err("Failed to request irq 0 (timer)\n"); 86 87 } 87 88 88 89 static void

+2 -1

arch/alpha/kernel/sys_rx164.c

··· 106 106 init_i8259a_irqs(); 107 107 common_init_isa_dma(); 108 108 109 - setup_irq(16+20, &isa_cascade_irqaction); 109 + if (request_irq(16 + 20, no_action, 0, "isa-cascade", NULL)) 110 + pr_err("Failed to register isa-cascade interrupt\n"); 110 111 } 111 112 112 113

+2 -1

arch/alpha/kernel/sys_sx164.c

··· 54 54 else 55 55 init_pyxis_irqs(0xff00003f0000UL); 56 56 57 - setup_irq(16+6, &timer_cascade_irqaction); 57 + if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL)) 58 + pr_err("Failed to register timer-cascade interrupt\n"); 58 59 } 59 60 60 61 /*

+2 -5

arch/alpha/kernel/sys_wildfire.c

··· 156 156 wildfire_init_irq_per_pca(int qbbno, int pcano) 157 157 { 158 158 int i, irq_bias; 159 - static struct irqaction isa_enable = { 160 - .handler = no_action, 161 - .name = "isa_enable", 162 - }; 163 159 164 160 irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA) 165 161 + pcano * WILDFIRE_IRQ_PER_PCA; ··· 194 198 irq_set_status_flags(i + irq_bias, IRQ_LEVEL); 195 199 } 196 200 197 - setup_irq(32+irq_bias, &isa_enable); 201 + if (request_irq(32 + irq_bias, no_action, 0, "isa_enable", NULL)) 202 + pr_err("Failed to register isa_enable interrupt\n"); 198 203 } 199 204 200 205 static void __init

+2 -4

arch/alpha/kernel/time.c

··· 242 242 outb(0x31, 0x42); 243 243 outb(0x13, 0x42); 244 244 245 - init_rtc_irq(); 245 + init_rtc_irq(NULL); 246 246 } 247 247 248 248 ··· 396 396 if (alpha_using_qemu) { 397 397 clocksource_register_hz(&qemu_cs, NSEC_PER_SEC); 398 398 init_qemu_clockevent(); 399 - 400 - timer_irqaction.handler = qemu_timer_interrupt; 401 - init_rtc_irq(); 399 + init_rtc_irq(qemu_timer_interrupt); 402 400 return; 403 401 } 404 402

+5 -2

arch/arm/common/sa1111.c

··· 302 302 break; 303 303 } 304 304 305 - if (i == 8) 305 + if (i == 8) { 306 306 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", 307 307 d->irq); 308 - return i == 8 ? -1 : 0; 308 + return 0; 309 + } 310 + 311 + return 1; 309 312 } 310 313 311 314 static int sa1111_type_irq(struct irq_data *d, unsigned int flags)

+3 -8

arch/c6x/platforms/timer64.c

··· 165 165 return IRQ_HANDLED; 166 166 } 167 167 168 - static struct irqaction timer_iact = { 169 - .name = "timer", 170 - .flags = IRQF_TIMER, 171 - .handler = timer_interrupt, 172 - .dev_id = &t64_clockevent_device, 173 - }; 174 - 175 168 void __init timer64_init(void) 176 169 { 177 170 struct clock_event_device *cd = &t64_clockevent_device; ··· 231 238 cd->cpumask = cpumask_of(smp_processor_id()); 232 239 233 240 clockevents_register_device(cd); 234 - setup_irq(cd->irq, &timer_iact); 241 + if (request_irq(cd->irq, timer_interrupt, IRQF_TIMER, "timer", 242 + &t64_clockevent_device)) 243 + pr_err("Failed to request irq %d (timer)\n", cd->irq); 235 244 236 245 out: 237 246 of_node_put(np);

+11 -11

arch/hexagon/kernel/smp.c

··· 114 114 local_irq_restore(flags); 115 115 } 116 116 117 - static struct irqaction ipi_intdesc = { 118 - .handler = handle_ipi, 119 - .flags = IRQF_TRIGGER_RISING, 120 - .name = "ipi_handler" 121 - }; 122 - 123 117 void __init smp_prepare_boot_cpu(void) 124 118 { 125 119 } ··· 126 132 127 133 void start_secondary(void) 128 134 { 129 - unsigned int cpu; 130 135 unsigned long thread_ptr; 136 + unsigned int cpu, irq; 131 137 132 138 /* Calculate thread_info pointer from stack pointer */ 133 139 __asm__ __volatile__( ··· 149 155 150 156 cpu = smp_processor_id(); 151 157 152 - setup_irq(BASE_IPI_IRQ + cpu, &ipi_intdesc); 158 + irq = BASE_IPI_IRQ + cpu; 159 + if (request_irq(irq, handle_ipi, IRQF_TRIGGER_RISING, "ipi_handler", 160 + NULL)) 161 + pr_err("Failed to request irq %u (ipi_handler)\n", irq); 153 162 154 163 /* Register the clock_event dummy */ 155 164 setup_percpu_clockdev(); ··· 198 201 199 202 void __init smp_prepare_cpus(unsigned int max_cpus) 200 203 { 201 - int i; 204 + int i, irq = BASE_IPI_IRQ; 202 205 203 206 /* 204 207 * should eventually have some sort of machine ··· 210 213 set_cpu_present(i, true); 211 214 212 215 /* Also need to register the interrupts for IPI */ 213 - if (max_cpus > 1) 214 - setup_irq(BASE_IPI_IRQ, &ipi_intdesc); 216 + if (max_cpus > 1) { 217 + if (request_irq(irq, handle_ipi, IRQF_TRIGGER_RISING, 218 + "ipi_handler", NULL)) 219 + pr_err("Failed to request irq %d (ipi_handler)\n", irq); 220 + } 215 221 } 216 222 217 223 void smp_send_reschedule(int cpu)

+3 -8

arch/hexagon/kernel/time.c

··· 143 143 return IRQ_HANDLED; 144 144 } 145 145 146 - /* This should also be pulled from devtree */ 147 - static struct irqaction rtos_timer_intdesc = { 148 - .handler = timer_interrupt, 149 - .flags = IRQF_TIMER | IRQF_TRIGGER_RISING, 150 - .name = "rtos_timer" 151 - }; 152 - 153 146 /* 154 147 * time_init_deferred - called by start_kernel to set up timer/clock source 155 148 * ··· 156 163 { 157 164 struct resource *resource = NULL; 158 165 struct clock_event_device *ce_dev = &hexagon_clockevent_dev; 166 + unsigned long flag = IRQF_TIMER | IRQF_TRIGGER_RISING; 159 167 160 168 ce_dev->cpumask = cpu_all_mask; 161 169 ··· 189 195 #endif 190 196 191 197 clockevents_register_device(ce_dev); 192 - setup_irq(ce_dev->irq, &rtos_timer_intdesc); 198 + if (request_irq(ce_dev->irq, timer_interrupt, flag, "rtos_timer", NULL)) 199 + pr_err("Failed to register rtos_timer interrupt\n"); 193 200 } 194 201 195 202 void __init time_init(void)

+2

arch/microblaze/Kconfig

··· 47 47 select CPU_NO_EFFICIENT_FFS 48 48 select MMU_GATHER_NO_RANGE if MMU 49 49 select SPARSE_IRQ 50 + select GENERIC_IRQ_MULTI_HANDLER 51 + select HANDLE_DOMAIN_IRQ 50 52 51 53 # Endianness selection 52 54 choice

-3

arch/microblaze/include/asm/irq.h

··· 14 14 struct pt_regs; 15 15 extern void do_IRQ(struct pt_regs *regs); 16 16 17 - /* should be defined in each interrupt controller driver */ 18 - extern unsigned int xintc_get_irq(void); 19 - 20 17 #endif /* _ASM_MICROBLAZE_IRQ_H */

+1 -20

arch/microblaze/kernel/irq.c

··· 20 20 #include <linux/irqchip.h> 21 21 #include <linux/of_irq.h> 22 22 23 - static u32 concurrent_irq; 24 - 25 23 void __irq_entry do_IRQ(struct pt_regs *regs) 26 24 { 27 - unsigned int irq; 28 - struct pt_regs *old_regs = set_irq_regs(regs); 29 25 trace_hardirqs_off(); 30 - 31 - irq_enter(); 32 - irq = xintc_get_irq(); 33 - next_irq: 34 - BUG_ON(!irq); 35 - generic_handle_irq(irq); 36 - 37 - irq = xintc_get_irq(); 38 - if (irq != -1U) { 39 - pr_debug("next irq: %d\n", irq); 40 - ++concurrent_irq; 41 - goto next_irq; 42 - } 43 - 44 - irq_exit(); 45 - set_irq_regs(old_regs); 26 + handle_arch_irq(regs); 46 27 trace_hardirqs_on(); 47 28 } 48 29

+1 -1

arch/riscv/kernel/traps.c

··· 157 157 /* Set the exception vector address */ 158 158 csr_write(CSR_TVEC, &handle_exception); 159 159 /* Enable interrupts */ 160 - csr_write(CSR_IE, IE_SIE | IE_EIE); 160 + csr_write(CSR_IE, IE_SIE); 161 161 }

+6 -12

arch/sh/boards/mach-cayman/irq.c

··· 40 40 return IRQ_NONE; 41 41 } 42 42 43 - static struct irqaction cayman_action_smsc = { 44 - .name = "Cayman SMSC Mux", 45 - .handler = cayman_interrupt_smsc, 46 - }; 47 - 48 - static struct irqaction cayman_action_pci2 = { 49 - .name = "Cayman PCI2 Mux", 50 - .handler = cayman_interrupt_pci2, 51 - }; 52 - 53 43 static void enable_cayman_irq(struct irq_data *data) 54 44 { 55 45 unsigned int irq = data->irq; ··· 139 149 } 140 150 141 151 /* Setup the SMSC interrupt */ 142 - setup_irq(SMSC_IRQ, &cayman_action_smsc); 143 - setup_irq(PCI2_IRQ, &cayman_action_pci2); 152 + if (request_irq(SMSC_IRQ, cayman_interrupt_smsc, 0, "Cayman SMSC Mux", 153 + NULL)) 154 + pr_err("Failed to register Cayman SMSC Mux interrupt\n"); 155 + if (request_irq(PCI2_IRQ, cayman_interrupt_pci2, 0, "Cayman PCI2 Mux", 156 + NULL)) 157 + pr_err("Failed to register Cayman PCI2 Mux interrupt\n"); 144 158 }

+3 -6

arch/sh/drivers/dma/dma-pvr2.c

··· 64 64 return 0; 65 65 } 66 66 67 - static struct irqaction pvr2_dma_irq = { 68 - .name = "pvr2 DMA handler", 69 - .handler = pvr2_dma_interrupt, 70 - }; 71 - 72 67 static struct dma_ops pvr2_dma_ops = { 73 68 .request = pvr2_request_dma, 74 69 .get_residue = pvr2_get_dma_residue, ··· 79 84 80 85 static int __init pvr2_dma_init(void) 81 86 { 82 - setup_irq(HW_EVENT_PVR2_DMA, &pvr2_dma_irq); 87 + if (request_irq(HW_EVENT_PVR2_DMA, pvr2_dma_interrupt, 0, 88 + "pvr2 DMA handler", NULL)) 89 + pr_err("Failed to register pvr2 DMA handler interrupt\n"); 83 90 request_dma(PVR2_CASCADE_CHAN, "pvr2 cascade"); 84 91 85 92 return register_dmac(&pvr2_dma_info);

+3 -8

arch/unicore32/kernel/time.c

··· 72 72 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 73 73 }; 74 74 75 - static struct irqaction puv3_timer_irq = { 76 - .name = "ost0", 77 - .flags = IRQF_TIMER | IRQF_IRQPOLL, 78 - .handler = puv3_ost0_interrupt, 79 - .dev_id = &ckevt_puv3_osmr0, 80 - }; 81 - 82 75 void __init time_init(void) 83 76 { 84 77 writel(0, OST_OIER); /* disable any timer interrupts */ ··· 87 94 ckevt_puv3_osmr0.min_delta_ticks = MIN_OSCR_DELTA * 2; 88 95 ckevt_puv3_osmr0.cpumask = cpumask_of(0); 89 96 90 - setup_irq(IRQ_TIMER0, &puv3_timer_irq); 97 + if (request_irq(IRQ_TIMER0, puv3_ost0_interrupt, 98 + IRQF_TIMER | IRQF_IRQPOLL, "ost0", &ckevt_puv3_osmr0)) 99 + pr_err("Failed to register ost0 interrupt\n"); 91 100 92 101 clocksource_register_hz(&cksrc_puv3_oscr, CLOCK_TICK_RATE); 93 102 clockevents_register_device(&ckevt_puv3_osmr0);

+1

arch/x86/Kconfig

··· 128 128 select GENERIC_GETTIMEOFDAY 129 129 select GENERIC_VDSO_TIME_NS 130 130 select GUP_GET_PTE_LOW_HIGH if X86_PAE 131 + select HARDIRQS_SW_RESEND 131 132 select HARDLOCKUP_CHECK_TIMESTAMP if X86_64 132 133 select HAVE_ACPI_APEI if ACPI 133 134 select HAVE_ACPI_APEI_NMI if ACPI

+6

arch/x86/kernel/apic/vector.c

··· 557 557 irqd->hwirq = virq + i; 558 558 irqd_set_single_target(irqd); 559 559 /* 560 + * Prevent that any of these interrupts is invoked in 561 + * non interrupt context via e.g. generic_handle_irq() 562 + * as that can corrupt the affinity move state. 563 + */ 564 + irqd_set_handle_enforce_irqctx(irqd); 565 + /* 560 566 * Legacy vectors are already assigned when the IOAPIC 561 567 * takes them over. They stay on the same vector. This is 562 568 * required for check_timer() to work correctly as it might

+1 -1

drivers/irqchip/Kconfig

··· 458 458 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 459 459 460 460 config IMX_INTMUX 461 - def_bool y if ARCH_MXC 461 + def_bool y if ARCH_MXC || COMPILE_TEST 462 462 select IRQ_DOMAIN 463 463 help 464 464 Support for the i.MX INTMUX interrupt multiplexer.

+1 -1

drivers/irqchip/irq-atmel-aic.c

··· 83 83 irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); 84 84 irq_gc_unlock(gc); 85 85 86 - return 0; 86 + return 1; 87 87 } 88 88 89 89 static int aic_set_type(struct irq_data *d, unsigned type)

+1 -1

drivers/irqchip/irq-atmel-aic5.c

··· 128 128 irq_reg_writel(bgc, 1, AT91_AIC5_ISCR); 129 129 irq_gc_unlock(bgc); 130 130 131 - return 0; 131 + return 1; 132 132 } 133 133 134 134 static int aic5_set_type(struct irq_data *d, unsigned type)

+15

drivers/irqchip/irq-bcm2835.c

··· 61 61 | SHORTCUT1_MASK | SHORTCUT2_MASK) 62 62 63 63 #define REG_FIQ_CONTROL 0x0c 64 + #define FIQ_CONTROL_ENABLE BIT(7) 64 65 65 66 #define NR_BANKS 3 66 67 #define IRQS_PER_BANK 32 ··· 136 135 { 137 136 void __iomem *base; 138 137 int irq, b, i; 138 + u32 reg; 139 139 140 140 base = of_iomap(node, 0); 141 141 if (!base) ··· 159 157 handle_level_irq); 160 158 irq_set_probe(irq); 161 159 } 160 + 161 + reg = readl_relaxed(intc.enable[b]); 162 + if (reg) { 163 + writel_relaxed(reg, intc.disable[b]); 164 + pr_err(FW_BUG "Bootloader left irq enabled: " 165 + "bank %d irq %*pbl\n", b, IRQS_PER_BANK, &reg); 166 + } 167 + } 168 + 169 + reg = readl_relaxed(base + REG_FIQ_CONTROL); 170 + if (reg & FIQ_CONTROL_ENABLE) { 171 + writel_relaxed(0, base + REG_FIQ_CONTROL); 172 + pr_err(FW_BUG "Bootloader left fiq enabled\n"); 162 173 } 163 174 164 175 if (is_2836) {

+1 -1

drivers/irqchip/irq-bcm7038-l1.c

··· 50 50 51 51 struct bcm7038_l1_cpu { 52 52 void __iomem *map_base; 53 - u32 mask_cache[0]; 53 + u32 mask_cache[]; 54 54 }; 55 55 56 56 /*

+474 -58

drivers/irqchip/irq-gic-v3-its.c

··· 96 96 struct mutex dev_alloc_lock; 97 97 struct list_head entry; 98 98 void __iomem *base; 99 + void __iomem *sgir_base; 99 100 phys_addr_t phys_base; 100 101 struct its_cmd_block *cmd_base; 101 102 struct its_cmd_block *cmd_write; ··· 189 188 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 190 189 #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) 191 190 191 + /* 192 + * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we 193 + * always have vSGIs mapped. 194 + */ 195 + static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) 196 + { 197 + return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); 198 + } 199 + 192 200 static u16 get_its_list(struct its_vm *vm) 193 201 { 194 202 struct its_node *its; ··· 207 197 if (!is_v4(its)) 208 198 continue; 209 199 210 - if (vm->vlpi_count[its->list_nr]) 200 + if (require_its_list_vmovp(vm, its)) 211 201 __set_bit(its->list_nr, &its_list); 212 202 } 213 203 ··· 249 239 return NULL; 250 240 } 251 241 252 - static int irq_to_cpuid(struct irq_data *d) 242 + static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags) 253 243 { 254 - struct its_device *its_dev = irq_data_get_irq_chip_data(d); 244 + raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); 245 + return vpe->col_idx; 246 + } 247 + 248 + static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags) 249 + { 250 + raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); 251 + } 252 + 253 + static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags) 254 + { 255 + struct its_vlpi_map *map = get_vlpi_map(d); 256 + int cpu; 257 + 258 + if (map) { 259 + cpu = vpe_to_cpuid_lock(map->vpe, flags); 260 + } else { 261 + /* Physical LPIs are already locked via the irq_desc lock */ 262 + struct its_device *its_dev = irq_data_get_irq_chip_data(d); 263 + cpu = its_dev->event_map.col_map[its_get_event_id(d)]; 264 + /* Keep GCC quiet... */ 265 + *flags = 0; 266 + } 267 + 268 + return cpu; 269 + } 270 + 271 + static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags) 272 + { 255 273 struct its_vlpi_map *map = get_vlpi_map(d); 256 274 257 275 if (map) 258 - return map->vpe->col_idx; 259 - 260 - return its_dev->event_map.col_map[its_get_event_id(d)]; 276 + vpe_to_cpuid_unlock(map->vpe, flags); 261 277 } 262 278 263 279 static struct its_collection *valid_col(struct its_collection *col) ··· 389 353 struct { 390 354 struct its_vpe *vpe; 391 355 } its_invdb_cmd; 356 + 357 + struct { 358 + struct its_vpe *vpe; 359 + u8 sgi; 360 + u8 priority; 361 + bool enable; 362 + bool group; 363 + bool clear; 364 + } its_vsgi_cmd; 392 365 }; 393 366 }; 394 367 ··· 544 499 static void its_encode_db(struct its_cmd_block *cmd, bool db) 545 500 { 546 501 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); 502 + } 503 + 504 + static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi) 505 + { 506 + its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); 507 + } 508 + 509 + static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio) 510 + { 511 + its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); 512 + } 513 + 514 + static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp) 515 + { 516 + its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); 517 + } 518 + 519 + static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr) 520 + { 521 + its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); 522 + } 523 + 524 + static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en) 525 + { 526 + its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); 547 527 } 548 528 549 529 static inline void its_fixup_cmd(struct its_cmd_block *cmd) ··· 936 866 return valid_vpe(its, desc->its_invdb_cmd.vpe); 937 867 } 938 868 869 + static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, 870 + struct its_cmd_block *cmd, 871 + struct its_cmd_desc *desc) 872 + { 873 + if (WARN_ON(!is_v4_1(its))) 874 + return NULL; 875 + 876 + its_encode_cmd(cmd, GITS_CMD_VSGI); 877 + its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); 878 + its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); 879 + its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); 880 + its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); 881 + its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); 882 + its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); 883 + 884 + its_fixup_cmd(cmd); 885 + 886 + return valid_vpe(its, desc->its_vsgi_cmd.vpe); 887 + } 888 + 939 889 static u64 its_cmd_ptr_to_offset(struct its_node *its, 940 890 struct its_cmd_block *ptr) 941 891 { ··· 1304 1214 if (!is_v4(its)) 1305 1215 continue; 1306 1216 1307 - if (!vpe->its_vm->vlpi_count[its->list_nr]) 1217 + if (!require_its_list_vmovp(vpe->its_vm, its)) 1308 1218 continue; 1309 1219 1310 1220 desc.its_vmovp_cmd.col = &its->collections[col_id]; ··· 1411 1321 1412 1322 static void wait_for_syncr(void __iomem *rdbase) 1413 1323 { 1414 - while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) 1324 + while (readl_relaxed(rdbase + GICR_SYNCR) & 1) 1415 1325 cpu_relax(); 1416 1326 } 1417 1327 ··· 1419 1329 { 1420 1330 struct its_vlpi_map *map = get_vlpi_map(d); 1421 1331 void __iomem *rdbase; 1332 + unsigned long flags; 1422 1333 u64 val; 1334 + int cpu; 1423 1335 1424 1336 if (map) { 1425 1337 struct its_device *its_dev = irq_data_get_irq_chip_data(d); ··· 1436 1344 } 1437 1345 1438 1346 /* Target the redistributor this LPI is currently routed to */ 1439 - rdbase = per_cpu_ptr(gic_rdists->rdist, irq_to_cpuid(d))->rd_base; 1347 + cpu = irq_to_cpuid_lock(d, &flags); 1348 + raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); 1349 + rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; 1440 1350 gic_write_lpir(val, rdbase + GICR_INVLPIR); 1441 1351 1442 1352 wait_for_syncr(rdbase); 1353 + raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); 1354 + irq_to_cpuid_unlock(d, flags); 1443 1355 } 1444 1356 1445 1357 static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) ··· 1595 1499 return 0; 1596 1500 } 1597 1501 1502 + /* 1503 + * Two favourable cases: 1504 + * 1505 + * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times 1506 + * for vSGI delivery 1507 + * 1508 + * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough 1509 + * and we're better off mapping all VPEs always 1510 + * 1511 + * If neither (a) nor (b) is true, then we map vPEs on demand. 1512 + * 1513 + */ 1514 + static bool gic_requires_eager_mapping(void) 1515 + { 1516 + if (!its_list_map || gic_rdists->has_rvpeid) 1517 + return true; 1518 + 1519 + return false; 1520 + } 1521 + 1598 1522 static void its_map_vm(struct its_node *its, struct its_vm *vm) 1599 1523 { 1600 1524 unsigned long flags; 1601 1525 1602 - /* Not using the ITS list? Everything is always mapped. */ 1603 - if (!its_list_map) 1526 + if (gic_requires_eager_mapping()) 1604 1527 return; 1605 1528 1606 1529 raw_spin_lock_irqsave(&vmovp_lock, flags); ··· 1653 1538 unsigned long flags; 1654 1539 1655 1540 /* Not using the ITS list? Everything is always mapped. */ 1656 - if (!its_list_map) 1541 + if (gic_requires_eager_mapping()) 1657 1542 return; 1658 1543 1659 1544 raw_spin_lock_irqsave(&vmovp_lock, flags); ··· 2151 2036 } 2152 2037 2153 2038 static int its_setup_baser(struct its_node *its, struct its_baser *baser, 2154 - u64 cache, u64 shr, u32 psz, u32 order, 2155 - bool indirect) 2039 + u64 cache, u64 shr, u32 order, bool indirect) 2156 2040 { 2157 2041 u64 val = its_read_baser(its, baser); 2158 2042 u64 esz = GITS_BASER_ENTRY_SIZE(val); 2159 2043 u64 type = GITS_BASER_TYPE(val); 2160 2044 u64 baser_phys, tmp; 2161 - u32 alloc_pages; 2045 + u32 alloc_pages, psz; 2162 2046 struct page *page; 2163 2047 void *base; 2164 2048 2165 - retry_alloc_baser: 2049 + psz = baser->psz; 2166 2050 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); 2167 2051 if (alloc_pages > GITS_BASER_PAGES_MAX) { 2168 2052 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", ··· 2234 2120 goto retry_baser; 2235 2121 } 2236 2122 2237 - if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { 2238 - /* 2239 - * Page size didn't stick. Let's try a smaller 2240 - * size and retry. If we reach 4K, then 2241 - * something is horribly wrong... 2242 - */ 2243 - free_pages((unsigned long)base, order); 2244 - baser->base = NULL; 2245 - 2246 - switch (psz) { 2247 - case SZ_16K: 2248 - psz = SZ_4K; 2249 - goto retry_alloc_baser; 2250 - case SZ_64K: 2251 - psz = SZ_16K; 2252 - goto retry_alloc_baser; 2253 - } 2254 - } 2255 - 2256 2123 if (val != tmp) { 2257 2124 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", 2258 2125 &its->phys_base, its_base_type_string[type], ··· 2259 2164 2260 2165 static bool its_parse_indirect_baser(struct its_node *its, 2261 2166 struct its_baser *baser, 2262 - u32 psz, u32 *order, u32 ids) 2167 + u32 *order, u32 ids) 2263 2168 { 2264 2169 u64 tmp = its_read_baser(its, baser); 2265 2170 u64 type = GITS_BASER_TYPE(tmp); 2266 2171 u64 esz = GITS_BASER_ENTRY_SIZE(tmp); 2267 2172 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; 2268 2173 u32 new_order = *order; 2174 + u32 psz = baser->psz; 2269 2175 bool indirect = false; 2270 2176 2271 2177 /* No need to enable Indirection if memory requirement < (psz*2)bytes */ ··· 2384 2288 } 2385 2289 } 2386 2290 2291 + static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) 2292 + { 2293 + u64 psz = SZ_64K; 2294 + 2295 + while (psz) { 2296 + u64 val, gpsz; 2297 + 2298 + val = its_read_baser(its, baser); 2299 + val &= ~GITS_BASER_PAGE_SIZE_MASK; 2300 + 2301 + switch (psz) { 2302 + case SZ_64K: 2303 + gpsz = GITS_BASER_PAGE_SIZE_64K; 2304 + break; 2305 + case SZ_16K: 2306 + gpsz = GITS_BASER_PAGE_SIZE_16K; 2307 + break; 2308 + case SZ_4K: 2309 + default: 2310 + gpsz = GITS_BASER_PAGE_SIZE_4K; 2311 + break; 2312 + } 2313 + 2314 + gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT; 2315 + 2316 + val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz); 2317 + its_write_baser(its, baser, val); 2318 + 2319 + if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) 2320 + break; 2321 + 2322 + switch (psz) { 2323 + case SZ_64K: 2324 + psz = SZ_16K; 2325 + break; 2326 + case SZ_16K: 2327 + psz = SZ_4K; 2328 + break; 2329 + case SZ_4K: 2330 + default: 2331 + return -1; 2332 + } 2333 + } 2334 + 2335 + baser->psz = psz; 2336 + return 0; 2337 + } 2338 + 2387 2339 static int its_alloc_tables(struct its_node *its) 2388 2340 { 2389 2341 u64 shr = GITS_BASER_InnerShareable; 2390 2342 u64 cache = GITS_BASER_RaWaWb; 2391 - u32 psz = SZ_64K; 2392 2343 int err, i; 2393 2344 2394 2345 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) ··· 2446 2303 struct its_baser *baser = its->tables + i; 2447 2304 u64 val = its_read_baser(its, baser); 2448 2305 u64 type = GITS_BASER_TYPE(val); 2449 - u32 order = get_order(psz); 2450 2306 bool indirect = false; 2307 + u32 order; 2451 2308 2452 - switch (type) { 2453 - case GITS_BASER_TYPE_NONE: 2309 + if (type == GITS_BASER_TYPE_NONE) 2454 2310 continue; 2455 2311 2312 + if (its_probe_baser_psz(its, baser)) { 2313 + its_free_tables(its); 2314 + return -ENXIO; 2315 + } 2316 + 2317 + order = get_order(baser->psz); 2318 + 2319 + switch (type) { 2456 2320 case GITS_BASER_TYPE_DEVICE: 2457 - indirect = its_parse_indirect_baser(its, baser, 2458 - psz, &order, 2321 + indirect = its_parse_indirect_baser(its, baser, &order, 2459 2322 device_ids(its)); 2460 2323 break; 2461 2324 ··· 2477 2328 } 2478 2329 } 2479 2330 2480 - indirect = its_parse_indirect_baser(its, baser, 2481 - psz, &order, 2331 + indirect = its_parse_indirect_baser(its, baser, &order, 2482 2332 ITS_MAX_VPEID_BITS); 2483 2333 break; 2484 2334 } 2485 2335 2486 - err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); 2336 + err = its_setup_baser(its, baser, cache, shr, order, indirect); 2487 2337 if (err < 0) { 2488 2338 its_free_tables(its); 2489 2339 return err; 2490 2340 } 2491 2341 2492 2342 /* Update settings which will be used for next BASERn */ 2493 - psz = baser->psz; 2494 2343 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; 2495 2344 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; 2496 2345 } ··· 2597 2450 __le64 *table; 2598 2451 2599 2452 if (!gic_rdists->has_rvpeid) 2453 + return true; 2454 + 2455 + /* Skip non-present CPUs */ 2456 + if (!base) 2600 2457 return true; 2601 2458 2602 2459 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); ··· 3633 3482 { 3634 3483 struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3635 3484 int from, cpu = cpumask_first(mask_val); 3485 + unsigned long flags; 3636 3486 3637 3487 /* 3638 3488 * Changing affinity is mega expensive, so let's be as lazy as 3639 3489 * we can and only do it if we really have to. Also, if mapped 3640 3490 * into the proxy device, we need to move the doorbell 3641 3491 * interrupt to its new location. 3492 + * 3493 + * Another thing is that changing the affinity of a vPE affects 3494 + * *other interrupts* such as all the vLPIs that are routed to 3495 + * this vPE. This means that the irq_desc lock is not enough to 3496 + * protect us, and that we must ensure nobody samples vpe->col_idx 3497 + * during the update, hence the lock below which must also be 3498 + * taken on any vLPI handling path that evaluates vpe->col_idx. 3642 3499 */ 3643 - if (vpe->col_idx == cpu) 3500 + from = vpe_to_cpuid_lock(vpe, &flags); 3501 + if (from == cpu) 3644 3502 goto out; 3645 3503 3646 - from = vpe->col_idx; 3647 3504 vpe->col_idx = cpu; 3648 3505 3649 3506 /* ··· 3667 3508 3668 3509 out: 3669 3510 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 3511 + vpe_to_cpuid_unlock(vpe, flags); 3670 3512 3671 3513 return IRQ_SET_MASK_OK_DONE; 3672 3514 } ··· 3688 3528 val = virt_to_phys(page_address(vpe->vpt_page)) & 3689 3529 GENMASK_ULL(51, 16); 3690 3530 val |= GICR_VPENDBASER_RaWaWb; 3691 - val |= GICR_VPENDBASER_NonShareable; 3531 + val |= GICR_VPENDBASER_InnerShareable; 3692 3532 /* 3693 3533 * There is no good way of finding out if the pending table is 3694 3534 * empty as we can race against the doorbell interrupt very ··· 3779 3619 void __iomem *rdbase; 3780 3620 3781 3621 /* Target the redistributor this VPE is currently known on */ 3622 + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); 3782 3623 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; 3783 3624 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); 3784 3625 wait_for_syncr(rdbase); 3626 + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); 3785 3627 } else { 3786 3628 its_vpe_send_cmd(vpe, its_send_inv); 3787 3629 } ··· 3837 3675 return 0; 3838 3676 } 3839 3677 3678 + static int its_vpe_retrigger(struct irq_data *d) 3679 + { 3680 + return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true); 3681 + } 3682 + 3840 3683 static struct irq_chip its_vpe_irq_chip = { 3841 3684 .name = "GICv4-vpe", 3842 3685 .irq_mask = its_vpe_mask_irq, 3843 3686 .irq_unmask = its_vpe_unmask_irq, 3844 3687 .irq_eoi = irq_chip_eoi_parent, 3845 3688 .irq_set_affinity = its_vpe_set_affinity, 3689 + .irq_retrigger = its_vpe_retrigger, 3846 3690 .irq_set_irqchip_state = its_vpe_set_irqchip_state, 3847 3691 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, 3848 3692 }; ··· 3950 3782 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); 3951 3783 3952 3784 /* Target the redistributor this vPE is currently known on */ 3785 + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); 3953 3786 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; 3954 3787 gic_write_lpir(val, rdbase + GICR_INVALLR); 3788 + 3789 + wait_for_syncr(rdbase); 3790 + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); 3955 3791 } 3956 3792 3957 3793 static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) ··· 3988 3816 .irq_eoi = irq_chip_eoi_parent, 3989 3817 .irq_set_affinity = its_vpe_set_affinity, 3990 3818 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity, 3819 + }; 3820 + 3821 + static void its_configure_sgi(struct irq_data *d, bool clear) 3822 + { 3823 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3824 + struct its_cmd_desc desc; 3825 + 3826 + desc.its_vsgi_cmd.vpe = vpe; 3827 + desc.its_vsgi_cmd.sgi = d->hwirq; 3828 + desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; 3829 + desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; 3830 + desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; 3831 + desc.its_vsgi_cmd.clear = clear; 3832 + 3833 + /* 3834 + * GICv4.1 allows us to send VSGI commands to any ITS as long as the 3835 + * destination VPE is mapped there. Since we map them eagerly at 3836 + * activation time, we're pretty sure the first GICv4.1 ITS will do. 3837 + */ 3838 + its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc); 3839 + } 3840 + 3841 + static void its_sgi_mask_irq(struct irq_data *d) 3842 + { 3843 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3844 + 3845 + vpe->sgi_config[d->hwirq].enabled = false; 3846 + its_configure_sgi(d, false); 3847 + } 3848 + 3849 + static void its_sgi_unmask_irq(struct irq_data *d) 3850 + { 3851 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3852 + 3853 + vpe->sgi_config[d->hwirq].enabled = true; 3854 + its_configure_sgi(d, false); 3855 + } 3856 + 3857 + static int its_sgi_set_affinity(struct irq_data *d, 3858 + const struct cpumask *mask_val, 3859 + bool force) 3860 + { 3861 + /* 3862 + * There is no notion of affinity for virtual SGIs, at least 3863 + * not on the host (since they can only be targetting a vPE). 3864 + * Tell the kernel we've done whatever it asked for. 3865 + */ 3866 + return IRQ_SET_MASK_OK; 3867 + } 3868 + 3869 + static int its_sgi_set_irqchip_state(struct irq_data *d, 3870 + enum irqchip_irq_state which, 3871 + bool state) 3872 + { 3873 + if (which != IRQCHIP_STATE_PENDING) 3874 + return -EINVAL; 3875 + 3876 + if (state) { 3877 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3878 + struct its_node *its = find_4_1_its(); 3879 + u64 val; 3880 + 3881 + val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); 3882 + val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); 3883 + writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); 3884 + } else { 3885 + its_configure_sgi(d, true); 3886 + } 3887 + 3888 + return 0; 3889 + } 3890 + 3891 + static int its_sgi_get_irqchip_state(struct irq_data *d, 3892 + enum irqchip_irq_state which, bool *val) 3893 + { 3894 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3895 + void __iomem *base; 3896 + unsigned long flags; 3897 + u32 count = 1000000; /* 1s! */ 3898 + u32 status; 3899 + int cpu; 3900 + 3901 + if (which != IRQCHIP_STATE_PENDING) 3902 + return -EINVAL; 3903 + 3904 + /* 3905 + * Locking galore! We can race against two different events: 3906 + * 3907 + * - Concurent vPE affinity change: we must make sure it cannot 3908 + * happen, or we'll talk to the wrong redistributor. This is 3909 + * identical to what happens with vLPIs. 3910 + * 3911 + * - Concurrent VSGIPENDR access: As it involves accessing two 3912 + * MMIO registers, this must be made atomic one way or another. 3913 + */ 3914 + cpu = vpe_to_cpuid_lock(vpe, &flags); 3915 + raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); 3916 + base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; 3917 + writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); 3918 + do { 3919 + status = readl_relaxed(base + GICR_VSGIPENDR); 3920 + if (!(status & GICR_VSGIPENDR_BUSY)) 3921 + goto out; 3922 + 3923 + count--; 3924 + if (!count) { 3925 + pr_err_ratelimited("Unable to get SGI status\n"); 3926 + goto out; 3927 + } 3928 + cpu_relax(); 3929 + udelay(1); 3930 + } while (count); 3931 + 3932 + out: 3933 + raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); 3934 + vpe_to_cpuid_unlock(vpe, flags); 3935 + 3936 + if (!count) 3937 + return -ENXIO; 3938 + 3939 + *val = !!(status & (1 << d->hwirq)); 3940 + 3941 + return 0; 3942 + } 3943 + 3944 + static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) 3945 + { 3946 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 3947 + struct its_cmd_info *info = vcpu_info; 3948 + 3949 + switch (info->cmd_type) { 3950 + case PROP_UPDATE_VSGI: 3951 + vpe->sgi_config[d->hwirq].priority = info->priority; 3952 + vpe->sgi_config[d->hwirq].group = info->group; 3953 + its_configure_sgi(d, false); 3954 + return 0; 3955 + 3956 + default: 3957 + return -EINVAL; 3958 + } 3959 + } 3960 + 3961 + static struct irq_chip its_sgi_irq_chip = { 3962 + .name = "GICv4.1-sgi", 3963 + .irq_mask = its_sgi_mask_irq, 3964 + .irq_unmask = its_sgi_unmask_irq, 3965 + .irq_set_affinity = its_sgi_set_affinity, 3966 + .irq_set_irqchip_state = its_sgi_set_irqchip_state, 3967 + .irq_get_irqchip_state = its_sgi_get_irqchip_state, 3968 + .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity, 3969 + }; 3970 + 3971 + static int its_sgi_irq_domain_alloc(struct irq_domain *domain, 3972 + unsigned int virq, unsigned int nr_irqs, 3973 + void *args) 3974 + { 3975 + struct its_vpe *vpe = args; 3976 + int i; 3977 + 3978 + /* Yes, we do want 16 SGIs */ 3979 + WARN_ON(nr_irqs != 16); 3980 + 3981 + for (i = 0; i < 16; i++) { 3982 + vpe->sgi_config[i].priority = 0; 3983 + vpe->sgi_config[i].enabled = false; 3984 + vpe->sgi_config[i].group = false; 3985 + 3986 + irq_domain_set_hwirq_and_chip(domain, virq + i, i, 3987 + &its_sgi_irq_chip, vpe); 3988 + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); 3989 + } 3990 + 3991 + return 0; 3992 + } 3993 + 3994 + static void its_sgi_irq_domain_free(struct irq_domain *domain, 3995 + unsigned int virq, 3996 + unsigned int nr_irqs) 3997 + { 3998 + /* Nothing to do */ 3999 + } 4000 + 4001 + static int its_sgi_irq_domain_activate(struct irq_domain *domain, 4002 + struct irq_data *d, bool reserve) 4003 + { 4004 + /* Write out the initial SGI configuration */ 4005 + its_configure_sgi(d, false); 4006 + return 0; 4007 + } 4008 + 4009 + static void its_sgi_irq_domain_deactivate(struct irq_domain *domain, 4010 + struct irq_data *d) 4011 + { 4012 + struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 4013 + 4014 + /* 4015 + * The VSGI command is awkward: 4016 + * 4017 + * - To change the configuration, CLEAR must be set to false, 4018 + * leaving the pending bit unchanged. 4019 + * - To clear the pending bit, CLEAR must be set to true, leaving 4020 + * the configuration unchanged. 4021 + * 4022 + * You just can't do both at once, hence the two commands below. 4023 + */ 4024 + vpe->sgi_config[d->hwirq].enabled = false; 4025 + its_configure_sgi(d, false); 4026 + its_configure_sgi(d, true); 4027 + } 4028 + 4029 + static const struct irq_domain_ops its_sgi_domain_ops = { 4030 + .alloc = its_sgi_irq_domain_alloc, 4031 + .free = its_sgi_irq_domain_free, 4032 + .activate = its_sgi_irq_domain_activate, 4033 + .deactivate = its_sgi_irq_domain_deactivate, 3991 4034 }; 3992 4035 3993 4036 static int its_vpe_id_alloc(void) ··· 4238 3851 return -ENOMEM; 4239 3852 } 4240 3853 3854 + raw_spin_lock_init(&vpe->vpe_lock); 4241 3855 vpe->vpe_id = vpe_id; 4242 3856 vpe->vpt_page = vpt_page; 4243 3857 if (gic_rdists->has_rvpeid) ··· 4348 3960 struct its_vpe *vpe = irq_data_get_irq_chip_data(d); 4349 3961 struct its_node *its; 4350 3962 4351 - /* If we use the list map, we issue VMAPP on demand... */ 4352 - if (its_list_map) 3963 + /* 3964 + * If we use the list map, we issue VMAPP on demand... Unless 3965 + * we're on a GICv4.1 and we eagerly map the VPE on all ITSs 3966 + * so that VSGIs can work. 3967 + */ 3968 + if (!gic_requires_eager_mapping()) 4353 3969 return 0; 4354 3970 4355 3971 /* Map the VPE to the first possible CPU */ ··· 4379 3987 struct its_node *its; 4380 3988 4381 3989 /* 4382 - * If we use the list map, we unmap the VPE once no VLPIs are 4383 - * associated with the VM. 3990 + * If we use the list map on GICv4.0, we unmap the VPE once no 3991 + * VLPIs are associated with the VM. 4384 3992 */ 4385 - if (its_list_map) 3993 + if (!gic_requires_eager_mapping()) 4386 3994 return; 4387 3995 4388 3996 list_for_each_entry(its, &its_nodes, entry) { ··· 4796 4404 struct page *page; 4797 4405 int err; 4798 4406 4799 - its_base = ioremap(res->start, resource_size(res)); 4407 + its_base = ioremap(res->start, SZ_64K); 4800 4408 if (!its_base) { 4801 4409 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); 4802 4410 return -ENOMEM; ··· 4847 4455 4848 4456 if (is_v4_1(its)) { 4849 4457 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer); 4458 + 4459 + its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K); 4460 + if (!its->sgir_base) { 4461 + err = -ENOMEM; 4462 + goto out_free_its; 4463 + } 4464 + 4850 4465 its->mpidr = readl_relaxed(its_base + GITS_MPIDR); 4851 4466 4852 4467 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", ··· 4867 4468 get_order(ITS_CMD_QUEUE_SZ)); 4868 4469 if (!page) { 4869 4470 err = -ENOMEM; 4870 - goto out_free_its; 4471 + goto out_unmap_sgir; 4871 4472 } 4872 4473 its->cmd_base = (void *)page_address(page); 4873 4474 its->cmd_write = its->cmd_base; ··· 4934 4535 its_free_tables(its); 4935 4536 out_free_cmd: 4936 4537 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); 4538 + out_unmap_sgir: 4539 + if (its->sgir_base) 4540 + iounmap(its->sgir_base); 4937 4541 out_free_its: 4938 4542 kfree(its); 4939 4543 out_unmap: ··· 5220 4818 struct device_node *of_node; 5221 4819 struct its_node *its; 5222 4820 bool has_v4 = false; 4821 + bool has_v4_1 = false; 5223 4822 int err; 5224 4823 5225 4824 gic_rdists = rdists; ··· 5241 4838 if (err) 5242 4839 return err; 5243 4840 5244 - list_for_each_entry(its, &its_nodes, entry) 4841 + list_for_each_entry(its, &its_nodes, entry) { 5245 4842 has_v4 |= is_v4(its); 4843 + has_v4_1 |= is_v4_1(its); 4844 + } 4845 + 4846 + /* Don't bother with inconsistent systems */ 4847 + if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) 4848 + rdists->has_rvpeid = false; 5246 4849 5247 4850 if (has_v4 & rdists->has_vlpis) { 4851 + const struct irq_domain_ops *sgi_ops; 4852 + 4853 + if (has_v4_1) 4854 + sgi_ops = &its_sgi_domain_ops; 4855 + else 4856 + sgi_ops = NULL; 4857 + 5248 4858 if (its_init_vpe_domain() || 5249 - its_init_v4(parent_domain, &its_vpe_domain_ops)) { 4859 + its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) { 5250 4860 rdists->has_vlpis = false; 5251 4861 pr_err("ITS: Disabling GICv4 support\n"); 5252 4862 }

+13 -3

drivers/irqchip/irq-gic-v3.c

··· 724 724 unsigned int i; 725 725 u64 affinity; 726 726 void __iomem *base = gic_data.dist_base; 727 + u32 val; 727 728 728 729 /* Disable the distributor */ 729 730 writel_relaxed(0, base + GICD_CTLR); ··· 757 756 /* Now do the common stuff, and wait for the distributor to drain */ 758 757 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); 759 758 759 + val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; 760 + if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { 761 + pr_info("Enabling SGIs without active state\n"); 762 + val |= GICD_CTLR_nASSGIreq; 763 + } 764 + 760 765 /* Enable distributor with ARE, Group1 */ 761 - writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 762 - base + GICD_CTLR); 766 + writel_relaxed(val, base + GICD_CTLR); 763 767 764 768 /* 765 769 * Set all global interrupts to the boot CPU only. ARE must be ··· 835 829 typer = gic_read_typer(ptr + GICR_TYPER); 836 830 if ((typer >> 32) == aff) { 837 831 u64 offset = ptr - region->redist_base; 832 + raw_spin_lock_init(&gic_data_rdist()->rd_lock); 838 833 gic_data_rdist_rd_base() = ptr; 839 834 gic_data_rdist()->phys_base = region->phys_base + offset; 840 835 ··· 1616 1609 1617 1610 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 1618 1611 &gic_data); 1619 - irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1620 1612 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 1621 1613 gic_data.rdists.has_rvpeid = true; 1622 1614 gic_data.rdists.has_vlpis = true; ··· 1625 1619 err = -ENOMEM; 1626 1620 goto out_free; 1627 1621 } 1622 + 1623 + irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); 1628 1624 1629 1625 gic_data.has_rss = !!(typer & GICD_TYPER_RSS); 1630 1626 pr_info("Distributor has %sRange Selector support\n", ··· 1793 1785 gic_v3_kvm_info.vcpu = r; 1794 1786 1795 1787 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 1788 + gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 1796 1789 gic_set_kvm_info(&gic_v3_kvm_info); 1797 1790 } 1798 1791 ··· 2109 2100 } 2110 2101 2111 2102 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis; 2103 + gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid; 2112 2104 gic_set_kvm_info(&gic_v3_kvm_info); 2113 2105 } 2114 2106

+127 -7

drivers/irqchip/irq-gic-v4.c

··· 85 85 86 86 static struct irq_domain *gic_domain; 87 87 static const struct irq_domain_ops *vpe_domain_ops; 88 + static const struct irq_domain_ops *sgi_domain_ops; 89 + 90 + static bool has_v4_1(void) 91 + { 92 + return !!sgi_domain_ops; 93 + } 94 + 95 + static int its_alloc_vcpu_sgis(struct its_vpe *vpe, int idx) 96 + { 97 + char *name; 98 + int sgi_base; 99 + 100 + if (!has_v4_1()) 101 + return 0; 102 + 103 + name = kasprintf(GFP_KERNEL, "GICv4-sgi-%d", task_pid_nr(current)); 104 + if (!name) 105 + goto err; 106 + 107 + vpe->fwnode = irq_domain_alloc_named_id_fwnode(name, idx); 108 + if (!vpe->fwnode) 109 + goto err; 110 + 111 + kfree(name); 112 + name = NULL; 113 + 114 + vpe->sgi_domain = irq_domain_create_linear(vpe->fwnode, 16, 115 + sgi_domain_ops, vpe); 116 + if (!vpe->sgi_domain) 117 + goto err; 118 + 119 + sgi_base = __irq_domain_alloc_irqs(vpe->sgi_domain, -1, 16, 120 + NUMA_NO_NODE, vpe, 121 + false, NULL); 122 + if (sgi_base <= 0) 123 + goto err; 124 + 125 + return 0; 126 + 127 + err: 128 + if (vpe->sgi_domain) 129 + irq_domain_remove(vpe->sgi_domain); 130 + if (vpe->fwnode) 131 + irq_domain_free_fwnode(vpe->fwnode); 132 + kfree(name); 133 + return -ENOMEM; 134 + } 88 135 89 136 int its_alloc_vcpu_irqs(struct its_vm *vm) 90 137 { ··· 159 112 if (vpe_base_irq <= 0) 160 113 goto err; 161 114 162 - for (i = 0; i < vm->nr_vpes; i++) 115 + for (i = 0; i < vm->nr_vpes; i++) { 116 + int ret; 163 117 vm->vpes[i]->irq = vpe_base_irq + i; 118 + ret = its_alloc_vcpu_sgis(vm->vpes[i], i); 119 + if (ret) 120 + goto err; 121 + } 164 122 165 123 return 0; 166 124 ··· 178 126 return -ENOMEM; 179 127 } 180 128 129 + static void its_free_sgi_irqs(struct its_vm *vm) 130 + { 131 + int i; 132 + 133 + if (!has_v4_1()) 134 + return; 135 + 136 + for (i = 0; i < vm->nr_vpes; i++) { 137 + unsigned int irq = irq_find_mapping(vm->vpes[i]->sgi_domain, 0); 138 + 139 + if (WARN_ON(!irq)) 140 + continue; 141 + 142 + irq_domain_free_irqs(irq, 16); 143 + irq_domain_remove(vm->vpes[i]->sgi_domain); 144 + irq_domain_free_fwnode(vm->vpes[i]->fwnode); 145 + } 146 + } 147 + 181 148 void its_free_vcpu_irqs(struct its_vm *vm) 182 149 { 150 + its_free_sgi_irqs(vm); 183 151 irq_domain_free_irqs(vm->vpes[0]->irq, vm->nr_vpes); 184 152 irq_domain_remove(vm->domain); 185 153 irq_domain_free_fwnode(vm->fwnode); ··· 210 138 return irq_set_vcpu_affinity(vpe->irq, info); 211 139 } 212 140 213 - int its_schedule_vpe(struct its_vpe *vpe, bool on) 141 + int its_make_vpe_non_resident(struct its_vpe *vpe, bool db) 214 142 { 215 - struct its_cmd_info info; 143 + struct irq_desc *desc = irq_to_desc(vpe->irq); 144 + struct its_cmd_info info = { }; 216 145 int ret; 217 146 218 147 WARN_ON(preemptible()); 219 148 220 - info.cmd_type = on ? SCHEDULE_VPE : DESCHEDULE_VPE; 149 + info.cmd_type = DESCHEDULE_VPE; 150 + if (has_v4_1()) { 151 + /* GICv4.1 can directly deal with doorbells */ 152 + info.req_db = db; 153 + } else { 154 + /* Undo the nested disable_irq() calls... */ 155 + while (db && irqd_irq_disabled(&desc->irq_data)) 156 + enable_irq(vpe->irq); 157 + } 221 158 222 159 ret = its_send_vpe_cmd(vpe, &info); 223 160 if (!ret) 224 - vpe->resident = on; 161 + vpe->resident = false; 162 + 163 + return ret; 164 + } 165 + 166 + int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en) 167 + { 168 + struct its_cmd_info info = { }; 169 + int ret; 170 + 171 + WARN_ON(preemptible()); 172 + 173 + info.cmd_type = SCHEDULE_VPE; 174 + if (has_v4_1()) { 175 + info.g0en = g0en; 176 + info.g1en = g1en; 177 + } else { 178 + /* Disabled the doorbell, as we're about to enter the guest */ 179 + disable_irq_nosync(vpe->irq); 180 + } 181 + 182 + ret = its_send_vpe_cmd(vpe, &info); 183 + if (!ret) 184 + vpe->resident = true; 225 185 226 186 return ret; 227 187 } ··· 320 216 return irq_set_vcpu_affinity(irq, &info); 321 217 } 322 218 323 - int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops) 219 + int its_prop_update_vsgi(int irq, u8 priority, bool group) 220 + { 221 + struct its_cmd_info info = { 222 + .cmd_type = PROP_UPDATE_VSGI, 223 + { 224 + .priority = priority, 225 + .group = group, 226 + }, 227 + }; 228 + 229 + return irq_set_vcpu_affinity(irq, &info); 230 + } 231 + 232 + int its_init_v4(struct irq_domain *domain, 233 + const struct irq_domain_ops *vpe_ops, 234 + const struct irq_domain_ops *sgi_ops) 324 235 { 325 236 if (domain) { 326 237 pr_info("ITS: Enabling GICv4 support\n"); 327 238 gic_domain = domain; 328 - vpe_domain_ops = ops; 239 + vpe_domain_ops = vpe_ops; 240 + sgi_domain_ops = sgi_ops; 329 241 return 0; 330 242 } 331 243

+6 -10

drivers/irqchip/irq-i8259.c

··· 268 268 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 269 269 } 270 270 271 - /* 272 - * IRQ2 is cascade interrupt to second interrupt controller 273 - */ 274 - static struct irqaction irq2 = { 275 - .handler = no_action, 276 - .name = "cascade", 277 - .flags = IRQF_NO_THREAD, 278 - }; 279 - 280 271 static struct resource pic1_io_resource = { 281 272 .name = "pic1", 282 273 .start = PIC_MASTER_CMD, ··· 302 311 */ 303 312 struct irq_domain * __init __init_i8259_irqs(struct device_node *node) 304 313 { 314 + /* 315 + * PIC_CASCADE_IR is cascade interrupt to second interrupt controller 316 + */ 317 + int irq = I8259A_IRQ_BASE + PIC_CASCADE_IR; 305 318 struct irq_domain *domain; 306 319 307 320 insert_resource(&ioport_resource, &pic1_io_resource); ··· 318 323 if (!domain) 319 324 panic("Failed to add i8259 IRQ domain"); 320 325 321 - setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); 326 + if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) 327 + pr_err("Failed to register cascade interrupt\n"); 322 328 register_syscore_ops(&i8259_syscore_ops); 323 329 return domain; 324 330 }

+1

drivers/irqchip/irq-ingenic-tcu.c

··· 180 180 IRQCHIP_DECLARE(jz4740_tcu_irq, "ingenic,jz4740-tcu", ingenic_tcu_irq_init); 181 181 IRQCHIP_DECLARE(jz4725b_tcu_irq, "ingenic,jz4725b-tcu", ingenic_tcu_irq_init); 182 182 IRQCHIP_DECLARE(jz4770_tcu_irq, "ingenic,jz4770-tcu", ingenic_tcu_irq_init); 183 + IRQCHIP_DECLARE(x1000_tcu_irq, "ingenic,x1000-tcu", ingenic_tcu_irq_init);

+3 -6

drivers/irqchip/irq-ingenic.c

··· 58 58 return IRQ_HANDLED; 59 59 } 60 60 61 - static struct irqaction intc_cascade_action = { 62 - .handler = intc_cascade, 63 - .name = "SoC intc cascade interrupt", 64 - }; 65 - 66 61 static int __init ingenic_intc_of_init(struct device_node *node, 67 62 unsigned num_chips) 68 63 { ··· 125 130 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK); 126 131 } 127 132 128 - setup_irq(parent_irq, &intc_cascade_action); 133 + if (request_irq(parent_irq, intc_cascade, 0, 134 + "SoC intc cascade interrupt", NULL)) 135 + pr_err("Failed to register SoC intc cascade interrupt\n"); 129 136 return 0; 130 137 131 138 out_domain_remove:

+1 -1

drivers/irqchip/irq-renesas-intc-irqpin.c

··· 461 461 } 462 462 463 463 i->iomem = devm_ioremap(dev, io[k]->start, 464 - resource_size(io[k])); 464 + resource_size(io[k])); 465 465 if (!i->iomem) { 466 466 dev_err(dev, "failed to remap IOMEM\n"); 467 467 ret = -ENXIO;

+85 -34

drivers/irqchip/irq-sifive-plic.c

··· 4 4 * Copyright (C) 2018 Christoph Hellwig 5 5 */ 6 6 #define pr_fmt(fmt) "plic: " fmt 7 + #include <linux/cpu.h> 7 8 #include <linux/interrupt.h> 8 9 #include <linux/io.h> 9 10 #include <linux/irq.h> ··· 56 55 #define CONTEXT_THRESHOLD 0x00 57 56 #define CONTEXT_CLAIM 0x04 58 57 59 - static void __iomem *plic_regs; 58 + #define PLIC_DISABLE_THRESHOLD 0xf 59 + #define PLIC_ENABLE_THRESHOLD 0 60 + 61 + struct plic_priv { 62 + struct cpumask lmask; 63 + struct irq_domain *irqdomain; 64 + void __iomem *regs; 65 + }; 60 66 61 67 struct plic_handler { 62 68 bool present; ··· 74 66 */ 75 67 raw_spinlock_t enable_lock; 76 68 void __iomem *enable_base; 69 + struct plic_priv *priv; 77 70 }; 78 71 static DEFINE_PER_CPU(struct plic_handler, plic_handlers); 79 72 ··· 93 84 } 94 85 95 86 static inline void plic_irq_toggle(const struct cpumask *mask, 96 - int hwirq, int enable) 87 + struct irq_data *d, int enable) 97 88 { 98 89 int cpu; 90 + struct plic_priv *priv = irq_get_chip_data(d->irq); 99 91 100 - writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); 92 + writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 101 93 for_each_cpu(cpu, mask) { 102 94 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 103 95 104 - if (handler->present) 105 - plic_toggle(handler, hwirq, enable); 96 + if (handler->present && 97 + cpumask_test_cpu(cpu, &handler->priv->lmask)) 98 + plic_toggle(handler, d->hwirq, enable); 106 99 } 107 100 } 108 101 109 102 static void plic_irq_unmask(struct irq_data *d) 110 103 { 111 - unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d), 112 - cpu_online_mask); 104 + struct cpumask amask; 105 + unsigned int cpu; 106 + struct plic_priv *priv = irq_get_chip_data(d->irq); 107 + 108 + cpumask_and(&amask, &priv->lmask, cpu_online_mask); 109 + cpu = cpumask_any_and(irq_data_get_affinity_mask(d), 110 + &amask); 113 111 if (WARN_ON_ONCE(cpu >= nr_cpu_ids)) 114 112 return; 115 - plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); 113 + plic_irq_toggle(cpumask_of(cpu), d, 1); 116 114 } 117 115 118 116 static void plic_irq_mask(struct irq_data *d) 119 117 { 120 - plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); 118 + struct plic_priv *priv = irq_get_chip_data(d->irq); 119 + 120 + plic_irq_toggle(&priv->lmask, d, 0); 121 121 } 122 122 123 123 #ifdef CONFIG_SMP ··· 134 116 const struct cpumask *mask_val, bool force) 135 117 { 136 118 unsigned int cpu; 119 + struct cpumask amask; 120 + struct plic_priv *priv = irq_get_chip_data(d->irq); 121 + 122 + cpumask_and(&amask, &priv->lmask, mask_val); 137 123 138 124 if (force) 139 - cpu = cpumask_first(mask_val); 125 + cpu = cpumask_first(&amask); 140 126 else 141 - cpu = cpumask_any_and(mask_val, cpu_online_mask); 127 + cpu = cpumask_any_and(&amask, cpu_online_mask); 142 128 143 129 if (cpu >= nr_cpu_ids) 144 130 return -EINVAL; 145 131 146 - plic_irq_toggle(cpu_possible_mask, d->hwirq, 0); 147 - plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1); 132 + plic_irq_toggle(&priv->lmask, d, 0); 133 + plic_irq_toggle(cpumask_of(cpu), d, 1); 148 134 149 135 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 150 136 ··· 209 187 .free = irq_domain_free_irqs_top, 210 188 }; 211 189 212 - static struct irq_domain *plic_irqdomain; 213 - 214 190 /* 215 191 * Handling an interrupt is a two-step process: first you claim the interrupt 216 192 * by reading the claim register, then you complete the interrupt by writing ··· 225 205 226 206 csr_clear(CSR_IE, IE_EIE); 227 207 while ((hwirq = readl(claim))) { 228 - int irq = irq_find_mapping(plic_irqdomain, hwirq); 208 + int irq = irq_find_mapping(handler->priv->irqdomain, hwirq); 229 209 230 210 if (unlikely(irq <= 0)) 231 211 pr_warn_ratelimited("can't find mapping for hwirq %lu\n", ··· 250 230 return -1; 251 231 } 252 232 233 + static void plic_set_threshold(struct plic_handler *handler, u32 threshold) 234 + { 235 + /* priority must be > threshold to trigger an interrupt */ 236 + writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 237 + } 238 + 239 + static int plic_dying_cpu(unsigned int cpu) 240 + { 241 + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 242 + 243 + csr_clear(CSR_IE, IE_EIE); 244 + plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 245 + 246 + return 0; 247 + } 248 + 249 + static int plic_starting_cpu(unsigned int cpu) 250 + { 251 + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 252 + 253 + csr_set(CSR_IE, IE_EIE); 254 + plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); 255 + 256 + return 0; 257 + } 258 + 253 259 static int __init plic_init(struct device_node *node, 254 260 struct device_node *parent) 255 261 { 256 262 int error = 0, nr_contexts, nr_handlers = 0, i; 257 263 u32 nr_irqs; 264 + struct plic_priv *priv; 258 265 259 - if (plic_regs) { 260 - pr_warn("PLIC already present.\n"); 261 - return -ENXIO; 266 + priv = kzalloc(sizeof(*priv), GFP_KERNEL); 267 + if (!priv) 268 + return -ENOMEM; 269 + 270 + priv->regs = of_iomap(node, 0); 271 + if (WARN_ON(!priv->regs)) { 272 + error = -EIO; 273 + goto out_free_priv; 262 274 } 263 - 264 - plic_regs = of_iomap(node, 0); 265 - if (WARN_ON(!plic_regs)) 266 - return -EIO; 267 275 268 276 error = -EINVAL; 269 277 of_property_read_u32(node, "riscv,ndev", &nr_irqs); ··· 305 257 goto out_iounmap; 306 258 307 259 error = -ENOMEM; 308 - plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1, 309 - &plic_irqdomain_ops, NULL); 310 - if (WARN_ON(!plic_irqdomain)) 260 + priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, 261 + &plic_irqdomain_ops, priv); 262 + if (WARN_ON(!priv->irqdomain)) 311 263 goto out_iounmap; 312 264 313 265 for (i = 0; i < nr_contexts; i++) { ··· 315 267 struct plic_handler *handler; 316 268 irq_hw_number_t hwirq; 317 269 int cpu, hartid; 318 - u32 threshold = 0; 319 270 320 271 if (of_irq_parse_one(node, i, &parent)) { 321 272 pr_err("failed to parse parent for context %d.\n", i); ··· 348 301 handler = per_cpu_ptr(&plic_handlers, cpu); 349 302 if (handler->present) { 350 303 pr_warn("handler already present for context %d.\n", i); 351 - threshold = 0xffffffff; 304 + plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 352 305 goto done; 353 306 } 354 307 308 + cpumask_set_cpu(cpu, &priv->lmask); 355 309 handler->present = true; 356 310 handler->hart_base = 357 - plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART; 311 + priv->regs + CONTEXT_BASE + i * CONTEXT_PER_HART; 358 312 raw_spin_lock_init(&handler->enable_lock); 359 313 handler->enable_base = 360 - plic_regs + ENABLE_BASE + i * ENABLE_PER_HART; 361 - 314 + priv->regs + ENABLE_BASE + i * ENABLE_PER_HART; 315 + handler->priv = priv; 362 316 done: 363 - /* priority must be > threshold to trigger an interrupt */ 364 - writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 365 317 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) 366 318 plic_toggle(handler, hwirq, 0); 367 319 nr_handlers++; 368 320 } 369 321 322 + cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 323 + "irqchip/sifive/plic:starting", 324 + plic_starting_cpu, plic_dying_cpu); 370 325 pr_info("mapped %d interrupts with %d handlers for %d contexts.\n", 371 326 nr_irqs, nr_handlers, nr_contexts); 372 327 set_handle_irq(plic_handle_irq); 373 328 return 0; 374 329 375 330 out_iounmap: 376 - iounmap(plic_regs); 331 + iounmap(priv->regs); 332 + out_free_priv: 333 + kfree(priv); 377 334 return error; 378 335 } 379 336

+13 -1

drivers/irqchip/irq-stm32-exti.c

··· 604 604 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 605 605 } 606 606 607 + static int stm32_exti_h_retrigger(struct irq_data *d) 608 + { 609 + struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 610 + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 611 + void __iomem *base = chip_data->host_data->base; 612 + u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 613 + 614 + writel_relaxed(mask, base + stm32_bank->swier_ofst); 615 + 616 + return 0; 617 + } 618 + 607 619 static struct irq_chip stm32_exti_h_chip = { 608 620 .name = "stm32-exti-h", 609 621 .irq_eoi = stm32_exti_h_eoi, 610 622 .irq_mask = stm32_exti_h_mask, 611 623 .irq_unmask = stm32_exti_h_unmask, 612 - .irq_retrigger = irq_chip_retrigger_hierarchy, 624 + .irq_retrigger = stm32_exti_h_retrigger, 613 625 .irq_set_type = stm32_exti_h_set_type, 614 626 .irq_set_wake = stm32_exti_h_set_wake, 615 627 .flags = IRQCHIP_MASK_ON_SUSPEND,

+13 -5

drivers/irqchip/irq-versatile-fpga.c

··· 6 6 #include <linux/irq.h> 7 7 #include <linux/io.h> 8 8 #include <linux/irqchip.h> 9 + #include <linux/irqchip/chained_irq.h> 9 10 #include <linux/irqchip/versatile-fpga.h> 10 11 #include <linux/irqdomain.h> 11 12 #include <linux/module.h> ··· 69 68 70 69 static void fpga_irq_handle(struct irq_desc *desc) 71 70 { 71 + struct irq_chip *chip = irq_desc_get_chip(desc); 72 72 struct fpga_irq_data *f = irq_desc_get_handler_data(desc); 73 - u32 status = readl(f->base + IRQ_STATUS); 73 + u32 status; 74 74 75 + chained_irq_enter(chip, desc); 76 + 77 + status = readl(f->base + IRQ_STATUS); 75 78 if (status == 0) { 76 79 do_bad_IRQ(desc); 77 - return; 80 + goto out; 78 81 } 79 82 80 83 do { ··· 87 82 status &= ~(1 << irq); 88 83 generic_handle_irq(irq_find_mapping(f->domain, irq)); 89 84 } while (status); 85 + 86 + out: 87 + chained_irq_exit(chip, desc); 90 88 } 91 89 92 90 /* ··· 212 204 if (of_property_read_u32(node, "valid-mask", &valid_mask)) 213 205 valid_mask = 0; 214 206 207 + writel(clear_mask, base + IRQ_ENABLE_CLEAR); 208 + writel(clear_mask, base + FIQ_ENABLE_CLEAR); 209 + 215 210 /* Some chips are cascaded from a parent IRQ */ 216 211 parent_irq = irq_of_parse_and_map(node, 0); 217 212 if (!parent_irq) { ··· 223 212 } 224 213 225 214 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); 226 - 227 - writel(clear_mask, base + IRQ_ENABLE_CLEAR); 228 - writel(clear_mask, base + FIQ_ENABLE_CLEAR); 229 215 230 216 /* 231 217 * On Versatile AB/PB, some secondary interrupts have a direct

+5 -4

drivers/irqchip/irq-vic.c

··· 509 509 void __iomem *regs; 510 510 u32 interrupt_mask = ~0; 511 511 u32 wakeup_mask = ~0; 512 - 513 - if (WARN(parent, "non-root VICs are not supported")) 514 - return -EINVAL; 512 + int parent_irq; 515 513 516 514 regs = of_iomap(node, 0); 517 515 if (WARN_ON(!regs)) ··· 517 519 518 520 of_property_read_u32(node, "valid-mask", &interrupt_mask); 519 521 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask); 522 + parent_irq = of_irq_get(node, 0); 523 + if (parent_irq < 0) 524 + parent_irq = 0; 520 525 521 526 /* 522 527 * Passing 0 as first IRQ makes the simple domain allocate descriptors 523 528 */ 524 - __vic_init(regs, 0, 0, interrupt_mask, wakeup_mask, node); 529 + __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node); 525 530 526 531 return 0; 527 532 }

+74 -49

drivers/irqchip/irq-xilinx-intc.c

··· 38 38 void __iomem *base; 39 39 struct irq_domain *root_domain; 40 40 u32 intr_mask; 41 + u32 nr_irq; 41 42 }; 42 43 43 - static struct xintc_irq_chip *xintc_irqc; 44 + static struct xintc_irq_chip *primary_intc; 44 45 45 - static void xintc_write(int reg, u32 data) 46 + static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data) 46 47 { 47 48 if (static_branch_unlikely(&xintc_is_be)) 48 - iowrite32be(data, xintc_irqc->base + reg); 49 + iowrite32be(data, irqc->base + reg); 49 50 else 50 - iowrite32(data, xintc_irqc->base + reg); 51 + iowrite32(data, irqc->base + reg); 51 52 } 52 53 53 - static unsigned int xintc_read(int reg) 54 + static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) 54 55 { 55 56 if (static_branch_unlikely(&xintc_is_be)) 56 - return ioread32be(xintc_irqc->base + reg); 57 + return ioread32be(irqc->base + reg); 57 58 else 58 - return ioread32(xintc_irqc->base + reg); 59 + return ioread32(irqc->base + reg); 59 60 } 60 61 61 62 static void intc_enable_or_unmask(struct irq_data *d) 62 63 { 63 - unsigned long mask = 1 << d->hwirq; 64 + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 65 + unsigned long mask = BIT(d->hwirq); 64 66 65 67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); 66 68 ··· 71 69 * acks the irq before calling the interrupt handler 72 70 */ 73 71 if (irqd_is_level_type(d)) 74 - xintc_write(IAR, mask); 72 + xintc_write(irqc, IAR, mask); 75 73 76 - xintc_write(SIE, mask); 74 + xintc_write(irqc, SIE, mask); 77 75 } 78 76 79 77 static void intc_disable_or_mask(struct irq_data *d) 80 78 { 79 + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 80 + 81 81 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); 82 - xintc_write(CIE, 1 << d->hwirq); 82 + xintc_write(irqc, CIE, BIT(d->hwirq)); 83 83 } 84 84 85 85 static void intc_ack(struct irq_data *d) 86 86 { 87 + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 88 + 87 89 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); 88 - xintc_write(IAR, 1 << d->hwirq); 90 + xintc_write(irqc, IAR, BIT(d->hwirq)); 89 91 } 90 92 91 93 static void intc_mask_ack(struct irq_data *d) 92 94 { 93 - unsigned long mask = 1 << d->hwirq; 95 + struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 96 + unsigned long mask = BIT(d->hwirq); 94 97 95 98 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); 96 - xintc_write(CIE, mask); 97 - xintc_write(IAR, mask); 99 + xintc_write(irqc, CIE, mask); 100 + xintc_write(irqc, IAR, mask); 98 101 } 99 102 100 103 static struct irq_chip intc_dev = { ··· 110 103 .irq_mask_ack = intc_mask_ack, 111 104 }; 112 105 113 - unsigned int xintc_get_irq(void) 106 + static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc) 114 107 { 115 - unsigned int hwirq, irq = -1; 108 + unsigned int irq = 0; 109 + u32 hwirq; 116 110 117 - hwirq = xintc_read(IVR); 111 + hwirq = xintc_read(irqc, IVR); 118 112 if (hwirq != -1U) 119 - irq = irq_find_mapping(xintc_irqc->root_domain, hwirq); 113 + irq = irq_find_mapping(irqc->root_domain, hwirq); 120 114 121 115 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); 122 116 ··· 126 118 127 119 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 128 120 { 129 - if (xintc_irqc->intr_mask & (1 << hw)) { 121 + struct xintc_irq_chip *irqc = d->host_data; 122 + 123 + if (irqc->intr_mask & BIT(hw)) { 130 124 irq_set_chip_and_handler_name(irq, &intc_dev, 131 - handle_edge_irq, "edge"); 125 + handle_edge_irq, "edge"); 132 126 irq_clear_status_flags(irq, IRQ_LEVEL); 133 127 } else { 134 128 irq_set_chip_and_handler_name(irq, &intc_dev, 135 - handle_level_irq, "level"); 129 + handle_level_irq, "level"); 136 130 irq_set_status_flags(irq, IRQ_LEVEL); 137 131 } 132 + irq_set_chip_data(irq, irqc); 138 133 return 0; 139 134 } 140 135 ··· 149 138 static void xil_intc_irq_handler(struct irq_desc *desc) 150 139 { 151 140 struct irq_chip *chip = irq_desc_get_chip(desc); 141 + struct xintc_irq_chip *irqc; 152 142 u32 pending; 153 143 144 + irqc = irq_data_get_irq_handler_data(&desc->irq_data); 154 145 chained_irq_enter(chip, desc); 155 146 do { 156 - pending = xintc_get_irq(); 157 - if (pending == -1U) 147 + pending = xintc_get_irq_local(irqc); 148 + if (pending == 0) 158 149 break; 159 150 generic_handle_irq(pending); 160 151 } while (true); 161 152 chained_irq_exit(chip, desc); 162 153 } 163 154 155 + static void xil_intc_handle_irq(struct pt_regs *regs) 156 + { 157 + u32 hwirq; 158 + struct xintc_irq_chip *irqc = primary_intc; 159 + 160 + do { 161 + hwirq = xintc_read(irqc, IVR); 162 + if (likely(hwirq != -1U)) { 163 + int ret; 164 + 165 + ret = handle_domain_irq(irqc->root_domain, hwirq, regs); 166 + WARN_ONCE(ret, "Unhandled HWIRQ %d\n", hwirq); 167 + continue; 168 + } 169 + 170 + break; 171 + } while (1); 172 + } 173 + 164 174 static int __init xilinx_intc_of_init(struct device_node *intc, 165 175 struct device_node *parent) 166 176 { 167 - u32 nr_irq; 168 - int ret, irq; 169 177 struct xintc_irq_chip *irqc; 170 - 171 - if (xintc_irqc) { 172 - pr_err("irq-xilinx: Multiple instances aren't supported\n"); 173 - return -EINVAL; 174 - } 178 + int ret, irq; 175 179 176 180 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); 177 181 if (!irqc) 178 182 return -ENOMEM; 179 - 180 - xintc_irqc = irqc; 181 - 182 183 irqc->base = of_iomap(intc, 0); 183 184 BUG_ON(!irqc->base); 184 185 185 - ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); 186 + ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq); 186 187 if (ret < 0) { 187 188 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); 188 - goto err_alloc; 189 + goto error; 189 190 } 190 191 191 192 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); ··· 206 183 irqc->intr_mask = 0; 207 184 } 208 185 209 - if (irqc->intr_mask >> nr_irq) 186 + if (irqc->intr_mask >> irqc->nr_irq) 210 187 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); 211 188 212 189 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", 213 - intc, nr_irq, irqc->intr_mask); 190 + intc, irqc->nr_irq, irqc->intr_mask); 214 191 215 192 216 193 /* 217 194 * Disable all external interrupts until they are 218 195 * explicity requested. 219 196 */ 220 - xintc_write(IER, 0); 197 + xintc_write(irqc, IER, 0); 221 198 222 199 /* Acknowledge any pending interrupts just in case. */ 223 - xintc_write(IAR, 0xffffffff); 200 + xintc_write(irqc, IAR, 0xffffffff); 224 201 225 202 /* Turn on the Master Enable. */ 226 - xintc_write(MER, MER_HIE | MER_ME); 227 - if (!(xintc_read(MER) & (MER_HIE | MER_ME))) { 203 + xintc_write(irqc, MER, MER_HIE | MER_ME); 204 + if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) { 228 205 static_branch_enable(&xintc_is_be); 229 - xintc_write(MER, MER_HIE | MER_ME); 206 + xintc_write(irqc, MER, MER_HIE | MER_ME); 230 207 } 231 208 232 - irqc->root_domain = irq_domain_add_linear(intc, nr_irq, 209 + irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq, 233 210 &xintc_irq_domain_ops, irqc); 234 211 if (!irqc->root_domain) { 235 212 pr_err("irq-xilinx: Unable to create IRQ domain\n"); 236 - goto err_alloc; 213 + ret = -EINVAL; 214 + goto error; 237 215 } 238 216 239 217 if (parent) { ··· 246 222 } else { 247 223 pr_err("irq-xilinx: interrupts property not in DT\n"); 248 224 ret = -EINVAL; 249 - goto err_alloc; 225 + goto error; 250 226 } 251 227 } else { 252 - irq_set_default_host(irqc->root_domain); 228 + primary_intc = irqc; 229 + set_handle_irq(xil_intc_handle_irq); 253 230 } 254 231 255 232 return 0; 256 233 257 - err_alloc: 258 - xintc_irqc = NULL; 234 + error: 235 + iounmap(irqc->base); 259 236 kfree(irqc); 260 237 return ret; 261 238

+1 -1

drivers/irqchip/qcom-irq-combiner.c

··· 33 33 int parent_irq; 34 34 u32 nirqs; 35 35 u32 nregs; 36 - struct combiner_reg regs[0]; 36 + struct combiner_reg regs[]; 37 37 }; 38 38 39 39 static inline int irq_nr(u32 reg, u32 bit)

+1

drivers/pci/pcie/Kconfig

··· 34 34 config PCIEAER_INJECT 35 35 tristate "PCI Express error injection support" 36 36 depends on PCIEAER 37 + select GENERIC_IRQ_INJECTION 37 38 help 38 39 This enables PCI Express Root Port Advanced Error Reporting 39 40 (AER) software error injector.

+2 -4

drivers/pci/pcie/aer_inject.c

··· 16 16 17 17 #include <linux/module.h> 18 18 #include <linux/init.h> 19 - #include <linux/irq.h> 19 + #include <linux/interrupt.h> 20 20 #include <linux/miscdevice.h> 21 21 #include <linux/pci.h> 22 22 #include <linux/slab.h> ··· 468 468 } 469 469 pci_info(edev->port, "Injecting errors %08x/%08x into device %s\n", 470 470 einj->cor_status, einj->uncor_status, pci_name(dev)); 471 - local_irq_disable(); 472 - generic_handle_irq(edev->irq); 473 - local_irq_enable(); 471 + ret = irq_inject_interrupt(edev->irq); 474 472 } else { 475 473 pci_err(rpdev, "AER device not found\n"); 476 474 ret = -ENODEV;

+54 -3

drivers/pinctrl/stm32/pinctrl-stm32.c

··· 92 92 u32 bank_nr; 93 93 u32 bank_ioport_nr; 94 94 u32 pin_backup[STM32_GPIO_PINS_PER_BANK]; 95 + u8 irq_type[STM32_GPIO_PINS_PER_BANK]; 95 96 }; 96 97 97 98 struct stm32_pinctrl { ··· 304 303 .get_direction = stm32_gpio_get_direction, 305 304 }; 306 305 306 + static void stm32_gpio_irq_trigger(struct irq_data *d) 307 + { 308 + struct stm32_gpio_bank *bank = d->domain->host_data; 309 + int level; 310 + 311 + /* If level interrupt type then retrig */ 312 + level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); 313 + if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || 314 + (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) 315 + irq_chip_retrigger_hierarchy(d); 316 + } 317 + 318 + static void stm32_gpio_irq_eoi(struct irq_data *d) 319 + { 320 + irq_chip_eoi_parent(d); 321 + stm32_gpio_irq_trigger(d); 322 + }; 323 + 324 + static int stm32_gpio_set_type(struct irq_data *d, unsigned int type) 325 + { 326 + struct stm32_gpio_bank *bank = d->domain->host_data; 327 + u32 parent_type; 328 + 329 + switch (type) { 330 + case IRQ_TYPE_EDGE_RISING: 331 + case IRQ_TYPE_EDGE_FALLING: 332 + case IRQ_TYPE_EDGE_BOTH: 333 + parent_type = type; 334 + break; 335 + case IRQ_TYPE_LEVEL_HIGH: 336 + parent_type = IRQ_TYPE_EDGE_RISING; 337 + break; 338 + case IRQ_TYPE_LEVEL_LOW: 339 + parent_type = IRQ_TYPE_EDGE_FALLING; 340 + break; 341 + default: 342 + return -EINVAL; 343 + } 344 + 345 + bank->irq_type[d->hwirq] = type; 346 + 347 + return irq_chip_set_type_parent(d, parent_type); 348 + }; 349 + 307 350 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) 308 351 { 309 352 struct stm32_gpio_bank *bank = irq_data->domain->host_data; ··· 375 330 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); 376 331 } 377 332 333 + static void stm32_gpio_irq_unmask(struct irq_data *d) 334 + { 335 + irq_chip_unmask_parent(d); 336 + stm32_gpio_irq_trigger(d); 337 + } 338 + 378 339 static struct irq_chip stm32_gpio_irq_chip = { 379 340 .name = "stm32gpio", 380 - .irq_eoi = irq_chip_eoi_parent, 341 + .irq_eoi = stm32_gpio_irq_eoi, 381 342 .irq_ack = irq_chip_ack_parent, 382 343 .irq_mask = irq_chip_mask_parent, 383 - .irq_unmask = irq_chip_unmask_parent, 384 - .irq_set_type = irq_chip_set_type_parent, 344 + .irq_unmask = stm32_gpio_irq_unmask, 345 + .irq_set_type = stm32_gpio_set_type, 385 346 .irq_set_wake = irq_chip_set_wake_parent, 386 347 .irq_request_resources = stm32_gpio_irq_request_resources, 387 348 .irq_release_resources = stm32_gpio_irq_release_resources,

+1

include/kvm/arm_vgic.h

··· 70 70 71 71 /* Hardware has GICv4? */ 72 72 bool has_gicv4; 73 + bool has_gicv4_1; 73 74 74 75 /* GIC system register CPU interface */ 75 76 struct static_key_false gicv3_cpuif;

+1

include/linux/cpuhotplug.h

··· 102 102 CPUHP_AP_IRQ_ARMADA_XP_STARTING, 103 103 CPUHP_AP_IRQ_BCM2836_STARTING, 104 104 CPUHP_AP_IRQ_MIPS_GIC_STARTING, 105 + CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 105 106 CPUHP_AP_ARM_MVEBU_COHERENCY, 106 107 CPUHP_AP_MICROCODE_LOADER, 107 108 CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING,

+2

include/linux/interrupt.h

··· 248 248 extern int prepare_percpu_nmi(unsigned int irq); 249 249 extern void teardown_percpu_nmi(unsigned int irq); 250 250 251 + extern int irq_inject_interrupt(unsigned int irq); 252 + 251 253 /* The following three functions are for the core kernel use only. */ 252 254 extern void suspend_device_irqs(void); 253 255 extern void resume_device_irqs(void);

+13

include/linux/irq.h

··· 211 211 * IRQD_CAN_RESERVE - Can use reservation mode 212 212 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change 213 213 * required 214 + * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 215 + * from actual interrupt context. 214 216 */ 215 217 enum { 216 218 IRQD_TRIGGER_MASK = 0xf, ··· 236 234 IRQD_DEFAULT_TRIGGER_SET = (1 << 25), 237 235 IRQD_CAN_RESERVE = (1 << 26), 238 236 IRQD_MSI_NOMASK_QUIRK = (1 << 27), 237 + IRQD_HANDLE_ENFORCE_IRQCTX = (1 << 28), 239 238 }; 240 239 241 240 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) ··· 304 301 static inline bool irqd_is_single_target(struct irq_data *d) 305 302 { 306 303 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 304 + } 305 + 306 + static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 307 + { 308 + __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 309 + } 310 + 311 + static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 312 + { 313 + return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 307 314 } 308 315 309 316 static inline bool irqd_is_wakeup_set(struct irq_data *d)

+2

include/linux/irqchip/arm-gic-common.h

··· 32 32 struct resource vctrl; 33 33 /* vlpi support */ 34 34 bool has_v4; 35 + /* rvpeid support */ 36 + bool has_v4_1; 35 37 }; 36 38 37 39 const struct gic_kvm_info *gic_get_kvm_info(void);

+22 -1

include/linux/irqchip/arm-gic-v3.h

··· 57 57 #define GICD_SPENDSGIR 0x0F20 58 58 59 59 #define GICD_CTLR_RWP (1U << 31) 60 + #define GICD_CTLR_nASSGIreq (1U << 8) 60 61 #define GICD_CTLR_DS (1U << 6) 61 62 #define GICD_CTLR_ARE_NS (1U << 4) 62 63 #define GICD_CTLR_ENABLE_G1A (1U << 1) ··· 91 90 #define GICD_TYPER_ESPIS(typer) \ 92 91 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) 93 92 93 + #define GICD_TYPER2_nASSGIcap (1U << 8) 94 94 #define GICD_TYPER2_VIL (1U << 7) 95 95 #define GICD_TYPER2_VID GENMASK(4, 0) 96 96 ··· 322 320 #define GICR_VPENDBASER_NonShareable \ 323 321 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable) 324 322 323 + #define GICR_VPENDBASER_InnerShareable \ 324 + GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable) 325 + 325 326 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB) 326 327 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC) 327 328 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt) ··· 348 343 #define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58) 349 344 #define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0) 350 345 346 + #define GICR_VSGIR 0x0080 347 + 348 + #define GICR_VSGIR_VPEID GENMASK(15, 0) 349 + 350 + #define GICR_VSGIPENDR 0x0088 351 + 352 + #define GICR_VSGIPENDR_BUSY (1U << 31) 353 + #define GICR_VSGIPENDR_PENDING GENMASK(15, 0) 354 + 351 355 /* 352 356 * ITS registers, offsets from ITS_base 353 357 */ ··· 379 365 #define GITS_CIDR3 0xfffc 380 366 381 367 #define GITS_TRANSLATER 0x10040 368 + 369 + #define GITS_SGIR 0x20020 370 + 371 + #define GITS_SGIR_VPEID GENMASK_ULL(47, 32) 372 + #define GITS_SGIR_VINTID GENMASK_ULL(3, 0) 382 373 383 374 #define GITS_CTLR_ENABLE (1U << 0) 384 375 #define GITS_CTLR_ImDe (1U << 1) ··· 519 500 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI) 520 501 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI) 521 502 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC) 522 - /* VMOVP and INVDB are the odd ones, as they dont have a physical counterpart */ 503 + /* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */ 523 504 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2) 505 + #define GITS_CMD_VSGI GITS_CMD_GICv4(3) 524 506 #define GITS_CMD_INVDB GITS_CMD_GICv4(0xe) 525 507 526 508 /* ··· 670 650 671 651 struct rdists { 672 652 struct { 653 + raw_spinlock_t rd_lock; 673 654 void __iomem *rd_base; 674 655 struct page *pend_page; 675 656 phys_addr_t phys_base;

+23 -2

include/linux/irqchip/arm-gic-v4.h

··· 49 49 }; 50 50 /* GICv4.1 implementations */ 51 51 struct { 52 + struct fwnode_handle *fwnode; 53 + struct irq_domain *sgi_domain; 54 + struct { 55 + u8 priority; 56 + bool enabled; 57 + bool group; 58 + } sgi_config[16]; 52 59 atomic_t vmapp_count; 53 60 }; 54 61 }; 55 62 63 + /* 64 + * Ensures mutual exclusion between affinity setting of the 65 + * vPE and vLPI operations using vpe->col_idx. 66 + */ 67 + raw_spinlock_t vpe_lock; 56 68 /* 57 69 * This collection ID is used to indirect the target 58 70 * redistributor for this VPE. The ID itself isn't involved in ··· 105 93 SCHEDULE_VPE, 106 94 DESCHEDULE_VPE, 107 95 INVALL_VPE, 96 + PROP_UPDATE_VSGI, 108 97 }; 109 98 110 99 struct its_cmd_info { ··· 118 105 bool g0en; 119 106 bool g1en; 120 107 }; 108 + struct { 109 + u8 priority; 110 + bool group; 111 + }; 121 112 }; 122 113 }; 123 114 124 115 int its_alloc_vcpu_irqs(struct its_vm *vm); 125 116 void its_free_vcpu_irqs(struct its_vm *vm); 126 - int its_schedule_vpe(struct its_vpe *vpe, bool on); 117 + int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en); 118 + int its_make_vpe_non_resident(struct its_vpe *vpe, bool db); 127 119 int its_invall_vpe(struct its_vpe *vpe); 128 120 int its_map_vlpi(int irq, struct its_vlpi_map *map); 129 121 int its_get_vlpi(int irq, struct its_vlpi_map *map); 130 122 int its_unmap_vlpi(int irq); 131 123 int its_prop_update_vlpi(int irq, u8 config, bool inv); 124 + int its_prop_update_vsgi(int irq, u8 priority, bool group); 132 125 133 126 struct irq_domain_ops; 134 - int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops); 127 + int its_init_v4(struct irq_domain *domain, 128 + const struct irq_domain_ops *vpe_ops, 129 + const struct irq_domain_ops *sgi_ops); 135 130 136 131 #endif

+5

kernel/irq/Kconfig

··· 43 43 config AUTO_IRQ_AFFINITY 44 44 bool 45 45 46 + # Interrupt injection mechanism 47 + config GENERIC_IRQ_INJECTION 48 + bool 49 + 46 50 # Tasklet based software resend for pending interrupts on enable_irq() 47 51 config HARDIRQS_SW_RESEND 48 52 bool ··· 131 127 config GENERIC_IRQ_DEBUGFS 132 128 bool "Expose irq internals in debugfs" 133 129 depends on DEBUG_FS 130 + select GENERIC_IRQ_INJECTION 134 131 default n 135 132 ---help--- 136 133

+1 -1

kernel/irq/chip.c

··· 278 278 } 279 279 } 280 280 if (resend) 281 - check_irq_resend(desc); 281 + check_irq_resend(desc, false); 282 282 283 283 return ret; 284 284 }

+1 -27

kernel/irq/debugfs.c

··· 190 190 return -EFAULT; 191 191 192 192 if (!strncmp(buf, "trigger", size)) { 193 - unsigned long flags; 194 - int err; 195 - 196 - /* Try the HW interface first */ 197 - err = irq_set_irqchip_state(irq_desc_get_irq(desc), 198 - IRQCHIP_STATE_PENDING, true); 199 - if (!err) 200 - return count; 201 - 202 - /* 203 - * Otherwise, try to inject via the resend interface, 204 - * which may or may not succeed. 205 - */ 206 - chip_bus_lock(desc); 207 - raw_spin_lock_irqsave(&desc->lock, flags); 208 - 209 - if (irq_settings_is_level(desc) || desc->istate & IRQS_NMI) { 210 - /* Can't do level nor NMIs, sorry */ 211 - err = -EINVAL; 212 - } else { 213 - desc->istate |= IRQS_PENDING; 214 - check_irq_resend(desc); 215 - err = 0; 216 - } 217 - 218 - raw_spin_unlock_irqrestore(&desc->lock, flags); 219 - chip_bus_sync_unlock(desc); 193 + int err = irq_inject_interrupt(irq_desc_get_irq(desc)); 220 194 221 195 return err ? err : count; 222 196 }

+9 -1

kernel/irq/internals.h

··· 108 108 irqreturn_t handle_irq_event(struct irq_desc *desc); 109 109 110 110 /* Resending of interrupts :*/ 111 - void check_irq_resend(struct irq_desc *desc); 111 + int check_irq_resend(struct irq_desc *desc, bool inject); 112 112 bool irq_wait_for_poll(struct irq_desc *desc); 113 113 void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action); 114 114 ··· 425 425 { 426 426 return desc->pending_mask; 427 427 } 428 + static inline bool handle_enforce_irqctx(struct irq_data *data) 429 + { 430 + return irqd_is_handle_enforce_irqctx(data); 431 + } 428 432 bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear); 429 433 #else /* CONFIG_GENERIC_PENDING_IRQ */ 430 434 static inline bool irq_can_move_pcntxt(struct irq_data *data) ··· 452 448 return NULL; 453 449 } 454 450 static inline bool irq_fixup_move_pending(struct irq_desc *desc, bool fclear) 451 + { 452 + return false; 453 + } 454 + static inline bool handle_enforce_irqctx(struct irq_data *data) 455 455 { 456 456 return false; 457 457 }

+6

kernel/irq/irqdesc.c

··· 638 638 int generic_handle_irq(unsigned int irq) 639 639 { 640 640 struct irq_desc *desc = irq_to_desc(irq); 641 + struct irq_data *data; 641 642 642 643 if (!desc) 643 644 return -EINVAL; 645 + 646 + data = irq_desc_get_irq_data(desc); 647 + if (WARN_ON_ONCE(!in_irq() && handle_enforce_irqctx(data))) 648 + return -EPERM; 649 + 644 650 generic_handle_irq_desc(desc); 645 651 return 0; 646 652 }

+7 -7

kernel/irq/irqdomain.c

··· 46 46 EXPORT_SYMBOL_GPL(irqchip_fwnode_ops); 47 47 48 48 /** 49 - * irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for 49 + * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for 50 50 * identifying an irq domain 51 51 * @type: Type of irqchip_fwnode. See linux/irqdomain.h 52 - * @name: Optional user provided domain name 53 52 * @id: Optional user provided id if name != NULL 53 + * @name: Optional user provided domain name 54 54 * @pa: Optional user-provided physical address 55 55 * 56 56 * Allocate a struct irqchip_fwid, and return a poiner to the embedded ··· 1310 1310 unsigned int irq_base, 1311 1311 unsigned int nr_irqs, void *arg) 1312 1312 { 1313 + if (!domain->ops->alloc) { 1314 + pr_debug("domain->ops->alloc() is NULL\n"); 1315 + return -ENOSYS; 1316 + } 1317 + 1313 1318 return domain->ops->alloc(domain, irq_base, nr_irqs, arg); 1314 1319 } 1315 1320 ··· 1350 1345 domain = irq_default_domain; 1351 1346 if (WARN(!domain, "domain is NULL; cannot allocate IRQ\n")) 1352 1347 return -EINVAL; 1353 - } 1354 - 1355 - if (!domain->ops->alloc) { 1356 - pr_debug("domain->ops->alloc() is NULL\n"); 1357 - return -ENOSYS; 1358 1348 } 1359 1349 1360 1350 if (realloc && irq_base >= 0) {

+108 -37

kernel/irq/resend.c

··· 47 47 /* Tasklet to handle resend: */ 48 48 static DECLARE_TASKLET(resend_tasklet, resend_irqs, 0); 49 49 50 + static int irq_sw_resend(struct irq_desc *desc) 51 + { 52 + unsigned int irq = irq_desc_get_irq(desc); 53 + 54 + /* 55 + * Validate whether this interrupt can be safely injected from 56 + * non interrupt context 57 + */ 58 + if (handle_enforce_irqctx(&desc->irq_data)) 59 + return -EINVAL; 60 + 61 + /* 62 + * If the interrupt is running in the thread context of the parent 63 + * irq we need to be careful, because we cannot trigger it 64 + * directly. 65 + */ 66 + if (irq_settings_is_nested_thread(desc)) { 67 + /* 68 + * If the parent_irq is valid, we retrigger the parent, 69 + * otherwise we do nothing. 70 + */ 71 + if (!desc->parent_irq) 72 + return -EINVAL; 73 + irq = desc->parent_irq; 74 + } 75 + 76 + /* Set it pending and activate the softirq: */ 77 + set_bit(irq, irqs_resend); 78 + tasklet_schedule(&resend_tasklet); 79 + return 0; 80 + } 81 + 82 + #else 83 + static int irq_sw_resend(struct irq_desc *desc) 84 + { 85 + return -EINVAL; 86 + } 50 87 #endif 51 88 52 89 /* ··· 91 54 * 92 55 * Is called with interrupts disabled and desc->lock held. 93 56 */ 94 - void check_irq_resend(struct irq_desc *desc) 57 + int check_irq_resend(struct irq_desc *desc, bool inject) 95 58 { 59 + int err = 0; 60 + 96 61 /* 97 - * We do not resend level type interrupts. Level type 98 - * interrupts are resent by hardware when they are still 99 - * active. Clear the pending bit so suspend/resume does not 100 - * get confused. 62 + * We do not resend level type interrupts. Level type interrupts 63 + * are resent by hardware when they are still active. Clear the 64 + * pending bit so suspend/resume does not get confused. 101 65 */ 102 66 if (irq_settings_is_level(desc)) { 103 67 desc->istate &= ~IRQS_PENDING; 104 - return; 68 + return -EINVAL; 105 69 } 70 + 106 71 if (desc->istate & IRQS_REPLAY) 107 - return; 108 - if (desc->istate & IRQS_PENDING) { 109 - desc->istate &= ~IRQS_PENDING; 72 + return -EBUSY; 73 + 74 + if (!(desc->istate & IRQS_PENDING) && !inject) 75 + return 0; 76 + 77 + desc->istate &= ~IRQS_PENDING; 78 + 79 + if (!desc->irq_data.chip->irq_retrigger || 80 + !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) 81 + err = irq_sw_resend(desc); 82 + 83 + /* If the retrigger was successfull, mark it with the REPLAY bit */ 84 + if (!err) 110 85 desc->istate |= IRQS_REPLAY; 111 - 112 - if (!desc->irq_data.chip->irq_retrigger || 113 - !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) { 114 - #ifdef CONFIG_HARDIRQS_SW_RESEND 115 - unsigned int irq = irq_desc_get_irq(desc); 116 - 117 - /* 118 - * If the interrupt is running in the thread 119 - * context of the parent irq we need to be 120 - * careful, because we cannot trigger it 121 - * directly. 122 - */ 123 - if (irq_settings_is_nested_thread(desc)) { 124 - /* 125 - * If the parent_irq is valid, we 126 - * retrigger the parent, otherwise we 127 - * do nothing. 128 - */ 129 - if (!desc->parent_irq) 130 - return; 131 - irq = desc->parent_irq; 132 - } 133 - /* Set it pending and activate the softirq: */ 134 - set_bit(irq, irqs_resend); 135 - tasklet_schedule(&resend_tasklet); 136 - #endif 137 - } 138 - } 86 + return err; 139 87 } 88 + 89 + #ifdef CONFIG_GENERIC_IRQ_INJECTION 90 + /** 91 + * irq_inject_interrupt - Inject an interrupt for testing/error injection 92 + * @irq: The interrupt number 93 + * 94 + * This function must only be used for debug and testing purposes! 95 + * 96 + * Especially on x86 this can cause a premature completion of an interrupt 97 + * affinity change causing the interrupt line to become stale. Very 98 + * unlikely, but possible. 99 + * 100 + * The injection can fail for various reasons: 101 + * - Interrupt is not activated 102 + * - Interrupt is NMI type or currently replaying 103 + * - Interrupt is level type 104 + * - Interrupt does not support hardware retrigger and software resend is 105 + * either not enabled or not possible for the interrupt. 106 + */ 107 + int irq_inject_interrupt(unsigned int irq) 108 + { 109 + struct irq_desc *desc; 110 + unsigned long flags; 111 + int err; 112 + 113 + /* Try the state injection hardware interface first */ 114 + if (!irq_set_irqchip_state(irq, IRQCHIP_STATE_PENDING, true)) 115 + return 0; 116 + 117 + /* That failed, try via the resend mechanism */ 118 + desc = irq_get_desc_buslock(irq, &flags, 0); 119 + if (!desc) 120 + return -EINVAL; 121 + 122 + /* 123 + * Only try to inject when the interrupt is: 124 + * - not NMI type 125 + * - activated 126 + */ 127 + if ((desc->istate & IRQS_NMI) || !irqd_is_activated(&desc->irq_data)) 128 + err = -EINVAL; 129 + else 130 + err = check_irq_resend(desc, true); 131 + 132 + irq_put_desc_busunlock(desc, flags); 133 + return err; 134 + } 135 + EXPORT_SYMBOL_GPL(irq_inject_interrupt); 136 + #endif

+3 -1

virt/kvm/arm/vgic/vgic-v3.c

··· 595 595 /* GICv4 support? */ 596 596 if (info->has_v4) { 597 597 kvm_vgic_global_state.has_gicv4 = gicv4_enable; 598 - kvm_info("GICv4 support %sabled\n", 598 + kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable; 599 + kvm_info("GICv4%s support %sabled\n", 600 + kvm_vgic_global_state.has_gicv4_1 ? ".1" : "", 599 601 gicv4_enable ? "en" : "dis"); 600 602 } 601 603

+14 -20

virt/kvm/arm/vgic/vgic-v4.c

··· 67 67 * it. And if we've migrated our vcpu from one CPU to another, we must 68 68 * tell the ITS (so that the messages reach the right redistributor). 69 69 * This is done in two steps: first issue a irq_set_affinity() on the 70 - * irq corresponding to the vcpu, then call its_schedule_vpe(). You 71 - * must be in a non-preemptible context. On exit, another call to 72 - * its_schedule_vpe() tells the redistributor that we're done with the 73 - * vcpu. 70 + * irq corresponding to the vcpu, then call its_make_vpe_resident(). 71 + * You must be in a non-preemptible context. On exit, a call to 72 + * its_make_vpe_non_resident() tells the redistributor that we're done 73 + * with the vcpu. 74 74 * 75 75 * Finally, the doorbell handling: Each vcpu is allocated an interrupt 76 76 * which will fire each time a VLPI is made pending whilst the vcpu is ··· 86 86 struct kvm_vcpu *vcpu = info; 87 87 88 88 /* We got the message, no need to fire again */ 89 - if (!irqd_irq_disabled(&irq_to_desc(irq)->irq_data)) 89 + if (!kvm_vgic_global_state.has_gicv4_1 && 90 + !irqd_irq_disabled(&irq_to_desc(irq)->irq_data)) 90 91 disable_irq_nosync(irq); 91 92 92 93 vcpu->arch.vgic_cpu.vgic_v3.its_vpe.pending_last = true; ··· 200 199 int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db) 201 200 { 202 201 struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; 203 - struct irq_desc *desc = irq_to_desc(vpe->irq); 204 202 205 203 if (!vgic_supports_direct_msis(vcpu->kvm) || !vpe->resident) 206 204 return 0; 207 205 208 - /* 209 - * If blocking, a doorbell is required. Undo the nested 210 - * disable_irq() calls... 211 - */ 212 - while (need_db && irqd_irq_disabled(&desc->irq_data)) 213 - enable_irq(vpe->irq); 214 - 215 - return its_schedule_vpe(vpe, false); 206 + return its_make_vpe_non_resident(vpe, need_db); 216 207 } 217 208 218 209 int vgic_v4_load(struct kvm_vcpu *vcpu) ··· 225 232 if (err) 226 233 return err; 227 234 228 - /* Disabled the doorbell, as we're about to enter the guest */ 229 - disable_irq_nosync(vpe->irq); 230 - 231 - err = its_schedule_vpe(vpe, true); 235 + err = its_make_vpe_resident(vpe, false, vcpu->kvm->arch.vgic.enabled); 232 236 if (err) 233 237 return err; 234 238 235 239 /* 236 240 * Now that the VPE is resident, let's get rid of a potential 237 - * doorbell interrupt that would still be pending. 241 + * doorbell interrupt that would still be pending. This is a 242 + * GICv4.0 only "feature"... 238 243 */ 239 - return irq_set_irqchip_state(vpe->irq, IRQCHIP_STATE_PENDING, false); 244 + if (!kvm_vgic_global_state.has_gicv4_1) 245 + err = irq_set_irqchip_state(vpe->irq, IRQCHIP_STATE_PENDING, false); 246 + 247 + return err; 240 248 } 241 249 242 250 static struct vgic_its *vgic_get_its(struct kvm *kvm,

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