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dt-bindings: clock: samsung: remove define with number of clocks for FSD

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240917094355.37887-3-inbaraj.e@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Inbaraj E and committed by
Krzysztof Kozlowski 2d3e0135 a86ffa40

-7
-7
include/dt-bindings/clock/fsd-clk.h
··· 28 28 #define DOUT_CMU_IMEM_ACLK 13 29 29 #define DOUT_CMU_IMEM_DMACLK 14 30 30 #define GAT_CMU_FSYS0_SHARED0DIV4 15 31 - #define CMU_NR_CLK 16 32 31 33 32 /* PERIC */ 34 33 #define PERIC_SCLK_UART0 1 ··· 75 76 #define PERIC_EQOS_PHYRXCLK_MUX 43 76 77 #define PERIC_EQOS_PHYRXCLK 44 77 78 #define PERIC_DOUT_RGMII_CLK 45 78 - #define PERIC_NR_CLK 46 79 79 80 80 /* FSYS0 */ 81 81 #define UFS0_MPHY_REFCLK_IXTAL24 1 ··· 99 101 #define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 100 102 #define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 101 103 #define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 102 - #define FSYS0_NR_CLK 23 103 104 104 105 /* FSYS1 */ 105 106 #define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 ··· 109 112 #define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 110 113 #define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 111 114 #define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 112 - #define FSYS1_NR_CLK 9 113 115 114 116 /* IMEM */ 115 117 #define IMEM_DMA0_IPCLKPORT_ACLK 1 ··· 122 126 #define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 123 127 #define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 124 128 #define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 125 - #define IMEM_NR_CLK 12 126 129 127 130 /* MFC */ 128 131 #define MFC_MFC_IPCLKPORT_ACLK 1 129 - #define MFC_NR_CLK 2 130 132 131 133 /* CAM_CSI */ 132 134 #define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 ··· 139 145 #define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 140 146 #define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 141 147 #define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 142 - #define CAM_CSI_NR_CLK 13 143 148 144 149 #endif /*_DT_BINDINGS_CLOCK_FSD_H */