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perf/arm-ni: Fix and optimise register offset calculation

LKP points out an operator precedence oversight in the new NoC S3
support that, annoyingly, my local W=1 build didn't flag. In fixing
that, we can also take the similarly-missed opportunity to cache the
version check itself at event_init time.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202511041749.ok8zDP6u-lkp@intel.com/
Fixes: 8fa08f8835e5 ("perf/arm-ni: Add NoC S3 support")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>

authored by

Robin Murphy and committed by
Will Deacon 2d7a8248 989b40b7

+12 -9
+12 -9
drivers/perf/arm-ni.c
··· 323 323 return 0; 324 324 } 325 325 326 + static bool arm_ni_is_7xx(const struct arm_ni *ni) 327 + { 328 + return ni->part == PART_NI_700 || ni->part == PART_NI_710AE; 329 + } 330 + 326 331 static int arm_ni_event_init(struct perf_event *event) 327 332 { 328 333 struct arm_ni_cd *cd = pmu_to_cd(event->pmu); 334 + struct arm_ni *ni; 329 335 330 336 if (event->attr.type != event->pmu->type) 331 337 return -ENOENT; ··· 339 333 if (is_sampling_event(event)) 340 334 return -EINVAL; 341 335 342 - event->cpu = cd_to_ni(cd)->cpu; 336 + ni = cd_to_ni(cd); 337 + event->cpu = ni->cpu; 338 + event->hw.flags = arm_ni_is_7xx(ni); 339 + 343 340 if (NI_EVENT_TYPE(event) == NI_PMU) 344 341 return arm_ni_validate_group(event); 345 342 ··· 420 411 writel_relaxed(S32_MIN, (void __iomem *)hw->event_base); 421 412 } 422 413 423 - static bool arm_ni_is_7xx(const struct arm_ni *ni) 424 - { 425 - return ni->part == PART_NI_700 || ni->part == PART_NI_710AE; 426 - } 427 - 428 414 static int arm_ni_event_add(struct perf_event *event, int flags) 429 415 { 430 416 struct arm_ni_cd *cd = pmu_to_cd(event->pmu); 431 417 struct hw_perf_event *hw = &event->hw; 432 418 struct arm_ni_unit *unit; 433 419 enum ni_node_type type = NI_EVENT_TYPE(event); 434 - bool is_7xx = arm_ni_is_7xx(cd_to_ni(cd)); 435 420 u32 reg; 436 421 437 422 if (type == NI_PMU) { ··· 433 430 return -ENOSPC; 434 431 hw->idx = NI_CCNT_IDX; 435 432 hw->event_base = (unsigned long)cd->pmu_base + 436 - is_7xx ? NI700_PMCCNTR_L : NI_PMCCNTR_L; 433 + (hw->flags ? NI700_PMCCNTR_L : NI_PMCCNTR_L); 437 434 cd->ccnt = event; 438 435 arm_ni_init_ccnt(hw); 439 436 } else { ··· 446 443 unit = (void *)hw->config_base; 447 444 unit->event[hw->idx] = NI_EVENT_EVENTID(event); 448 445 hw->event_base = (unsigned long)cd->pmu_base + 449 - is_7xx ? NI700_PMEVCNTR(hw->idx) : NI_PMEVCNTR(hw->idx); 446 + (hw->flags ? NI700_PMEVCNTR(hw->idx) : NI_PMEVCNTR(hw->idx)); 450 447 arm_ni_init_evcnt(hw); 451 448 lo_hi_writeq_relaxed(le64_to_cpu(unit->pmusel), unit->pmusela); 452 449