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phy: ti: gmii-sel: Enable SGMII mode for J721E

TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Siddharth Vadapalli and committed by
Vinod Koul 2de2e49b 178b6515

+1 -1
+1 -1
drivers/phy/ti/phy-gmii-sel.c
··· 230 230 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { 231 231 .use_of_data = true, 232 232 .regfields = phy_gmii_sel_fields_am654, 233 - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 233 + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 234 234 .num_ports = 8, 235 235 .num_qsgmii_main_ports = 2, 236 236 };