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drm/msm/dpu: Add CWB to msm_display_topology

Currently, the topology is calculated based on the assumption that the
user cannot request real-time and writeback simultaneously. For example,
the number of LMs and CTLs are currently based off the number of phys
encoders under the assumption there will be at least 1 LM/CTL per phys
encoder.

This will not hold true for concurrent writeback as both phys encoders
(1 real-time and 1 writeback) must be driven by 1 LM/CTL when concurrent
writeback is enabled.

To account for this, add a cwb_enabled flag and only adjust the number of
CTL/LMs needed by a given topology based on the number of phys encoders
only if CWB is not enabled.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/637486/
Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-4-a44c293cf422@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

authored by

Jessica Zhang and committed by
Dmitry Baryshkov 2ea34682 cae6a13a

+24 -3
+10 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
··· 1246 1246 dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, 1247 1247 &crtc_state->adjusted_mode); 1248 1248 1249 + topology.cwb_enabled = drm_crtc_in_clone_mode(crtc_state); 1250 + 1249 1251 /* 1250 1252 * Datapath topology selection 1251 1253 * ··· 1261 1259 * If DSC is enabled, use 2 LMs for 2:2:1 topology 1262 1260 * 1263 1261 * Add dspps to the reservation requirements if ctm is requested 1262 + * 1263 + * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is not 1264 + * enabled. This is because in cases where CWB is enabled, num_intf will 1265 + * count both the WB and real-time phys encoders. 1266 + * 1267 + * For non-DSC CWB usecases, have the num_lm be decided by the 1268 + * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. 1264 1269 */ 1265 1270 1266 - if (topology.num_intf == 2) 1271 + if (topology.num_intf == 2 && !topology.cwb_enabled) 1267 1272 topology.num_lm = 2; 1268 1273 else if (topology.num_dsc == 2) 1269 1274 topology.num_lm = 2;
+12 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
··· 381 381 int i = 0, j, num_ctls; 382 382 bool needs_split_display; 383 383 384 - /* each hw_intf needs its own hw_ctrl to program its control path */ 385 - num_ctls = top->num_intf; 384 + /* 385 + * For non-CWB mode, each hw_intf needs its own hw_ctl to program its 386 + * control path. 387 + * 388 + * Hardcode num_ctls to 1 if CWB is enabled because in CWB, both the 389 + * writeback and real-time encoders must be driven by the same control 390 + * path 391 + */ 392 + if (top->cwb_enabled) 393 + num_ctls = 1; 394 + else 395 + num_ctls = top->num_intf; 386 396 387 397 needs_split_display = _dpu_rm_needs_split_display(top); 388 398
+2
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
··· 52 52 * @num_dspp: number of dspp blocks used 53 53 * @num_dsc: number of Display Stream Compression (DSC) blocks used 54 54 * @needs_cdm: indicates whether cdm block is needed for this display topology 55 + * @cwb_enabled: indicates whether CWB is enabled for this display topology 55 56 */ 56 57 struct msm_display_topology { 57 58 u32 num_lm; ··· 60 59 u32 num_dspp; 61 60 u32 num_dsc; 62 61 bool needs_cdm; 62 + bool cwb_enabled; 63 63 }; 64 64 65 65 int dpu_rm_init(struct drm_device *dev,