Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: enable pdb0 for hibernation on SRIOV
When switching to new GPU index after hibernation and then resume,
VRAM offset of each VRAM BO will be changed, and the cached gpu
addresses needed to updated.
This is to enable pdb0 and switch to use pdb0-based virtual gpu
address by default in amdgpu_bo_create_reserved(). since the virtual
addresses do not change, this can avoid the need to update all
cached gpu addresses all over the codebase.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Samuel Zhang <guoqing.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Samuel Zhang
and committed by
Alex Deucher
2f405eb4
18b66a6c
+40
-16
+26
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+26
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
···
38
38
#include <drm/drm_drv.h>
39
39
#include <drm/ttm/ttm_tt.h>
40
40
41
+
static const u64 four_gb = 0x100000000ULL;
42
+
43
+
bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev)
44
+
{
45
+
return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev);
46
+
}
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+
41
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/**
42
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* amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
43
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*
···
258
251
u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
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mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
260
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mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
261
-
mc->gart_start = hive_vram_end + 1;
254
+
/* node_segment_size may not 4GB aligned on SRIOV, align up is needed. */
255
+
mc->gart_start = ALIGN(hive_vram_end + 1, four_gb);
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
263
-
mc->fb_start = hive_vram_start;
264
-
mc->fb_end = hive_vram_end;
257
+
if (amdgpu_virt_xgmi_migrate_enabled(adev)) {
258
+
/* set mc->vram_start to 0 to switch the returned GPU address of
259
+
* amdgpu_bo_create_reserved() from FB aperture to GART aperture.
260
+
*/
261
+
mc->vram_start = 0;
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+
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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+
mc->visible_vram_size = min(mc->visible_vram_size, mc->real_vram_size);
264
+
} else {
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+
mc->fb_start = hive_vram_start;
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+
mc->fb_end = hive_vram_end;
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+
}
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
267
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mc->vram_end, mc->real_vram_size >> 20);
···
293
276
void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
294
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enum amdgpu_gart_placement gart_placement)
295
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{
296
-
const uint64_t four_gb = 0x100000000ULL;
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u64 size_af, size_bf;
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/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
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u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
···
1057
1041
*/
1058
1042
u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
1059
1043
u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
1060
-
u64 vram_addr = adev->vm_manager.vram_base_offset -
1061
-
adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1062
-
u64 vram_end = vram_addr + vram_size;
1044
+
u64 vram_addr, vram_end;
1063
1045
u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
1064
1046
int idx;
1065
1047
···
1069
1055
flags |= AMDGPU_PTE_SNOOPED;
1070
1056
flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
1071
1057
flags |= AMDGPU_PDE_PTE_FLAG(adev);
1058
+
1059
+
vram_addr = adev->vm_manager.vram_base_offset;
1060
+
if (!amdgpu_virt_xgmi_migrate_enabled(adev))
1061
+
vram_addr -= adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1062
+
vram_end = vram_addr + vram_size;
1072
1063
1073
1064
/* The first n PDE0 entries are used as PTE,
1074
1065
* pointing to vram
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+5
-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
+5
-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
···
74
74
static void gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev,
75
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uint32_t xcc_mask)
76
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{
77
+
uint64_t gart_start = amdgpu_virt_xgmi_migrate_enabled(adev) ?
78
+
adev->gmc.vram_start : adev->gmc.fb_start;
77
79
uint64_t pt_base;
78
80
int i;
79
81
···
93
91
if (adev->gmc.pdb0_bo) {
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WREG32_SOC15(GC, GET_INST(GC, i),
95
93
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
96
-
(u32)(adev->gmc.fb_start >> 12));
94
+
(u32)(gart_start >> 12));
97
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WREG32_SOC15(GC, GET_INST(GC, i),
98
96
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
99
-
(u32)(adev->gmc.fb_start >> 44));
97
+
(u32)(gart_start >> 44));
100
98
101
99
WREG32_SOC15(GC, GET_INST(GC, i),
102
100
regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
···
182
180
/* In the case squeezing vram into GART aperture, we don't use
183
181
* FB aperture and AGP aperture. Disable them.
184
182
*/
185
-
if (adev->gmc.pdb0_bo) {
183
+
if (adev->gmc.pdb0_bo && adev->gmc.xgmi.connected_to_cpu) {
186
184
WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_TOP, 0);
187
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WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
188
186
WREG32_SOC15(GC, GET_INST(GC, i), regMC_VM_AGP_TOP, 0);
+4
-4
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+4
-4
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
1722
1722
1723
1723
/* add the xgmi offset of the physical node */
1724
1724
base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1725
-
if (adev->gmc.xgmi.connected_to_cpu) {
1725
+
if (amdgpu_gmc_is_pdb0_enabled(adev)) {
1726
1726
amdgpu_gmc_sysvm_location(adev, mc);
1727
1727
} else {
1728
1728
amdgpu_gmc_vram_location(adev, mc, base);
···
1837
1837
return 0;
1838
1838
}
1839
1839
1840
-
if (adev->gmc.xgmi.connected_to_cpu) {
1840
+
if (amdgpu_gmc_is_pdb0_enabled(adev)) {
1841
1841
adev->gmc.vmid0_page_table_depth = 1;
1842
1842
adev->gmc.vmid0_page_table_block_size = 12;
1843
1843
} else {
···
1863
1863
if (r)
1864
1864
return r;
1865
1865
1866
-
if (adev->gmc.xgmi.connected_to_cpu)
1866
+
if (amdgpu_gmc_is_pdb0_enabled(adev))
1867
1867
r = amdgpu_gmc_pdb0_alloc(adev);
1868
1868
}
1869
1869
···
2363
2363
{
2364
2364
int r;
2365
2365
2366
-
if (adev->gmc.xgmi.connected_to_cpu)
2366
+
if (amdgpu_gmc_is_pdb0_enabled(adev))
2367
2367
amdgpu_gmc_init_pdb0(adev);
2368
2368
2369
2369
if (adev->gart.bo == NULL) {
+4
-2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
+4
-2
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
···
76
76
77
77
static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
78
78
{
79
+
uint64_t gart_start = amdgpu_virt_xgmi_migrate_enabled(adev) ?
80
+
adev->gmc.vram_start : adev->gmc.fb_start;
79
81
uint64_t pt_base;
80
82
u32 inst_mask;
81
83
int i;
···
97
95
if (adev->gmc.pdb0_bo) {
98
96
WREG32_SOC15(MMHUB, i,
99
97
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
100
-
(u32)(adev->gmc.fb_start >> 12));
98
+
(u32)(gart_start >> 12));
101
99
WREG32_SOC15(MMHUB, i,
102
100
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
103
-
(u32)(adev->gmc.fb_start >> 44));
101
+
(u32)(gart_start >> 44));
104
102
105
103
WREG32_SOC15(MMHUB, i,
106
104
regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,