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clk: renesas: rzg2l: Postpone updating priv->clks[]

Since the sibling data is filled after the priv->clks[] array entry is
populated, the first clock that is probed and has a sibling will
temporarily behave as its own sibling until its actual sibling is
populated. To avoid any issues, postpone updating priv->clks[] until after
the sibling is populated.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514090415.4098534-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Claudiu Beznea and committed by
Geert Uytterhoeven 2f96afdf 1bf4adbb

+4 -4
+4 -4
drivers/clk/renesas/rzg2l-cpg.c
··· 1389 1389 goto fail; 1390 1390 } 1391 1391 1392 - clk = clock->hw.clk; 1393 - dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 1394 - priv->clks[id] = clk; 1395 - 1396 1392 if (mod->is_coupled) { 1397 1393 struct mstp_clock *sibling; 1398 1394 ··· 1399 1403 sibling->sibling = clock; 1400 1404 } 1401 1405 } 1406 + 1407 + clk = clock->hw.clk; 1408 + dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); 1409 + priv->clks[id] = clk; 1402 1410 1403 1411 return; 1404 1412