Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/dp: Use the effective data rate for DP compressed BW calculation
Use intel_dp_effective_data_rate() to calculate the required link BW for
compressed streams on non-UHBR DP-SST links. This ensures that the BW is
calculated the same way for all DP output types and DSC/non-DSC modes,
during mode validation as well as during state computation.
This approach also allows for accounting with BW overhead due to DSC,
FEC being enabled on a link. Acounting for these will be added by
follow-up changes.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-10-imre.deak@intel.com
+16
-11
+16
-11
drivers/gpu/drm/i915/display/intel_dp.c
+16
-11
drivers/gpu/drm/i915/display/intel_dp.c
···
2026
2026
return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
2027
2027
}
2028
2028
2029
-
static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
2030
-
u32 lane_count, u32 mode_clock,
2031
-
enum intel_output_format output_format,
2032
-
int timeslots)
2029
+
static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp,
2030
+
int link_clock, int lane_count,
2031
+
int mode_clock, int mode_hdisplay,
2032
+
int dsc_slice_count, int link_bpp_x16,
2033
+
unsigned long bw_overhead_flags)
2033
2034
{
2034
-
u32 available_bw, required_bw;
2035
+
int available_bw;
2036
+
int required_bw;
2035
2037
2036
-
available_bw = (link_clock * lane_count * timeslots * 16) / 8;
2037
-
required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock));
2038
+
available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count);
2039
+
required_bw = intel_dp_link_required(link_clock, lane_count,
2040
+
mode_clock, mode_hdisplay,
2041
+
link_bpp_x16, bw_overhead_flags);
2038
2042
2039
2043
return available_bw >= required_bw;
2040
2044
}
···
2086
2082
if (ret)
2087
2083
continue;
2088
2084
} else {
2089
-
if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate,
2090
-
lane_count,
2085
+
if (!is_bw_sufficient_for_dsc_config(intel_dp,
2086
+
link_rate, lane_count,
2091
2087
adjusted_mode->crtc_clock,
2092
-
pipe_config->output_format,
2093
-
timeslots))
2088
+
adjusted_mode->hdisplay,
2089
+
pipe_config->dsc.slice_count,
2090
+
dsc_bpp_x16, 0))
2094
2091
continue;
2095
2092
}
2096
2093